SU1341682A1 - Dynamic shift register employing mis-transistors - Google Patents

Abstract

The invention relates to electronic engineering, in particular to microelectronics, and can be used as ring shift registers, sweep registers, scan pulse generators. The purpose of the invention is to increase the reliability of the dynamic shift register. The goal is achieved by the introduction of a second compensating transistor in each bit of the shift register, which acts on the gate of the memory transistor, prevents the formation of an active voltage divider by the memory and first compensating transistors. The first and second compensating transistors ensure the complete neutralization of randomly generated charges of interference simultaneously at the gate and the source of the storage transistor. 1 il. S. (L

Description

The invention relates to electronic engineering, in particular, to microelectronics, and can be used as ring shifts: from registers, sweep registers, and generators of scanning pulses.

The purpose of the invention is to increase the reliability of the dynamic shift register.

The drawing shows the electrical circuit of the device. The dynamic shift register contains the memorizing 1, commuting 2, controlling zeroing 3, the first 4 and second 5 compensating and key 6 transistors, the first 7 and second 8 clock buses and the power bus 9.

The register works as follows.

During the operation of the clock voltage on one of the clock buses (clock phases on the first 7 and second 8 clock buses are opposite), the switching transistor 2 is opened and the register input to the gate of the storage transistor 1, for example (n + 1) -th bit. or from the previous discharge. At the same time, even if the information corresponding to O is recorded, i.e. the gate of the storage transistor 1 receives a voltage below the threshold, the output of this bit is zeroed with the help of the zeroing control transistor 3. When recording 1, the output voltage of the previous transistor 1 goes through the memory transistor 1, which exceeds the threshold, The key transistor 2 serves to transmit the full amplitude of the clock voltage. On the output of the n-th bit, feedback is acting through the first 4 and second 5 compensating transistors. If in the previous one, the input of the (n + 2) -th bit, from which the feedback acts on the n-th bit, is recorded 1, then the input of the (n + 1) -th bit can only be written A. In this case, the feedback acts on the source and the gate of the storage transistor 1, therefore, the storage 1 and the first compensating 4 transistors cannot form an active voltage divider. At the entrance

(n + 1) -th voltage supplies the voltage exactly corresponding to O, or (if the gates of the first 4 and second 5 compensating transistors have a voltage below the threshold) 1.

Claims (1)

Invention Formula Dynamic shift register on DP-transistors, each bit of which contains memory, switching, zeroing control, compensating and key transistors, the first and second clock, the power bus, and the drains of the memory and to the earth transistors of odd bits and control gates zeroing and switching transistors of even gaps are connected to the first clock bus, and gates of the first switching and controlling zeroing transistors of odd bits, drains of memory and key transients the even-bit sources are connected to the second clock bus, the source of the storage transistor of each bit is connected to the drains of the first compensating and controlling resetting the transistors whose sources are connected to the power bus, the switching-transistor drain of each even-numbered discharge is connected to the source of the memory transistor of an odd-ness and is the input of the register bit, the storage gate of the transistor of each bit is connected to the source of the switching transistor and the gate of the key transistor shutter the first compensating transistor of odd-ness is connected to the source of the storage transistor of odd-ness, and the gate of the first compensating transistor of even-numbered connected to the source of the memory an even bit transistor, characterized in that, in order to increase the reliability of the operation of the dynamic shift register, in each the discharge is introduced the second compensating transistor, the source of which is connected to the power supply, and the drain is connected to the gate of the key transistor, the gates of the first and second compensating transistors are combined. P Editor L.Pcholinsk Compiled by A. Ershov Tehred L. Serdyukova Order 4441/55 Circulation 589Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d.4 / 5 Production and printing company, Uzhgorod, Projecto st., 4 n-i-1 ni-z Proofreader A.Zimokosov.