SU1635214A1 - Memory member - Google Patents

Description

one

(21) 4687147/24

(22) 05.05.89

(46) 03/15/91. Bup. 10 (72) A.M.Kopytov, A.G. Solod and V.O.Kireev

(53) 681.327.66 (088.8)

(56) IEEE Journal of Solid State Circuits, V. SC-22, No. 5, 1987, p.712-720, fig.2.

IEEE Journal of Solid State Circuits, V. SC-22, No. 5, 1987, p. 712-720, fig. four.

(54) MEMORY ELEMENT

(57) The invention relates to computing and can be applied in various memory devices, registers, stacks, RAM.

The aim of the invention is to increase the reliability of the memory element. This is achieved in that the memory element contains a key element on the two switching transistors 10, 11 and the setting transistor 12 with corresponding links. In the recording mode, the transistors 10, 11 are closed by the signal on the bus 13, and the transistor 12 is opened. This ensures the closed state of both transistors of the first inverter 1, which leads to the absence of a through current in the memory element. As a result, information is written to the memory element independently of the ratios of the resistances of the transistor channels of the memory elements. 1 il.

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The invention relates to computing and can be used in various storage devices, registers, stacks, RAM.

The aim of the invention is to increase the reliability of the memory element.

The drawing shows an electrical circuit of the memory element.

The memory element contains a trigger on CMPS transistors, made on two inverters 1, 2, two sampling elements on MOS transistors 3, 4, two bit buses 5, 6, two tires 7, 8 samples, a bus 9 of zero potential, the first and the second commuting transistors 10, 11, the installation

transistor 12, write bus 13, power bus 14.

The memory element is two-port.

The dual port memory element operates as follows.

In the read mode, a potential O is applied to the bus 13. At the same time, the p-switched switching transistors 10, 11 are open and the first and second inverters 1, 2 are connected to the power supply terminal 14. The sampling bus 7 is excited one by one at the same time, and the information written in the memory element is read to the bit bus 5 of the first port. At another address, a sample bus 8 is excited.

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the second port and through the transistor 4 of the bottom of the yin 6 of the second port is connected to the output of the first inverter 1, the potential recorded in the element is set on it.

Thus, information is read from a memory element at one address on the first port and from another memory element at another address on the second port. When busses 7j 8 of the first and second ports are driven to one common address, the bit buses 5.6 of the first and second ports are connected to the output of the first inverter 1 via transistors 3, 4 and the information recorded in the memory element is read to the bit buses 5, 6 first and second ports.

In the recording mode, a positive write pulse is applied to the bus 13. When this, the p-channel switching transistors 10, 11 are closed and the outputs of the first and second inverters 1, 2 are disconnected from the power fault 14. The transistor 12 opens, and the output level of the second inverter 2 is set to O. The output of the first inverter 1 is also disconnected from the bus 9, i.e. is in the third state.

When bus 7 is energized, the output of the first port of the first inverter 1 is connected via the transistor 3 of the first port to the bit bus 5 of the first port and the output of the first inverter 1 records the potential of the bit bus 5, while no current flows through during recording, because the first inverter 1 is in the third state. It is possible, however, to excite the sampling bus 8 of the second port at the same address, to read the information from the bit bus 5 of the first port to the second bus 6 of the second port.

Let us consider in more detail the entry of level 1 and O into the memory element. Suppose that level 1 is recorded at the output of the first inverter 1. The output of the second inverter 2 is connected to the bus 9 via the open transistor 12. The output of the first inverter 1 is in the third state, and through the transistor 3 of the sample, the output of the first inverter 1 is connected to the discharge bus 5 of the first port, which is in state 1, is charged by the parasitic output capacitance of the first

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Inverter 1 to 1. At the end of the write pulse, the switching transistors 10 and 11 open and connect the trigger power inputs to the power bus 14, the transistor 12 closes, the output of the first inverter 1 is connected to the power bus 14 and through the open p-channel transistor of the first inverter 1 to its The output is set to a voltage equal to the supply voltage.

Suppose that the level O is recorded at the output of the first inverter 1. The output of the second inverter 2 is connected to the bus 9 via the open transistor 12, the output of the first inverter 1 is in the third state, and the parasitic capacitance of the output of the first inverter 1 to O is discharged. switching transistors 10 and 11 open and connect the load transistors of the first and second inverters 1, 2 to the power supply bus 14, close the transistor 12, the output of the first and second inverters 1, 2 connect to the power bus 14 and open p-channels The transistors of the first and second inverters 1, 2 are charged by the parasitic capacitance of the first and second inverters 1, 2. The recording strobe is shorter than the sampling time of tires 7, 8, therefore, the output of the first inverter 1 is connected to the capacity of discharge bus 5 or 6, two orders of magnitude higher than the parasitic capacitance of the output of the second inverter 2. The output of the second inverter 2 is not charged to the power supply voltage level 1-2, the output voltage of the first inverter 1 is set equal to the level O, the positive reverse circuit closes in communication, obespechivayu- conductive x storing information in the memory element.

Claims (1)

Invention Formula five 0 five 0 A memory element containing a trigger on a CMDF transistor, two sampling elements on MDP transistors, the sources of which are connected to the first output of the trigger, the gates are connected to the first and second buses of the sample of the memory element, and the drains to the first and second bits memory element, respectively, the input potential of zero trigger connected to the zero potential bus of the memory element, characterized in that, in order to increase the reliability of the memory element, it contains a key element on two switching MOS transistors and an installation MOS transistor, the source and drain of which are connected to the zero potential input and the second output Trigger, respectively, the gate of the transistor installation is connected to the write bus of the memory element and connected to the gates of the switching transistors, whose sources are connected to the power bus of the memory element, and the drains are connected to the first and second power inputs of the trigger, respectively.