SU1285533A1 - Memory register - Google Patents

Abstract

The invention relates to digital computing and can be used in random access memory devices. The aim of the invention is to improve the noise immunity of a memory cell when a voltage is applied to an address input. To achieve this goal, two storage capacitors have been inserted into the memory cell, which are connected between the address input of the memory cell and the nodal points of the memory cell trigger. Due to the capacitors, the action of the signal at the address input increases the potential of the open MOSFET transistor trigger, which leads to a decrease in the effective resistance of the transistor and a decrease in the probability of a false switch trigger. 1 il. (L

Description

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The invention relates to digital computing and can be used in random access memory devices.

The purpose of the invention is to improve the immunity of the memory cell under the action of voltage at the address input.

The drawing is a diagram of a memory cell.

The memory cell contains a trigger consisting of key MOS transistors 1 and 2 and load resistors 3 and A, switching elements made on MOS transistors 5 and 6, and charging elements made on capacitors 7 and 8. On The diagram also shows the power bus 9, the potential-zero bus 10, the address input 11, the first 12 and the second 13 bit inputs.

The memory cell operates as follows.

In the storage mode, a potential is established on the address line 11 that is lower than the threshold voltage of the transistors 5 and 6.

To write information into the memory cell, it is necessary to set the potential on the bit inputs 12 and 13 of the input information: on one - low (approximately zero) and on the other - high (approximately potential of the power source + U) t

transistors 5 and 6 are opened to a high level and a low potential is set in a trigger node connected to a low-potential discharge input, and a high potential is set in another node.

In this case, the trigger switches to the appropriate state.

When reading the information of the potentiator, when the potential of the drain switch of transistor 1 is low and the potential of transistor 2 is high. In this case, a readout signal appears at the discharge input 12 as a result of the current flowing through the series-connected open transistors 5 and 1.

This increases the drain potential of transistor 1, which can lead to a false trigger switch. By introducing a capacitor 8, the drain potential of transistor 2 and the gate of transistor 1 increases, which leads to a decrease in the effective resistance of transistor 1 in comparison with the known device and to a decrease in the likelihood of a false switching trigger. The presence of capacitor 7 does not increase the drain potential of transistor 1 due to the very short constant discharge time of capacitor 7 through the open transistor 1, while the drain potential of transistor 2 decreases slowly because the discharge of capacitor 8 occurs through resistor 4, having a lot of resistance.

Claims (1)

Invention Formula The memory cell containing the trigger and the first and second switching elements, each of which is made on the VDP transistor, the sources of the VDP transistors are connected to the corresponding trigger inputs / outputs, the drains are the corresponding bit inputs, and the gates are the address input cells a memory that differs from the fact that, in order to increase the noise immunity, the first and second charging elements are introduced into it, each of which is made of condensation al at the address input is changed so 45 / torus, the pins of which are connected to same as when recording. Bit inputs at the beginning of the readout usually have a high potential. Let us consider the source and the source of the MOSFET of the corresponding switching element.