SU1370765A1 - Asynchronous pulse distributor - Google Patents

Abstract

The invention relates to computing and can be used in switching and data transmission systems. The purpose of the invention is to simplify the device. An asynchronous pulse distributor (ARI) contains cells 1 in each bit, each of which consists of trigger 2 and AND-NE element 3. Trigger 2 contains load elements (NE) 4 and MIS transistors 5-7. The element AND-3 contains MOSFETs 8-10 and NE 11. The ARI also contains a power bus 12, a common bus 13, a bus 15 of the installation, an output bus 17. The ARI has a simple electrical circuit. 1 il.

Description

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The invention relates to automation and computing and can be used in switching and data transmission systems.

The aim of the invention is to simplify the device by reducing the number of transistors in the discharge cell of the distributor by completing the trigger of each cell on the MOS transistors and directly connecting the drains of the MOS transistors of opposite arms to the triggers of the neighboring cells.

The drawing shows a schematic diagram of an asynchronous distributor.

The device contains cells 1 in each bit, each of which consists of trigger 2 and an AND-NEZ element. Trigger 2 contains two load elements 4 and three MIS transistors 5-7. The element AND NOT 3 contains three MOS transistors 8-10 and the load element 1J.

The MOS transistor7 of the trigger 2 of the i-th cell 1 is connected to the serial connection point of the first 5 and second 6 MOS transistors of the trigger 2 of the subsequent (i + 1) -th cell 1.

The device works as follows.

The installation (i-1) is made by feeding to its bus 15 the installation of a Zero logic level (low potential). In this case, 1 is written to the trigger 2 of this cell, i.e. The MOS transistors 5 and 8 are closed, after which the MOS transistor 7 is opened, and at the gate of the MOS transistor 6 a low potential appears, which closes this transistor, resulting in an output bus 17

(1 -) th cell remains high potential as long as the low potential is maintained on its installation bus 15.

Once on the bus J 5 mouth

The load elements 4 of the trigger 2 25 of the new (1-1) -th cell J are switched off between the power supply bus 12 and the drain of the first 5 and third 7 MOS transistors of the trigger 2, respectively.

The load elements 4 and 11 can also be implemented as J1-transistors. The triggers 2 and the elements of the AND-3 are connected between the power bus 12 and the common bus 13. The first 5 and second 6 MOS transistors of the trigger 2 are connected in series, with the source of the second MOS transistor 6 connected to the common bus 13.

The gate of the first MOS transistor 5, which is the first input of the trigger, is connected to the first input 14 of the NAND element 3 and is connected to the bus 15 of the installation of the corresponding cell 1.

The gate of the second MOS transistor 6 of the trigger 2, which is the second input of the trigger 2, is connected to the drain of the third MOS transistor 7. The drain of the first MOS transistor 5, which is the first output of the trigger 2, is connected to the gate of the third MOS transistor 7, which is the third input of the trigger 2, and connected to the second input 16 of the element AND-NOT 3. The output bus 17 of the i-th cell, which is the output of the element AND-HE 3 of this cell, is connected to the bus 1 5 of the next (i + 1) cell 1 and to the third input 18 of the element AND-NOT 3 of the previous (i-1) cell 1. Source of the third

The high potential opening of the MIS transistor 8, the low potential will be set on the output bus J7 of this cell 1 and will go to the bus 15 of the next ith cell 1, as a result of which the trigger 2 of this cell will also be written 1.

Next, the (.1 + J) -th cell 1 will be installed, the process of which is similar to that considered. It is significant that as long as in trigger 2 the 1st one

one

recorded

H

in the same trig

A ger 2 (i) cell 1 cannot be written down 1. Indeed, there is a high potential at the source of the MOS transistor 7, which maintains a high potential at the drain of the same MOS transistor 6 of the flip-flop 2. Therefore, the feed on the J5 bus il) cell 1 low

potential before the i-cell transitions to the initial state (i.e., trigger 2 of this cell will be recorded o), will only cause the

low potential on a drain of a MOSFET 8.

The elements AND-NOT 3 neighboring cells J form a trigger, so the output tires 17 of these elements cannot have low potential at the same time, i.e. low potential. on the output bus of the 17th i-th cell 1, it maintains a high potential for output power

not 17 (il) -ft cells 1. Therefore, supplying the installation signal (il) -fl cell 1 on bus 15 of the installation does not cause a low potential on the output bus 17 of this cell and a change in the signal on the output bus 17 (i-1) - th cells.

Thus, the re-installation of (1-1) -th cell 1 is carried out only after i-cell 1 has returned to its original state.

Consequently, when re-initiating the asynchronous distributor operation before the previous cycle of its operation is completed, the subsequent wave of cell settings will not reach the previous one, since there will always be at least one cell in the initial state between them, which ensures the correct functioning of the distributor software mode.

In the proposed asynchronous distributor, each cell requires nine MOS transistors for its implementation, whereas in the distributor-prototype - ten MOS transistors. Thus, the proposed technical solution saves equipment by 10%, which achieves the goal.

Claims (1)

Invention Formula An asynchronous pulse distributor containing, in each discharge, cells, each of which consists of 0 five the trigger and the NAND element, the first input of the trigger is connected to the first input of the NAND element and connected to the installation bus of the same cell, the first output of the trigger is connected to the third input of the trigger and the second input of the NAND element, and the second output of the trigger is connected to the second trigger input, the first and second trigger inputs are connected according to the AND scheme, the output bus of the i-th cell, which is the output of the AND-NOT element, is connected to the installation bus of the subsequent (i + J) -th cell and the third input of the AND- element NOT a previous {1-1) cell, characterized in that, in order to simplify , the trigger of each cell is made in the form of two load elements and three SchTs1 transistors, the gates of the first and second MOS transistors, which are connected in series, are respectively the first and second trigger inputs, and the load elements are connected between the power rail and the drain of the first and The third MOS transistors, which are respectively the first and second outputs of the trigger, 0 the gate of the third MOS transistor is the third input of the trigger, the source is connected to the serial connection point ervogo and second MIS transistors subsequent flip-flop (1 + 1) th cell and the source of the second MIS transistor is connected to a trigger common bus. 0 five five (Ul)