SU1314374A1 - Device for processing multichannel analog signals - Google Patents

Abstract

This invention relates to a magnetic iaiiiicH. The purpose of the invention is to reduce the consumption of magnetic media. From the selected address b.yuka And operational sludge; TP code d.1N || НЫ de (served on the cable input ;: adder 12, and on the other the input of the CNG; units of the NINA from the output of the trigger 13. interconnected with the sensor 1-; smsr. Maximum code value from b By the current 4 ope: - the tivable memory is compared in the comparator 15 with r (K iuiM value of the transducer code 8. prsva.-p1nruyuya the value of the nose code, 1 ode 1 o: h cut cat ;; arator 15 n; ihch :: h n memory b. yuka 14. (the termination signal of the d .. h is formed at the output of node 18 of the coincidence as rez. 1yat. logical research institute of signals of the determinant 17 of the bullet), the code values and the determinant of the 16th unit About the value of the code. At the end of the defect, through the mode setting unit 10, the mode 1 is switched on in one of the 19 I.-1 and 20 memory blocks and the number of the drop is fixed, the number of the maximum and the defect maximum 1 square SS tel. 4 .: CAS J

Description

The invention relates to a magnetic recording technique, namely, to signal processing devices prior to recording on magnetic media, and can be used primarily for signal processing in flaw detection.

The purpose of the invention is to reduce the consumption of magnetic media.

The drawing shows a block diagram of the device.

The device "will block control unit 1, calculate 2 defect lengths, determinant 3 maxima, signal, detector 4 ends of defect. A, counter 5 channel numbers, analog switch 6, calculator 7 level, noise, analog-digital converter 8 , the first determinant 9 of a nonzero code value, the mode setting unit 10, the RAM block 11, the adder 12, the trigger 13, the RAM block 14, a comparator 15, the second determinant 16 of the nonzero code value, the determinant 7 of the zero code value, the node 18 , blocks 19 and 20 memorization, accumulation tion unit 21, magnetic recording, and a clock generator 22.

The device works as follows.

From counter 5, the channel number code is fed to the address inputs of the analog switch 6, to which, in accordance with the code, the input bus of the channel is connected to the input of the analog-digital converter 8, in the latter the signal corresponding to the level of the noise calculated in the calculator 2 is subtracted. The differential signal in the form of a code is fed to the first determinant 9 of nonzero code values, the output of which through block 10 starts recording information into blocks 11 and 14 of the working memory. From the selected address of the operative memory block 11, the defect length code is applied to one of the inputs of the adder 12, to the second input of which a signal "1 from the output of the trigger 13 interconnected with the sensor of the flaw detector meter is supplied. The sum of the previous code value and "1" is remembered again in block I. Addition "1 continues until the signal at the input of the analog-digital converter 8 exceeds the noise level. The maximum code value from the RAM block 14 is compared in the comparator 15 with the current code value of the converter 8. The prevailing code value of the analog-to-digital converter 8 through the comparator 15 is entered into the memory of the block 14. The signal of the end of the defect is formed at the output of the node 18 coincidence as a result of the logical multiplying the signals of the determinant 17 of the zero code value and the determinant of the 16 non-zero code value.

At the end of the defect, through block 10, the recording mode is activated in one of the

VNIIPI Order 2009/51 Circulation 590 Subscription

Production and Production Enterprise, Uzhgorod, yj. Design. four

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19 or 20 memorize and record the channel number, length, and defect maximum value. Upon completion of the recording, the memory locations of blocks 11 and 14 are zeroed.

The device operates cyclically through all channels of signals.

After the memory cells of the block 19 (20) are filled, the information is overwritten on the magnetic carrier of the magnetic recording apparatus 21.

Claims (1)

Invention Formula A device for processing multi-channel analog signals, containing an analog-to-digital converter, whose input is connected to the output of an analog switch, a solver level transmitter, whose output is connected to an analog-digital converter subtracting input, input buses connected to the inputs of an analog switch and a noise level calculator, blocks Memories, the outputs of which are connected to the apparatus of magnetic recording, and the tact generator connected to the input of the channel number counter, the outputs of which are connected to the address inputs The signals of the analog switch, characterized in that, in order to reduce the consumption of magnetic media, it is equipped with a trigger, the input of which is connected to a path measurement sensor, an adder, the first input of which is connected to the output of the trigger, the first and second operational memory blocks, zero and non-zero code values, a coincidence node and a mode setting block; the first input of the comparator, the first input of the first operative memory block, the zero determiner input are connected to the output of the analog-digital converter code values and the input of the first determinant of nonzero code values, the output of the first RAM block is connected to the input of the second determinant of nonzero code values and the second input of the comparator, the output of which is connected to the second input of the first RAM block, the output of the determinant of zero code values and the output of the second the determinant of nonzero code values are connected to the inputs of the coincidence node; the output of the latter and the output of the first determinant of nonzero code values are connected to the inputs of the mode setting block, the output of which o is connected to the control inputs of the first and second RAM blocks, the outputs of the latter are connected to the inputs of the memory blocks, the second input of the adder is connected to a separate output of the second operational memory block whose input is connected to the output of the adder, and the address inputs of the RAM blocks are connected to the outputs of the channel number counter.