SU1307568A1 - Device for counting difference of two pulse sequences - Google Patents

Abstract

The invention relates to the automation of technological processes and can be used to control the difference in angular as well as linear movement of two objects. The aim of the invention is to enhance the functionality while improving functional reliability. The device contains sensors I, 2 movements, element OR 14, element 11, reversible counter 10, comparison block 16, relay 18, maximum difference setting adjuster 17, trigger 12. To achieve the goal, blocks 3, 4, transformations, blocks are entered into the device 5, 6, 7, 8 memory, the element And 13, the control unit 9, the element OR-NOT 19, the generator 15 pulses, formed a new functional connection. The device provides the ability to determine the difference between both asynchronous pulse sequences and synchronous ones. In addition, the sign of the difference of the sequence of pulses is determined and the counting direction is changed using the control unit 9, which is important when using this device in control systems for the synchronous movement of objects. 4 il. about fugues. R

Description

The invention relates to the automation of technological processes and can be used to control the difference in angular as well as linear movement of two objects. Such objects may be two bodies rotating in the forward or reverse direction around one axis or linearly moving in the forward or reverse direction.

The aim of the invention is to enhance the functionality while improving functional reliability.

FIG. 1 shows a functional block diagram of the device; in fig. 2 - functional logic circuit of the memory unit; in fig. 3 - functional logic circuit of the control unit; in fig. 4 - timing charts of the device.

The device contains the first 1 and second 2 motion sensors, the outputs of which are connected respectively to the inputs of the first 3 and second 4 conversion units. The first and second outputs of the first conversion unit 3 are connected to the first inputs of the first 5 and second 6 memory blocks, the first and second outputs of the second conversion unit 4 are connected respectively to the first inputs of the third 7 and fourth 8 memory blocks. The first outputs of the memory blocks 5, 6, 7 and 8 are connected respectively to the first, second, third and fourth inputs of the control unit 9, the first and second outputs of which are connected to the forward and reverse counting inputs of the reversing counter 10, respectively, the clock input of which is connected to the output of the first element And 11, the first input of which is connected to the output of the trigger 12, the counting input of which is connected to the output of the second element And 13, the first input of which is connected to the output of the element OR 14, and the second to the second input of the element 11 and the generator 15 Pulse. Each of the inputs of the OR 14 element is connected to the first output of the corresponding memory block 5-8. The bit outputs of the counter 10 are connected to the corresponding bits of the first input of the comparator unit 16, the second input of which is connected to the output of the maximum difference setting unit 17, and the output to the input of the relay 18. Each of the bit outputs of the counter 10 is connected to the corresponding input of the OR element 19, the output of which is connected to the third input of the control unit 9, the third output of which is connected to the output sign thickness 20.

Each of blocks 5-8 of memory contains an element OR 21, the first input of which is connected to the first input of the memory unit, and the second - to the output of the element AND 22, the first input of which is connected to the first output of the memory unit and through the inverter 23 to the second the output of the memory block and the output of the element NAND 24. The second input

And 22 is connected to the second input of the memory block, the third and fourth inputs of which are connected respectively to the first and second inputs of the AND-24 element, the third input of which is connected to the output of the trigger 25, the counting input of which is connected to the output of the OR 21 element.

The control block 9 contains four elements OR 26-29, elements AND 30-33, two elements AND-NO 34 and 35 and trigger 36.

 The first inputs of the AND elements — HE 34 and 35 are connected to the third input of the control unit 9, the first and fifth inputs of which are connected to the first inputs of the OR elements 26 and 27, respectively, the second inputs

g of which are connected respectively to the fourth and second inputs of the control unit 9. The outputs of the elements OR 26 and 27 are connected to the second inputs of the elements AND-NOT 34 and 35 and the first inputs of the elements AND 30 33. The second inputs of the elements 30 and 33 are connected to the direct output of the trigger 36 and the output 20 of the control unit 9, the second inputs elements And 31 and 32 are connected to the inverse output of the trigger 36, the H-input of which is connected to the output of the element AND-NOT 34. The outputs of the elements 30 and 31 are connected to

 the inputs of the OR element 28, the output of which is connected to the first output of the control unit, the second output of which is connected to the output of the element OR 29, the first and second inputs of which are connected to the outputs of the AND elements 32 and 33, respectively.

FIG. 4a, b show time diagrams of the signals at the outputs of blocks 3 and 4; in FIG. 4c, d — at the first outputs of memory blocks 5 and 7, in FIG. 4 d, e, g, 3 - at the outputs, elements 14 and 13, generator 15 and trigger 12, respectively, in FIG. 4 and, k, l - at the clock input and the inputs of the forward and reverse counting of the counter 10, respectively, in FIG. 4 m - on the output sign bus 20.

The device works as follows.

 Let both controlled objects move in the forward direction. At the same time, from the outputs of sensors 1 and 2, information is transferred in the form of cyclic Gre codes to the inputs of blocks 3 and 4 of conversion, respectively. In the converters, the directions of movement of the objects are determined and pulses are formed, the number of which is directly proportional to the movements of the first and second objects. And when moving the first and second

0 objects in the forward direction pulses appear at the first outputs, and when moving in the opposite direction - at the second outputs of blocks 3 and 4. Then the pulses arrive at the inputs of the corresponding blocks 5–8 of the memory. In this case, there can be three options5 for the time shift of pulses at the outputs of blocks i and 2 relative to each other: the falling edge of the pulse at the output of block 1 is ahead of the falling edge of the pulse at the output

block 2; the leading edge of the pulse at the output of block 1 lags behind the trailing edge of the pulse at the output of block 2; the leading edge of the pulse at the output of block 1 coincides with the trailing edge of the pulse at the output of block 2.

Let the pulses come from the first outputs of blocks 3 and 4. In the first variant, the received pulse is memorized by memory block 5, and then by block 7. At the first output of memory block 5, the signal "1" appears, and at the second output - signal "O which blocks the appearance of "1 at the first outputs of blocks 6, 7 and 8 of memory. The second outputs of memory blocks 6–8 are stored “1. Thus, "1 appears only at the first output of block 5, arriving at the first input of control block 9 and the first input of the OR 14 element. From the output of the OR 14" element 1 is transmitted to the input of the AND 13 element, allowing the pulse from the generator 15 to pass trigger 12. The generator pulse switches trigger 12, and at its output it is set to "1. The next impulse of the generator passes through the element 11 to the clock input of the reversible counter 10 and to the inputs of the blocks 5–8 of memory. At this time, the signal "1" is generated at the first output of the control unit 9, which is fed to the input of the direct count of the counter 10. Thus, at the end of the pulse at the output of the And 11 element, the contents of the counter 10 change to +. the trigger 12 returns to the initial state, thereby prohibiting the further passage of the pulses of the generator 15 through the element II, the memory block 6 returns to the initial state. The generator pulse acts selectively on the memory blocks. It returns to the initial state only that block of memory, at the output of which I have an i. As soon as “1” appears on the second output of memory block 5, i.e. the memory block 7 is unlocked, “1” appears on the first output of block 7, and “1 on the first outputs of the blocks 5, 6 and 8. Next, “1 passes through the element OR 14 to the element AND 13, allowing the pulse generator 15 to pass to the counting input of the trigger 12. At the output of the trigger 12 again,“ I, allowing the next pulse of the generator through the element 11. At this time point “1 at the output of block 7 causes the appearance of“ 1 at the second output of block 9 and, thereby switching the counter to the “Subtraction. Now the impulse propagated to the clock input of counter 10 causes a change in the contents of counter 10 to - I.

In the second embodiment, the device operates in the same way, with the only difference that the memory block 7 is serviced first, and then the block 5.

In the third embodiment, "I may occur either on the first output of block 5, or

five

0 5 0 5

five

0

0

at the first output of block 7, depending on which memory block has a longer delay. Regardless of this, both memory units will be serviced, and an account will not be entered into the result of the account. The pulse frequency of the generator is chosen to be greater than D - 3, where Hz is the maximum of the two pulse frequency at the output of converters 3 and 4.

A difference sign is generated at the output 20 of the control unit 9 as follows. If a zero code is present at the output of the reverse counter I), then the output of the OR-NOT 19 element is "1. In this case, the appearance of “1 at output 20 corresponds to the sign“ - (-. The appearance of “1 at the first output of block 6 or 7 causes the appearance of“ O at output 20, which corresponds to the sign “-.

When moving objects in the near-direction, the device works in a similar way, but there are used b / w 6 and 8 memory.

In case the absolute value of the difference of sequences of pulses reaches the maximum value specified by the setting device 17, the relay 18 is activated, which by its contacts turns off the drives of both objects (not shown).

The memory block (Fig. 2) operates as follows. The impulse arriving at the first input passes through the element or 21 to the input of the trigger 25. The trigger switches, and at its output is set to "1, causing, if there is" 1 at the second, third and fourth inputs, the appearance of "O at the output of the element And 22 and "1 at the output of the inverter 23. Passing an impulse under these conditions through the second input e; 1 of the terminal AND 22 returns 1 trigger 25 and the entire memory block to its initial state.

Thus, in the proposed device, it is possible to determine the difference between both asynchronous and synchronous impu sequences. 1st. In addition, the sign of the difference of the sequence of pulses is determined and the counting direction is changed using the control unit 9, which is important when using this device in control systems for synchronous movement of the bypass. In such systems, the chgebraic difference in the displacements of objects' dzzuch is used to influence one of the objects in order to make its movement synchronous with the second. Two pulses simultaneously arriving at the inputs of the corresponding memory blocks correspond to two pulses successively arriving at the input of a reversible counter. Consequently, the meter does not fail, which ensures high reliability of the device.

Claims (1)

Claims The difference counting device of two pulse sequences, containing the first and second displacement sensors, the OR element, the first AND element, the reversible counter, the comparison unit, the output of which is connected to the relay input, the maximum difference setting device and the trigger, characterized in that functionality while improving functional reliability, the first and second conversion blocks, the first, second, third and fourth blocks of memory, the second And element, the control block the OR-NOT element and the pulse generator, the outputs of the first and second displacement sensors are connected to the inputs of the first and second conversion units, the first outputs of which are connected to the first inputs of the first and third memory blocks, respectively, and the second outputs respectively to the first inputs of the second and the fourth memory blocks, the first inputs of the first, second, third and fourth memory blocks are connected respectively to the first, second, third and fourth inputs of the OR element and the first, second, third and fourth fifth inputs of the control unit, the first and second inputs connected respectively to the inputs of the forward and reverse bills down counter, a clock input coupled to inputs. the first, second, third and fourth memory blocks and the output of the first element And, the first input of which is connected to the trigger output, the counting input of which is connected to the output of the second element And, the first input of which is connected to the first input of the first 0 of the AND element and the output of the pulse generator, and the second with the output of the OR element, with the second inputs of the first, second, third and fourth memory blocks connected to the third inputs of the third, fourth, first and second memory blocks, respectively, and the fourth inputs of the fourth, respectively, the third, second and first memory blocks, the outputs of the bits of the reversible counter are connected to the corresponding inputs of the OR element - NOT and the corresponding bits of the first input of the comparator unit, the second input of which is connected to the output Occupancy maximum difference, wherein an output of OR - is coupled to the clock input of the control unit, whose third output is connected to sign five output bus. , 5 (6.7, c) fpuz. 2 fus.J -lf- lshshbppzdzhdy  g J 5 5 7 Is 9 / g1 and: At W 5j Is; jqjiDJHjnjiiiunjnnilMili I I I I I i 4 „С11ЙCtLJTLDULL.  , 21li. M .flii f hhf t -sT VNIIPI Order 1402/54 Circulation 902 Subscription Production and printing equipment, Uzhgorod, y, p. Four Project, 4 Circulation 902 Subscription Riet, Uzhgorod, y, p. Paoektyan,