SU1305727A1 - Device for simulating hysteresis loop - Google Patents

Abstract

The invention relates to information-measuring equipment, as well as radio engineering and computer technology. The purpose of the invention is to increase the accuracy of modeling the hysteresis loop by taking into account the appearance of residual magnetization of the material. The device contains code-controlled amplifiers 1 and 17, adder 3, comparators 4, 5, 6, 7, reversible counter 9, trigger 10, keys 11 and 16, storage unit 12, analog-to-digital converters 13, 14, divider 15, switch 18, selector channels 19, 21, pulse shaper 20, inverter 22. The hysteresis loop approximation by straight sections, taking into account the phenomenon of residual magnetization, is performed by changing the transmission coefficients of the coding-controlled amplifiers and storing the maximum value of the output signal. It is possible to model a family of increasing hysteresis loops, 4 Il. with y (L with SP yu Figure 1

Description

one

The invention relates to computing technology and can be used in the development of testing instruments, as well as in radio engineering.

The purpose of the invention is to improve the accuracy of modeling the hysteresis loop due to the occurrence of the residual magnetization of the material.

13057272

its output is connected to the third input of the selector 19 channels and the second input of the selector 21 channels.

Three outputs of the selector 19 channels are connected respectively to the three control inputs of the code-controlled

the amplifier, the first output of the selector 19 channels through the inverter 22 is connected with the control input of the key

On (i, 1 is represented by the structure fO 16, In the selector of 21 channels first and

a circuit for simulating a hysteresis loop; FIG. 2 is a graph of approximation of the hysteresis loop by straight sections; Fig, 3 is a functional diagram of the channel selector; Fig. 4 shows a table of its output states when simulating different parts of the hysteresis loop.

The device comprises a code-controlled amplifier 1, the input 2 of which is the input of the device. The output of the code-controlled amplifier 1 is connected: to the first input of the adder 3, the output of which is connected to the first inputs of the comparators A-7, and also is the output 8 of the device. The output of comparator 6 is connected with the summing input of the reversible counter 9 and with the first input of the trigger 10, and the output of the comparator is the 1st subtractive input of the counter and the second inputs of the trigger. The output of the reversible counter 9 through the key 11 is connected to the input of the storage unit 12, and is also connected to the input of the digital-to-analog converter 13,

The output of the D / A converter 13 is connected to the second inputs of the comparator in 6 and 7, and the output of the storage unit 12 to the input of the D / A converter 14, The output of the latter is connected to the input of the divider 15, to the second input of the comparator 5 and through the key 16 - from the input of the code-controlled amplifier 17, the output of which is connected to the second input of the adder 3. The output of the comparator 5 is connected to the first input of the switch 35 of FIG 2, Let us give the equations describing the hysteresis loop by sections (Fig 2):

In section 3-0-1, the hysteresis loop is described by the equation

(one)

ivyk ..

where and

Bbix K.

45

UBX device output voltage;

the first gain of the code-controlled amplifier 1 is the input voltage of the device,

Lp plots 1-2 and 3-4 are valid 18, the output of which is associated with the first 50 o equation

19 channel selector input. Output Ug K, giv. U, (2)

trigger 10 is connected to the input of the form, where K is the second gain factor of the pulse generator 20, the output of the driver of the pulse generator 20 is connected to the up55

code-controlled amplifier 1, equalizing the input of the key 11, the second input of the selector 19 channels and the first input of the selector 21 channels. In addition, the output of the divider 15 is connected to the second input of the comparator 4, which

Uj -KOI Ugj ,,,, дкс J

(2.1)

where k

Q, is the first gain factor of the code-controlled amplifier 7 5

the amplifier, the first output of the selector 19 channels through the inverter 22 is connected with the control input of the key

the second outputs are connected respectively to the first and second control inputs of the code-controlled amplifier 17. A voltage equal to a logical one is applied to the input 23 of the switch 18.

The 19 canap selector consists of three 1K-flip-flops and three elements OR ,,

The input 24 of the selector 19 channels connected to the input I of the trigger 25 to the first inputs of the elements IZH 26 and 27, the Input 28 is connected to the input I of the trigger 29, the first input of the element

OR 30 and the second input of the element OR 27. Input 31 is connected to input I of trigger 32 and the second inputs of elements OR 26 and 30, the outputs of the elements OR are connected to inputs To the corresponding triggers, the direct outputs 33-35 of which are selector outputs 19 channels,

The hysteresis loop is approximated by straight sections, as shown in

Fig ,, 2, Let us present the equations describing the hysteresis loop by sections (Fig 2):

In section 3-0-1, the hysteresis loop is described by the equation

(one)

ivyk ..

de and

Bbix K.

UBX device output voltage;

the first gain of the code-controlled amplifier 1 input voltage device the second gain

code-controlled amplifier 1, Uj -KOI Ugj ,,,, dcs J

(2.1)

where k

Q, is the first gain factor of the code-controlled amplifier 7 5

and.

- the maximum value of the output of the MQKC

running voltage in a simulated hysteresis loop.

Sections 2-3 and 4-1 are satisfied with the equation

. (3)

where K is the third gain factor of the code-controlled amplifier 1,

   (3.1)

where K is the second gain of the code-controlled amplifier 17. The voltage 1) is determined from

and

and

out

TO.

where Kjj is the division factor of divider 15.

The values of the coefficients K ,, K, Kj, KQI, Og o are determined by the required shape of the hysteresis loop and must be selected before the start of the simulation. K factors

Kj and K,

and K and K are implemented respectively in code controlled amplifiers 1 and 17 as the ratio of the values of the resistors in the feedback circuit of the operational amplifiers to the values of the resistors connected to the inverse inputs of the operational amplifiers. The coefficient Kp is expressed in terms of the values of the divider resistors 15. The values of the coefficients K, satisfy the relation

K and Kj should

k, k, k ,,.

40

The simulation of the hysteresis loop begins with the reproduction of the main magnetization curve (Fig. 2, section 0-1). For this, it is necessary in the code-controlled amplifier 1 (Fig. 1) to set the gain factor K |, which is accomplished by moving the switch 18 to the lower position. In this case, from the input 23 to the input 24 (FIG. 3) of the channel selector 19, as it increases (Uebtx accord (1) also increases), a comparator 6 is triggered, which turns on the reversing counter 9 in the summation mode. At the moment when the voltage U passes through a maximum, the comparator 7 is activated, the output signal of which switches the reversible counter 9 from the summation mode to the subtraction mode and changes the state of the trigger 10 to the opposite. Trigger 10, in its turn, starts the shaper of 20 pulses. The latter generates a resolution signal for closing the key 1, and the information from the reversible counter 9 is recorded in the storage unit 12. The same signal, supplied to the second input of the channel selector 19, switches the gain factor of the code-controlled amplifier I with K | on kj. Using the same signal, which arrives at the first input of the selector 21 channels, the gain factor K is set in the code-controlled amplifier 17, and the voltage and is output to the second input

there is a voltage equal to the logical value “, fairly expressed, as a result of gp.“. ™ “.“ „a ™ 2), therefore, as U decreases,

unit. As a result of the triggering of the trigger 25, a logical unit appears at its output 33, which is fed to the control input of the coding control

to zero at the output 8 of the device, the voltage remains, in the formation and output of which participates

, storage unit 12, DAC 14, key

amplifier 1 and sets ", x", -,

. ,,, 16, code control amplifier 17 and

its gain is equal to K,.

Then switch 18 goes to Y P

top position according to the scheme. The device is ready to work.

15

20

25

40

 ) Voltage 1} is applied to the input 2 of the code-controlled amplifier 1, for example, an increasing one (Fig. 2, section 0-1) in this section describes

5 with impaction (1). If the voltage Ug starts to decrease as the voltage increases, then U (, b, y should change over section 1-2 (Fig. 2). To do this, it is necessary to determine the maximum voltage Ugbi, which is carried out using the analog-digital converter (ADC) next balancing. The ADC includes two comparators 6 and, a reversible counter 9 and a DAC 13. The first inputs of the comparators 6 and 7 are energized by Ug, and at the comparator 7 it is shifted by 0.5 quantization steps due to the adjustment the comparator bias, and the second inputs - the signal from the DAC 13, which converts to 9 d-down counter to an analog voltage.

When increasing (Uebtx according to (1) also increases), the comparator 6 is triggered, which includes the reversible counter 9 in the summation mode. At the moment when the voltage U goes over the maximum, the comparator 7 is triggered, the output signal of which switches the reversible counter 9 from summation mode to subtraction mode and changes the state of trigger 10 to the opposite. The trigger 10, in turn, starts the shaper 20 pulses. The latter generates a resolution signal for closing the key 11, and the information from the reversible counter 9 is recorded in the storage unit 12. The same signal, fed to the second input of the channel selector 19, switches the gain factor of the code-controlled amplifier I with K | on kj. Using the same signal, which is fed to the first input of the selector 21 channels, the gain factor K is set in the code-controlled amplifier 17, and the voltage and is output to the second input of the adder

thirty

35

   ,, rightly express- ™ 2), therefore, as U decreases,

to zero at the output 8 of the device, the voltage remains, in the formation and output of which participates

Then to the input 2 of the co-controlled Force 1 is fed an increasing

five

voltage U of a different polarity (negative). In this case, the decreasing} of its output goes to the first input of the comparator A, to the second input of which the voltage U is given, defined by the expression (4), the voltage is generated using the storage unit 12, the DAC 14 and the divider 15. The comparator 4 is activated when the condition U Here, a command is generated which arrives at the third input of the channel selector 19 and at the second input of the channel selector 21, as a result. the gains of the coding equipotential amplifiers 1 and 17 optK to Kg and with

switchable from o, ia ko,.

Having reached the maximum negative value (vol. 3, fig. 2), the april should then be measured along the 3-4 hysteresis loop. The moment of transition to the new section is determined by the ADC of the follow-up balancing. In this case, the compiler 6 is triggered, which changes the mode of operation of the reversible counter 9 s subtraction to summation and flips trigger 10 to the opposite state. The trigger 10 generates a command for the driver 20 pulses. Only in this case, the gain of the code-controlled amplifier 1 changes from K to and the code-controlled amplifier 17 changes from K to K. After performing the above operations for Ugj, the expression (2) is valid and when UB decreases; to zero on the output 8 of the device remains ,,

As the positive voltage increases, Ugy Ugjji decreases (to t, 4, fig. 2). At this moment, condition Wgt is fulfilled, which triggers comparator 4 and performs switching.

Further Ug) (increases to m. 1, fig, 2) and, having reached the maximum J, decreases again. The maximum determines the ADC of the following equilibration. A new cycle of modeling the hysteresis loop is started, and the operation of the device is repeated.

20

25

thirty

35

40

five

The transition to a new hysteresis loop is carried out along the main magnetization curve (section 0--1 or 0-3, fig 2) if the condition

11 S 1T

Bblx output max This triggers the comparator 6,

a shaping signal that through ne 3057276

switch 8 is fed to the first input of the selector) 9 channels. At the first output of the channel selector 19, the enabling signal appears, which is fed to the first control input of the code-controlled amplifier 1, setting its gain to K ,, The same signal through the inverter 22

Sh

kt 50

M exits key 16 and opens it,

disconnecting the code-controlled amplifier 17 from the second input of the adder 3, As a result of performing the above operations, satisfies expression (1) 5. simulating the main curve

tS magnetization. Condition in this

the moment of the device corresponds to point 1 (Fig. 2),

The operation of the channel selector 19 is performed in the following way. First, from the input 23 of the device, through the switch 18 to the input 24 of the channel selector 19, the signal of the logical unit is inserted. It enters input I of trigger 25 and sets it

25 direct output 33 to the state of a logical unit. The same command is sent through the elements OR 26 and 27 to the K-inputs of the flip-flops 29 and 32, setting at their direct outputs 34 and 35 logical

30 zero. Upon termination of the signal, the voltage of the logical unit is located at output 33. connected to the first control input of the codooperating control unit 1 and through inverter 22 - with

35 by the control input of the key 16. Then, from the driver of the 20 pulses, to the input 28, a pulse signal arrives, which is transmitted to the input I of the trigger 29 and through the IPI 30 and 27 elements to

40 inputs K of triggers 25 and 32. In this case, triggers 25 and 29 change their state, and the logical unit is set at output 34, which is connected to the second control input

5 code-controlled amplifier 1.

0

five

When the comparator 4 is triggered, the voltage of the logical unit is applied to input 3I, and a logic zero is output at the output 34 of the trigger 29, and a logical unit is output at the output 35 of the flip-flop 32. Output 35 is connected to the third control input, the controllable amplifier 1, After changes in the state of these triggers at input 31 — a logical unit remains, since comparator 4 is running al. However, if the input to trigger 32 is received by a command with input 7

yes 28 or 24, the latter is transferred to the opposite state. At this moment, the information from the reversible counter 9 through the public key 11 is recorded in the storage unit 12, and from the DAC 14 and the divider 15, another voltage Uj will be output to the second input of the comparator 4. This will lead to the fact that at the input 31, due to the return of the comparator 4 to the initial state, a logical zero signal will be present. Further, the operation of the channel selector is repeated.

Claims (1)

The invention The device for modeling a hysteresis loop containing two comparators, an inverter, a storage unit, an adder, the output of which is the output of a device, characterized in that, in order to improve the accuracy of the simulation, the third and fourth crimpers are inserted into the device, two co-controlled amplifier, reversible counter, trigger, pulse shaper, two digital-to-analog converters, a voltage divider, two channel selectors, two keys and a switch, with the information input of the first controller; amplifier is the information input of the device, and its output is connected to the first input of the adder, the output of the adder is connected to the first inputs of the comparators one through four, the output of the second comparator is connected to the summing input of the reversible counter and to the first input of the trigger, and the output of the third comparator connected to the subtracting input of the reversible counter and to the second trigger input, the output of the reversing counter is connected to the digital 057278 the input of the first digital-to-analog converter and via the first key - with the address input of the storage unit; the output of the first digital-analog converter is connected to the second inputs of the second and third comparators, and the output of the storage unit is connected to the digital input of the second digital-analog converter, fO the output of which is connected to the second input of the fourth comparator, to the input of the voltage divider and through the second key to the information input of the second к controllable amplifier whose output is connected to the second input of the adder, and the output of the voltage divider is connected to the second input of the first comparator, the output of the fourth comparator is connected to the first informational input of the switch connected by the output to the first input of the first channel selector; the direct output of the trigger through the pulse shaper is connected to the second input of the first the first channel selector, the first input of the second channel selector and the control input of the first key; the output of the first comparator is connected to the third input of the first channel selector 30 and the second input of the second channel selector, the outputs of the first channel selector are connected to the corresponding control inputs of the first code-controlled amplifier, while the first 35 output of the first channel selector is connected via an inverter to the control input of the second key, and the first and second outputs of the second channel selector connected respectively to the first and The -40 second control inputs of the second code-controlled amplifier, the second information input of the switch is connected to the voltage setting bus of the logical unit. FIG. g 3 Rig.CH Compiled by T. Tolstobrova Editor V, Danko Tehred L. Serdyukova Proofreader A. Obruchar Order 1455/49 Tir.azh 673. Subscription VNIIGSh State Committee of the USSR for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4