SU1298770A1 - Device for checking parameters - Google Patents

Abstract

The invention relates to the field of automation and information-measuring equipment and can be used in information-measuring systems and information-computer complexes of automated process control systems. The purpose of the invention is to improve the noise immunity of the device. The goal is achieved by the fact that, in a device for controlling parameters, containing an indicator 3, the input of which is connected to the output of the first memory block 7, the control unit 2, the input of which is connected to the output of the pulse generator 1, the switch 4, the information inputs of which are corresponding the device inputs, the control input is connected to the first output of control unit 2, and the output of switch 4 to the input of delay element 6, the I: element is additionally added, the second memory block 9, the parameter view selector 8 with their connections. This ensures the operation of the device in a continuous cyclic mode and control parameters of any kind of sensors. Controlled events are recorded according to the results of the analysis for two cycles of interrogation of sensors, which eliminates false registration when external interference with a duration of less than one cycle of interrogation of all sensors occurs. 2 hp f-ly, 4 ill. i (L y from 00

Description

The invention relates to automation and information-measuring equipment and can be used in information-measuring systems (IMS) and information-computing complexes (IWC) of automated process control systems (ASCTP),

The purpose of the invention is to expand the field of application by working with different sensors and increasing the noise immunity of the device.

FIG. 1 shows a diagram of the device, FIG. 2 is a temporal diagram in FIG. 3 and 4 are diagrams of the control unit and the parameter view selector, respectively.

The device (Fig. 1) contains a pulse generator 1, a control unit 2, an indicator 3, a switch 4, sensors 5, a delay element 6, a first memory block 7, a parameter view selector 8, a second memory block 9, And element 10.

The control unit (Fig. 3) contains the first counter 11, the decoder 12, the second counter 13.

The parameter type selector (Fig. 4) contains a decoder 14, an AND 15 key 16, an ADC 17, a comparison node 18, a memory node 19, an OR element 20.

The device works as follows.

Pulse signals from the output of the pulse generator 1 are fed to the input of the counter 11 of the control unit 2. Counter 11 counts the pulses into three and, together with the decoder 12, is a pulse distributor. From the first output of the decoder 12, each first of the three pulses is fed to the input of the counter 13, from the second output each second pulse is fed to the second output of the control unit 2 and is a read cycle fed to the input of the memory block 9. From the third output of the decoder 12, a third pulse arrives at the third output of the control unit 2 and is a write clock input to the block 9. The output of the counter 13 is the first output of the control unit 2 and is the address code of the polled sensor arriving at the control the input of the switch 4, which, in a constant cyclic mode, alternately connects the sensors 5 through the delay element 6

to the interrogator 8. The address code of the polled sensor is fed to the input of the decoder 14, which is part of the villages; € 8. When interrogating the analog

A sensor appears at the first output of the decoder 14, which is fed to the control input of the key 16 and the control input of the ADC 17. At the same time, the analog signal through the key 16 is fed to the input of the ADC 17j, where analog-to-digital conversion and output to the first input of the node are performed 18 comparisons, to the second input of which from the output of the memory node 19 enters

setpoint code corresponding to the address of the polled sensor entering the input of node 19; If the value of the analog signal connected to A1SCH17 is greater than the value of the setpoint (i.e. the parameter monitored using an analogue sensor exceeds the allowable rate), then the output of the node 18 comparison, a signal appears which, through

the element SH-20 arrives at the output of the selector 8 of the parameter type.

During polling (a signal appears at the second output of the decoder 14, arriving at the first input of an element 15, the second input of which receives a signal from a discrete sensor. In case the discrete sensor has triggered (for example, an emergency protection signal), that

The second input element And 15 receives a signal 1 and the output of the element 15 also generates a signal 1, which through the element OR 20 enters the output of the selector 8.

The delay element 6 ensures the elimination of failures from the influence of switching processes within switch 4,

The frequency of the pulses of the pulse generator 1 is chosen such that

the polling time of all sensors 5 would be less than the time until the occurrence of the second event caused by the first.

Address signals generated on

The first output of the control unit 2 is received at the address input of the memory unit 9, to the information flow of which, from the output of the selector 8, an information signal is received, which simultaneously arrives at the second input of the element 10. And then a signal is generated at the second output of the control unit 2 address entered on

The third input of block 9, from the output of which the read signal is fed to the first input of element I 1. From the timing diagram (Fig 2) and the functional diagram of the device (Fig. 1) it can be seen that during the initial appearance at the output of the selector 8 of the parameter type to any address of the logic signal 1, the latter is recorded in block 9, but it does not pass to the output of element I 10 and to the second output of the device.

If in the second polling cycle at the same address a logical signal 1 is formed at the output of the selector 8, then a logical signal 1 is generated at the read cycle at the output of the element 10 and the second output of the device, which is fed to the input of the memory block 7 as a signal authorizing the entry of the address and the display.

In the case of memory block 7, the latter is locked to record any new information (for example, using

marker bit). If during the second 25 reading and writing of the second memory block

respectively.

2. The device of claim 1, in which the polling of the sensors at the same address does not generate a logical signal 1 at the output of the parameter selector 8, then the output of the element 10 and the output of the device does not pass.

Thus, any external disturbance that may cause a false logic signal at the output of the selector 8 is not reflected at the output of the device and on the display. Only reliable information, which arises at the output of the selector 8 for two cycles, will be fixed by the device. This is achieved in comparison with the known device with high noise immunity of the device, which is very significant when using the device in an automated process control system, the level of external (industrial) interference for which in most cases is significant.

Invention Formula

1. A device for controlling parameters, containing an indicator whose input is connected to the output of the first memory block, a control unit whose input is connected to the output of a pulse generator, a switch, the information inputs of which are the corresponding inputs of the device, a control input connected to the first

that the control unit contains the first and second

30 counters and a decoder, the first output of which through the second counter is connected to the first output of the bdrka, and the second and third outputs of the decoder are the second and third outputs

35, respectively, the input of the first counter is the input of the block, the output is connected to the input of the decoder.

40

45

50

55

3. The device according to claim 1, 1 and 2, in that the parameter view selector comprises a decoder, a key, an analog-to-digital converter, an AND element, a comparison node, a memory node, and an OR element, the output of which is the output of the selector, the inputs of the decoder and the memory node are the address input of the selector, the first input of the AND element and the information input of the key are the information input of the selector, the first output of the decoder is connected to the control inputs of the key and the analog-digital converter, the Information input of which is connected to the output key a, the second output of the decoder is connected to the second input of the AND element, the output of which is connected to the first input of the OR element, the outputs of the analog-digital converter and the node by the left of the control unit, and the output of the switch is connected to the input of the delay element, application by working with different sensors and improving the noise immunity of the device, an element I, a second memory block and a parameter view selector, whose information input is connected to the output of the delay element, are addressable The input is connected to the first output of the control unit, the address inputs of the first and second memory blocks and the first output of the device, the output of the parameter view selector is connected to the information input of the second memory block and the first input of the And element, the second input of which is connected to the output of the second memory block The output of the element I is connected to the control input of the first memory block and the second output of the device, the second and third outputs of the control block are connected to the inputs

that the control unit contains the first and second

counters and a decoder, the first output of which through the second counter is connected to the first output of the bdrka, and the second and third outputs of the decoder are the second and third outputs

The block, respectively, the input of the first counter is the input of the block, the output is connected to the input of the decoder.

0

five

0

five

3. The device according to claim 1, 1 and 2, in that the parameter view selector comprises a decoder, a key, an analog-to-digital converter, an AND element, a comparison node, a memory node, and an OR element, the output of which is the output of the selector, the inputs of the decoder and the memory node are the address input of the selector, the first input of the AND element and the information input of the key are the information input of the selector, the first output of the decoder is connected to the control inputs of the key and the analog-digital converter, the Information input of which is connected to the output key a, the second output of the decoder is connected to the second input of the AND element, the output of which is connected to the first input of the OR element, the outputs of the analog-digital converter and the memory node are connected to the corresponding inputs of the comparison node, the output of which

connected to the second input element OR.

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Lanite {B1.2-S)

Schip (in. З З)

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Editor E. Papp

Compiled by I. Alekseev

Tehred M.Morgental Proofreader I.Erdeyi

Order 1349 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35 Raushsk nab. 4/5

Production and printing company, Uzhgorod, st. Project, 4

Claims (3)

Claim 1. A device for monitoring parameters, comprising an indicator, the input of which is connected to the output of the first memory block, a control unit, the input of which is connected to the output of the pulse generator, a switch, the information inputs of which are the corresponding inputs of the device, the control input is connected to the first output of the control unit, and the output of the switch is connected to the input of the delay element, characterized in that, in order to expand the scope by working with different sensors and increasing the noise immunity of the device, the And element is introduced, the second memory block and a parameter type selector, the information input of which is connected to the output of the delay element, the address input is connected to the first output of the control unit, the address inputs of the first and second memory blocks and the first output of the device, the output of the parameter type selector is connected to the information input the second memory unit and the first input of the And element, the second input of which is connected to the output of the second memory unit, the output of the And element is connected to the control input of the first memory unit and the second output of the device, the second and third outputs of the control unit are connected to the read and write inputs of the second memory unit, respectively. 2. The device pop. 1, characterized in that the control unit contains the first and second counters and a decoder, the first output of which is connected through the second counter to the first output of the receiver, and the second and third outputs of the decoder are the second and third outputs of the block, respectively, the input of the first counter is the input of the block, the output connected to the decoder input. 3. The device according to claim 1, wherein the type selector of the parameter contains a decoder, a key, an analog-to-digital converter, an AND element, a comparison node, a memory node and an OR element, the output of which is the output of the selector, the inputs of the decoder and of the memory node are the address input of the selector, the first input of the element And and the information input of the key are the information input of the selector, the first output of the decoder is connected to the control inputs of the key and the analog-to-digital converter, the information input of which is connected to the output of the key , the second output of the decoder is connected to the second input of the AND element, · the output of which is connected to the first input of the OR element, the outputs of the analog-digital converter and the memory unit5 are connected to the corresponding inputs of the comparison node, the output of which is connected to the second input of the OR element.