SU1297242A1 - Clock synchronizing device with variable correction effect - Google Patents

Abstract

The invention relates to telecommunications and simplifies the device. The device contains a synchronization signal shaper 1 with variable correction effect, phase discriminator 2, averaging block 3, correction block (KB) 4, frequency divider block 5, master oscillator (RG) 6. Shaper 1 contains an adder 7 modulo two. differentiating blocks (dB) 8, 9, AND-NE 10, elements AND 11, 12. Pulses from ЗГ 6 arrive at the clock input of CB 4. In the absence of signals at the outputs of the elements 11, 12, the pulse frequency at the output of KB 4 has average value. With the signals at the output of the element 11, the pulse frequency decreases, and with the signals at the output of the element 12 increases. In block 5 of the frequency dividers, the pulse frequency is reduced. In the presence of a phase discrepancy of inter-. For an input signal and pulses of the divider 14, pulses appear at the output of adder 7, the duration of which corresponds to the magnitude of the error. For each informational packet, two mismatch pulses are generated — along the front and along the slice. Phase discriminator 2 determines the sign of the phase difference between information pulses and c & (L ND: About 4 ND

Description

pulses from the inverse output of the divider 13. Depending on the sign of the divergence on the acc. the input of the averaging unit 3 receives bursts of pulses from

The invention relates to telecommunications and can be used in the transmission of discrete information for clock synchronization, received signals.

The aim of the invention is to simplify the device.

Figure 1 shows a structural electrical circuit of a clock synchronization device with a variable corrective effect; Figures 2 to 5 show signal timing diagrams explaining the operation of a clock synchronization device with a variable correction effect, respectively, for cases: the lag (in the phase of the clock oscillation relative to the information signals of the input signal) by Cf-t90, the lag by if 90, the advance (in clock phase relative to the information signals of the input signal) by (90 °, advance by tf 90.

A clock synchronization device with a variable correction effect contains a shaper 1 synchronizing signals with a variable correction effect, a phase discriminator 2 (made in the form of a 1K trigger) averaging unit 3, a correction unit 4, a unit 5 of frequency dividers specifying oscillator 6.

. Shaper I synchronization signals with variable correction. the effect contains the adder 7 modulo two, the first and second differentiating blocks 8 and 9, the element AND NOT 10, the first and second elements AND 11, 12.

The unit 5 of the frequency dividers contains the first and second frequency dividers 13, 14.

The clock synchronization device with a variable correction effect works as follows.

The pulses from the output of the master oscillator 6 (Fig.2l-5l) arrive at

ЗГ 6. КБ 4 changes the period of pulse transmission, so that the phase divergence is reduced. 2 hp f-ly, 5 ill.

clock input correction unit 4 (figure 1). In the absence of signals at the outputs of the first and second elements And 11 and 12, the pulse frequency at the output of the correction unit 4 has an average value, with signals at the output of the first element And 1, the pulse frequency decreases, and with signals at the output of the second element, And 12. The pulses from the output of the correction block 4 are fed to the block 5 of the frequency dividers, where their tracking frequency is reduced to a value of 1 / T, where T is the elementary sending duration of the input signal.

From the direct output of the first divider 13, the pulses (FIGS. 2e-5e) are fed to the second divider 14 with a division factor of 2, and to the second differentiating unit 9, and from the inverse output of the first divider 13, the pulses (FIGS. 2d-5d) at the first input of the phase discriminator 2.

At the second input of the adder 7 (shaper 1), the information of the input signal is received (Fig. 2a-5a), and at the first input - the pulses from the second divider 14 (Fig. 2b-5b). If there is a phase difference between these signals, pulses appear at the output of adder 7 (Figs. 2c-5c), the duration of which corresponds to the magnitude of the error. For each information parcel, two mismatch pulses are generated (on the front and on the slice), i.e. bipolar correction is performed. The signals from the first and second outputs of the phase discriminator 2 (Figures 2i-5 and Figures 2k-5k) determine the sign of the phase ff between the information pulse and the first divider pulses} 3 Depending on the sign of the phase difference on one of the inputs averaged The first or second output of the synchronizing signal of driver 1 (fig.2n-5n, fig.2m-5m) of the pulse packet with the frequency of the master oscillator 6 is received from the first block 3. The number of pulses in the packet is proportional to the phase difference. The averaging unit 3 averages the pulses arriving at its inputs corresponding to the phase mismatches, and outputs signals to the correction unit 4, which changes the pulse period so that the magnitude of the phase difference decreases. This ends the first synchronization cycle.

A new cycle of phase mismatch analysis is performed, and after detecting its magnitude and sign, the next adjustment of the clock cycle follows. The magnitude of the correction zone, within which the correction effect has a constant value, is determined by the pulse repetition period of the master oscillator 6.

The operation of the former 1 is carried out as follows.

The output signal of the adder 7 is fed to the first inputs of the first and second elements 11, 12 and the input of the first differentiating unit 8, which generates a short pulse on the front of the signal coming from the adder 7. The second differentiating unit 9 produces short pulses on the front of the signal coming from My output of the first divider 13.

In the lag mode (FIGS. 2 and 3), the pulses from the outputs of the first and second differentiating units 8 and 9 (FIG. 2d, 3d, 2g, 3g) do not coincide in time and the potential at the output of the AND-10 element is 1 ( high level). By a cut of the pulses coming from the inverse output of the first divider 13 (fig.2d-5d), the first input of the phase discriminator is set to the first output of the signal 1. At the same time, the first and second inputs of the first and second elements 11 and 12 are pulsed from the adder 7 and the pulses from the master oscillator 6, and the third input of the first element And 11 comes from the phase discriminator 2 potential 1. At the output of the first element

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And I1, a packet of pulses is formed (from the output of the master oscillator 6), the number of which is proportional to the duration of the signal from the adder 7 (FIG. 2N, 3N). At the output of the second element I 12, in this case, the potential is O, since its third input receives a signal with a level O from phase discriminator 2.

In the advanced mode (Fig. 4 and 5), the pulses from the outputs of the first and BTOpojp differentiating units 8 and 9 (Fig. 4d, 5d, 4g, 5g) coincide in time and at the output of the element AND-NE 10, (Fig. 4h, 5h ) at the same time, short pulses appear, which form at the first output of the phase discriminator 2, made in the IK flip-flop, a potential O (fig. 4n, 5n). At the output of the second element 12, the third input receives a signal from the second output of phase discriminator 2, a burst of pulses (FIG. 4m, 5m) is formed, the number of which is proportional to the duration of the signal from the adder 7. The potential at the output of the first element And 11 is equal to O (fign, 5n).

Claims (3)

Claim 1. A clock synchronization device with a variable correction effect, containing a series-connected master oscillator, a correction unit and a frequency divider unit, as well as an averaging unit, a synchronization signal generator with a variable correction effect and a phase discriminator, the first and second KOTopqro outputs via a variable correction signal generator The fect and averaging unit are connected respectively to the first and second control inputs of the correction unit, and the output The frequency divider unit is connected to the first input of the phase discriminator, the output of the frequency divider unit being the device output, characterized in that, in order to simplify the device, the first and second additional outputs of the frequency divider unit and the output of the master oscillator are connected respectively to the first, second and to the third clock inputs of the synchronization signal generator with a variable correction effect, the additional output of the synchronization signal of which is connected to the second input of the phase discriminator, the shaper of synchronizing signals with pexeHiaiM correctional effect consists of a modulo-two adder connected in series, the first differentiating unit and the NAND element as well as the first and second And elements and the second differentiating unit whose output is connected to the second input of the And -NO, the output of the modulo two adder is connected to the combined first inputs of the first and second elements AND, the input of the second differentiating unit and the first and second inputs of the modulo two are the with the first and second clock inputs and the information input of the variable timing generator, respectively, the combined second inputs of the first and second And elements are the third clock input of the variable correction effect generator, the third inputs of the first and second And elements are respectively the first and second inputs of the synchronizing signal of the generator of synchronizing signals from changes The first and second elements of the AND and the NAND element are respectively the first, second, and additional outputs of the clock signal, and the information input of the clock generator with the variable correction effect is the input of the device. 2. The device according to claim 1, about tl and - the fact that the phase discriminator is made in the form of T.K.-trigger, and the K-input of the 1K-trigger Connected to the common power wire, the clock and set inputs of the IK trigger are the first and second inputs of the phase discriminator, respectively, and the inverse and direct outputs of the 1K trigger are the first and second outputs of the phase discriminator. 3. The device according to claim 1, characterized in that the frequency divider unit is designed as a series of first and second frequency dividers connected in series, the input, the direct and inverse outputs of the first frequency divider being the input, output and the first additional output of the unit, respectively the frequency dividers, and the direct output of the second frequency divider is the second additional output of the frequency divider unit. TO; L tsch1111SCH | 1 | Ynish1111Ts | Sh1N11111111i; | (П11111 nam I111 3 FIG. HHL -iLujjz: riiir ryHllllirilllfllllllffllliiinillillllKimiUKilllilllll m // P1I11I1 SHShPSh lirililHd IHIIIIH L JTL L FIG. five