RU1818619C - Device for measuring time-and-frequency signals - Google Patents

Abstract

The device relates to the field of synchronization of spaced hours over a radio channel and can be used in single time systems for transmitting reference frequencies and accurate time signals. The goal is to increase the accuracy of the transmission of time signals. The device comprises a master oscillator 1, a time keeper 2, a reference frequency shaper 3, a pilot signal shaper 4, a signal switch 5, an envelope extraction unit 6, first and second phase shifters 7, 8, a carrier frequency shaper 9, a modulator 10, a radio transmitter 11, antenna 12, antenna current transformer 13, third phase shifter 14, comparator 15, control unit 16, first inverter 17, first and second keys 18.19, time signal driver 20,

Description

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with

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the first frequency divider 21, the first and second blocks 22. 23 delays, a multiplier 24, a second frequency divider 25, a reference signal shaper 26, a first adder 27 modulo two, a third delay unit 28, a second adder 29 modulo two, an integrator 30, a second inverter 31, third key 32. The device allows to increase the accuracy of the transmission of time signals with an envelope of arbitrary shape due to the introduction of phase locked loops emitted

The invention relates to a technique for synchronizing a diversity clock over a radio channel and can be used in single time systems for transmitting reference frequencies and accurate time signals.

The goal is to increase the accuracy of the transmission of time signals.

Fig. 1 is a structural electrical diagram of a device for transmitting time-frequency signals; figure 2-5 is a timing diagram of his work.

A device for transmitting time-frequency signals includes a master oscillator 1, a time keeper 2, a reference frequency shaper 3, a pilot signal shaper 4, a signal switch 5, an envelope extraction unit 6, first and second phase shifters 7, 8, a carrier frequency shaper 9, a module torus 10, radio transmitter 11, antenna 12, antenna current transformer 13, third phase shifter 14, comparator 15, control unit 1.6, first inverter 17, first and second keys 18.19, driver 20 of the time signals, first frequency divider 21, first and second blocks 22, 23 delays, multiplier 24, second frequency divider 25, reference driver 26, first adder 27 modulo two, third delay unit 28, second adder 29 modulo two. integrator 30, second inverter 31, third and fourth keys 32, 33.

A device for transmitting time-frequency signals operates as follows.

The signal of the master oscillator 1 enters through the second phase shifter 8 to the former 9, where the oscillation of the carrier frequency is generated. When a constant potential is applied to the control input of the modulator 10, a continuous signal is supplied from the modulator 10 to the input of the radio transmitter 11 and is emitted by the antenna 12. From the output of the winding

time signals relative to a reference signal synchronized by the pulses of the time keeper and automatically phased according to the results of the piloting of the envelope extraction unit of the radio signal. Automatically adjusting the phase of the carrier frequency during emission of the pulsed part of the program eliminates envelope stabilization errors caused by the layers of the carrier phase. 5 ill.

the antenna transformer 13 inductively coupled to the antenna 12, the emitted signal is fed to the signal input of the comparator 15, the reference input of which is supplied

5 a reference signal of the same frequency from the driver 3 of the reference frequency. The reference signal is generated from the frequency of the master oscillator 1, supplied to one input, and synchronized by the pulses of the keeper 2

10 times to the other input of the driver 3. In the presence of a phase mismatch between the emitted and the reference oscillations, signals are generated that go to the control inputs of the second phase 15 of the corrector 8 through the public key 33. Under the action of the mismatch signals, the phase is adjusted to the phase shift value that the signal receives when passing through the formation chains to exit from

0 antenna 12. At the end of the adjustment, the phase of the emitted signal is zero.

During continuous frequency emission, the envelope extracting unit 6 representing

5 is a synchronous detector with a low-pass filter, by supplying a pilot signal from the driver 4 through the switch 5 signals to the signal input of unit 6. In the driver 4 pilot signal high-frequency

0, the oscillation coming from the reference frequency driver 3 is modulated by a rectangular signal with a duty cycle of two (meander), coming from the second output of the keeper 2 times to the control input

35 former 4 (Fig. 2,6). The signal delay in the driver 4 is zero, therefore, the pilot signal is synchronized with the scale of the custodian 2 time (Fig.2, a). From the output of block 6, to the reference input of which

40, the high-frequency signal from the reference frequency driver 3 is delayed (due to the presence of a low-pass filter in the block 6) the envelope of the pilot signal (Fig. 2 c) is supplied to the first adder 27 modulo two. On dr-35

each adder 27 input is supplied from the former 26 by a reference signal (Fig. 2d) generated from pulses of the frequency divider 25. Under the action of the signal of the block 16, which is supplied to the control input of the shaper 26, a square wave reference signal is generated during piloting with a frequency equal to the envelope frequency of the pilot signal. The phase of the reference signal may be varied by the first phase shifter 7.

The key 32 at the output of the first adder 27 modulo two and the inverter 31 is controlled by the output signal of the second adder 29 modulo two, the inputs of which receive reference signals from the output of the driver 26 and from the third delay unit 28. The value of the delay of the reference signal in block 28 is equal to the duration of the chip or half the period.

When adding modulo two main (figure 2, d) and half-period (figure 2, e) delayed meander signals at the control input of the third key 32, there is a single (unlocking) potential (figure 2, e), therefore, direct (figure 2, g) and inverse (figure 2, h) the results of adding in the first adder modulo two envelopes of the pilot signal (figure 2, c) and the reference signal (figure 2, d) are received through the public key 32 to an integrator 30, which is zeroed at the installation input by the edges of the reference signal (Fig. 2d). In the integrator 30, the average value for the period of the sum of the result of the addition is determined and the mismatch signals generated at the inputs of the keys 18, 19 are generated. The keys are controlled by the control unit 16 by supplying direct and inverse potentials to the control inputs. In pilot mode, the key 19 is locked and the key 18 is open, and the mismatch signals from the integrator 30 to the control inputs of the first phase shifter 7. In the diagram of Fig. 2d, the reference signal is in the intermediate position when its adjustment is not completed. The corresponding mismatch signals at the first output of the integrator 30 are shown as pulses of negative polarity with a dot (Fig. 2, and). Under the action of pulses arriving at the first control input of the phase shifter 7, the reference signal shifts to the left to the equilibrium position (Fig. 2, k), while the average sum of the direct (Fig. 2, l) and inverse (Fig. 2, m) ) of the signals in the integrator 30 becomes zero (Fig. 2, n), and the tuning of the reference signal ends.

When the reference signal is mixed to the left of the equilibrium position, the mismatch signals occur at the second output of the integrator 30 and are fed to the second control input of the phase shifter 7 to shift the reference signal to the right.

At the end of the continuous frequency emission, the key 18 is locked by the signal from the control unit 16 and the piloting of the envelope extraction unit 6 is completed. The reference signal is fixed in the equilibrium position (Fig. 2, k), while the front of the coupled signal is ahead of the setup pulse (Fig. 2, a) by half the duration of the elementary packet minus the delay of the envelope of the pilot signal in the envelope extraction unit.

5 When pulse time signals are emitted, the output of the antenna transformer winding 13 is connected to the signal input of the envelope extraction unit 6 using the signal switch 5.

0 At the same time, the outputs of the integrator 80 through the second switch 19 is connected to the control inputs of the third phase shifter 14. The compensation of the phase mismatch "relative to the reference signal is carried out by

5 of the shift of the modulating signal at the control input of the modulator 10. Time signals (Fig. 3c) are generated from pulses of the frequency divider 21 of the master oscillator 1, which is input to the frequency divider 21

0 through the third phase shifter 14. The reference signal during emission of the pulse part of the program is generated according to the same law as the time signals in the driver 20, i.e. reference signal

5 is a copy of the envelope of the time signals (Fig. 3c). The initial combination of the emitted and reference signals within the duration of the chip is done by setting the shapers 20 and 26 pulses stored time. Further shift of the emitted signal is carried out using the phase-locked loop.

Synchronizing Imlu / Gyei en -.

5 l 2 times in fig.Za) the waiter 20 arrives through the second delay unit 22. As a result of the installation by delayed pulses (, b), the time signals during eeih during the shaper 20 cannot be shifted,

0 under the action of commands on the control inputs of the phase shifter 14 for more than a period of the output signal of the frequency divider 21 t. for the duration of the elementary premise. When added in the first adder 27

5 modulo two reference signals and an output envelope in block 6 at the output of the first adder 27, a total signal is generated, which directly and through Efron inverter 31 enters the third key 32. Gating pulses (gates of the envelope

71818619 8

) at the control input of the third key, for tuning the phase of the carrier frequency

ca 32 (FIG. 3d) are formed by adding together the emission of pulsed signals

module two main (fi gzd) and delayed-time output signals of the driver

In addition to the control input, the duration of the elementary send-20 is received

ki (fig.Z.zh) reference signal. Strobes 5 of the modulator 10, on the signal multiplier 24 (Fig.Z. z) open the key 32 of the catch. At the other input of the multiplier, 24 signals of each edge and fall of the reference time signals arrive after a delay of

la (Fig.Z.d) for the duration of the block 23 for half the duration of the elementary parcel, with the exception of the parcel (Fig.Z.p). Output signal

subsequent sections of the signal, not co-10 of the multiplier 24 (Fig.Z.r) unlocks the key

holding differential, i.e. non-carrier33 for passing commands from the comparator

information about the envelope shift. 15 to the phase shifter 8 through half the length of the emitted signals of the measurement of the elementary parcel (it is counted out under the action of commands with the integrator delay of the signal in the transmitter) after

30 entering through the open second 15 upon the appearance of the signal front to the rest

key 19 to the third phase shifter 14. In the presence of the pulse (minus

the diagram (fig.Z.g) shows a delay of the same magnitude). When gating the block 6, the envelope of the wand time signals excludes sections of the radio signal,

arbitrary position before starting there are transients on

auto-tuning, and in fig.Z.e - corresponding to 20 pulse fronts.

The resulting result of adding it modulo two is the value of the pulse delay in the block

with a fixed reference signal 22, synchronizing the shaper 20

(Fig.Z.d). The average value of the result in time in-signals, approximately determined by the tegrarator 30 for a time interval, is interchanged as the difference between half of the half-blinking pulses (fronts of support of the elementary premise and

signal (Fig.Z.d)) negatively, therefore, the delay of the signal in the transmitter, while

The mismatch signals appear to suggest that the delay in the transmitter output of the integrator 30. These signaling does not exceed half the duration

depicted in the form of pulses of the negative-elementary premise. The diagrams of Fig. 3

polarity with a dot (fig.Z.i). Since-30 illustrate the case of tuning the signal with

the second output of the integrator 30 is connected by an intermediate delay through the second switch 19 with the first control sensor and the corresponding delay by the sync input of the third phase shifter 14, the clock pulses in block 22

under the influence of delay mismatch signals.

(fig.Zi) at the first control input of fa-35 Fig.4.5 shows diagrams of the operating envelope 14 of the envelope of the device time signals for two extreme cases: none is shifted to the right to the position of maximum delay in the transmitter of stable equilibrium, coinciding by (figure 4) and zero delay (figure 5). The last output of block b (Fig. 3m) with the position of the pi-th case also occurs with the tuned signal (Fig. 2c). The signal is at the output of the 40 ke device without a transmitter, i.e. with the adder 27 modulo two in the equilibrium direct connection of the output, the position of the envelope is shown in Fig. 3, N. modulator 10 to the signal switch 5. In the equilibrium position, the average value of the Delay selection of block 22 has a number value in the integrator 30 equal to zero (Fig.Z.o.) to quickly capture the auto-tuning circuit, the signals at the output of the transformer-45 time signals from an arbitrary current envelope 13 and, therefore, radiated

the signals (Fig. Zl) are synchronized with the impulse-If the delay in the transmitter is equal to the time keeper (Fig. Z, a), and the signal half of the elementary parcel (Fig. 4, c) is assigned to the output of the former 20 (Fig. Z.k) one-pulse holding keeper 2 times

the pulses of the keeper 2 of time i50 are cut (Fig. 4, a) in block 22 is zero (Fig. 4, b). AT

emitted signals for the delay time in equilibrium the reference edges

the path of the signal transmitter 11. (Fig. 4, e) are ahead of the edges of the bend. Cross-connection of the outputs of the in-output at the output of the block 6 of the selection of the envelope-integrator 30 and the third phase shifter 14 (Fig. 4, d), and the installation pulse (Fig. ) in comparison with the direct connection, you-55 is in the middle of the elementary inputs of the integrator 30 to the control inputs, which sets the start of the cyclic code for the ladies of the first phase shifter 7, the time at the output of the shaper 20 is explained by the fact that the reference signal envelope of time prines. As a code, the piloting and emission of signals is considered to be a sequence of ones and zeros, the traces are reversed according to the law 1110001001. Figs. 4, 5

elementary premises at the beginning of the cyclic code in the envelopes of the time signals and in the reference signal are indicated by dashed lines inside the premises.

At the maximum bias of the adjustable signal at the output of the driver 20 time signals half a burst to the left (Fig. 4, g) or to the right (Fig. 4, and) from the installation pulse (Fig. 4,6), which limits the bias of the tunable signal within these limits, has the place, respectively, is the complete coincidence or mismatch of the envelope at the output of block b (Fig. 4, h) or (Fig. 4, k) and the reference signal (Fig. 4.d).

At zero delay in the transmitter (Fig. 5), the delay of the pulses of the keeper 2 times (Fig. 5, a) in block 22 is equal to half the duration of the elementary parcel (Fig. 5, b). In the equilibrium position of the output signal of the envelope extraction unit b (Fig. 5, d) relative to the reference signal (Fig. 5, e), the installation pulse (Fig. 5, b) is also located in the middle of the elementary set, which sets the beginning of the cyclic time code at the output of the driver 20 (Fig. 5, c). When the adjustable signal is displaced by half a burst to the left (Fig. 5, g) or to the right (Fig. 5, i), the corresponding output signals (Fig. B. c) or (Fig. 5, k) of the envelope extraction unit 6 are the same as on the diagrams of figure 4, completely coincide or do not coincide with the reference signal (figure 5, d). In both cases (Figs. 4, 5), the mismatch of the reference signal and the envelope at the output of block 6 does not exceed the duration of the chip. Since the accumulation time of the summation results in the integrator 30 is determined by the fixed envelope gates (Fig. 4, e; 5, e), at large envelope shifts, the mismatch signals will alternately appear when the integrator is zeroed by the edges of the reference signal at the antiphase outputs of the integrator 30, which will result in to fluctuations of an unadjusted signal far from the position of a stable equilibrium and an increase in the time of entering synchronism.

Claims (1)

The claims A device for transmitting time-frequency signals, comprising a modulator, first, second and third phase shifters, serially connected to a master oscillator, a time saver, a reference frequency shaper, a pilot shaper, a signal switch and an envelope extraction unit, as well as a carrier frequency shaper, block control, the output of which is connected to the control inputs of the time signal generator and the signal switch, a radio transmitter with antenna and antenna current transformer, one of the winding terminals of which is connected to the signal inputs of the signal switch and comparator, and the second terminal of the winding of the antenna current transformer is connected to the Earth bus, while the second and third outputs of the time saver are connected respectively to the control input of the pilot driver signal and the first 10 to the input of the control unit, to the second input of which the first output of the time saver is connected, and the output of the reference frequency driver is connected to the reference inputs of the comparator and the envelope extraction unit, characterized in that, in order to increase the accuracy of the transmission of time signals, the first, second, third and fourth switches, first and second frequency dividers, first and second inverters, first and second adders modulo two, an integrator, first, second and third delay blocks and a multiplier, the output of which is connected to the control input fourth key to the first and second inputs connected respectively koto5 cerned first and second outputs of the comparator, and first and second outputs of the fourth key are respectively connected to first and second control input of the second phase shifter, 0 whose output is connected through a series-connected carrier frequency driver and a modulator to the input of the radio transmitter, while the output of the master oscillator is connected to the second input 5 of the reference frequency driver to the signal inputs of the first, second and third phase shifters, the first and second outputs of the first key being connected respectively to the first and second control inputs of the first phase shifter, the output of which is connected through the second frequency divider to the signal input of the reference signal driver, to installation input which is connected to the first output 5 of the time keeper, and the output of the control unit is connected to the control inputs of the second key, the driver of the reference signals and through the first inverter to the control input of the first key, to the first and To the second inputs of which, and through the second key, the first and second outputs of the integrator are connected respectively to the second and second inputs of the third phase shifter, to the first and second inputs 5 of which the first and second outputs of the third key are connected, respectively, while the output of the driver of the reference signals is connected to the installation input of the integrator, to the first input of the first adder modulo two, to the second input the second adder modulo two and through the third delay unit to the first input of the second adder modulo two, the output of which is connected to the control input of the third key, to the first and second inputs of which the modulo two output of the first adder is connected directly and through the second inverter to the second the input of which is connected to the output of the envelope selection unit, while the output of the third phase is shdjshshlshtszhzhi: and M lshiggl ol  5W the spreader through the first frequency divider is connected to the input of the time signal former, to the installation input which the first output of the time keeper is connected through the first delay unit, and the output of the time signal former is connected to the control input of the modulator and through the second delay unit to the first input and directly to the second multiplier input.  I Fig..Z L SL II..III, G and well TLJ L. KU ™ P L ". / "R i and I I I I 1. TO. I I T i i L. -J itL.