GB1572454A

GB1572454A - Radio-electric system

Info

Publication number: GB1572454A
Application number: GB4817676A
Authority: GB
Original assignee: CREMIERS L DE; Telecommunications Radioelectriques et Telephoniques SA TRT
Current assignee: CREMIERS L DE; Telecommunications Radioelectriques et Telephoniques SA TRT
Priority date: 1975-12-18
Filing date: 1976-11-18
Publication date: 1980-07-30
Also published as: DE2657283A1; NL7613800A; FR2405601A1

Description

(54) RADlOELECTRIC SYSTEM (71) We, TELECOMMUNICATIONS RADIOELECTRIQUES ET TELEPHONI QUES T.R.T., of 88 rue Brillat Savarin, 75013 Paris, France, a French Body Corporate, and LAURENT AUGIERS DE CREMIERS, of 17 bis route de la Reine, 92100 Boulogne, France, a French citizen, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a radioelectric system for transmitting information by modulating a discontinuously varying frequency carrier, the transmitter and the receiver each comprising a frequency-changing stage actuated by a frequency synthesiser which varies discontinuously in accordance with a rhythm determined by a clock generator and a periodically repeating code.

A system of this kind, which is called a frequency evasion system, in which the transmitted frequency varies discontinuously in accordance with a code and a rhythm known at the receiver end, can be used to increase the difficulty of an enemy in jamming the communication and also make it difficult to tune in and listen to the communication.

In this system, it is a problem to synchronise the receiver frequency synthesizer with the transmitter frequency synthesizer so that, at each instant, the two synthesizers provide identical frequencies so that the receiver assembly is properly tuned to the transmitted frequency.

The invention provides a particularly simple, effective means of obtaining such synchronization.

According to the invention, the receiver, upstream of the demodulator, comprises an amplitude-limiting circuit whose output is connected to a set of circuits adapted to provide a signal representing the average value of the noise level at the limiting-circuit output, the average-value signal being applied to a frequency-control device in the receiver clock generator so as to reduce said average-value signal to a minimum.

In the case where frequency modulation is used in the transmission system, it is known that in the receiver, the frequency discriminator for restoring the transmitted information is generally preceded by an amplitude limiter. In that case the limiter, which is already present in the receiver, can be used as the amplitude limiter according to the invention.

The invention will be clearly understood from the following description in conjunction with the drawings, all being given by way of example. In the drawings: Figure 1 is a diagram of a radio electric system according to the invention, using frequency modulation; Figure 2 shows diagrams explaining the operation; Figures 3 and 4 are diagrams explaining the operation of a variant of the radioelectric system in accordance with the invention; Figure 5 is a partial diagram of the receiver in the last embodiment; Figure 6 is a partial diagram of the receiver in another variant of the radioelectric system in accordance with the invention; and, Figure 7 shows how the invention is applied to a transmission system using amplitude modulation.

The system according to the invention shown in Figure 1 comprises a transmitter and a receiver, shown on the left and right of the drawing respectively.

In the transmitter, the analog or digital signal corresponding to the information for transmission and present at input 1 is applied to a modulator 2, in which the signal modulates the signal supplied by a pilot oscillator 3. Any suitable modulation can be used. In Figure 1 it is assumed that modulator 2 is a frequency modulator. The signal supplied by modulator 2 is transposed into an intermediate frequency by a first frequency-changing stage formed by a mixer 4 followed by a passband filter 5, the transposition frequency being provided by a fixed-frequency oscillator 6. The intermediate-frequency signal is transposed to the transmission frequency by a second frequency-changing stage formed by a mixer 7 followed by a pass-band filter 8 and a power amplifier 9 and connected to a transmission aerial 10.The transposition frequency applied to mixer 7 is obtained at the output of a frequency synthesizer 11 actuated so as periodically to provide a given configuration of a number of frequencies varying discontinuously in a given rhythm. The configuration for example, may be of 6 frequencies from 200 to 200.9 MHz at intervals of 0.1MHz and following in a certain order at a rhythm of 1 kHz, the configuration thus being repeated at a frequency of 100 Hz.

To this end, synthesizer 11 is frequency-controlled by a code generator 12 which supplies a periodic signal which, in each period, corresponds to the configuration of the 10 frequencies to be obtained. The clock generator 13 supplies a frequency H to the code generator 12, frequency H being the rhythm of the frequency discontinuities in synthesizer 11 (H = 1 kHz in the quoted example). Code generator 12 can be constructed by a well-known method using a shift register looped via a modulo 2 adder, the shift frequency being provided by a clock generator 13. The information in the shift register varies in pseudo-random manner at each shift pulse within a period depending on the length of the register, and the information can make up the control signal of synthesizer 11. The clock generator, as shown in Figure 1, comprises a crystal oscillator 14 followed by a frequency divider 15.

The receiver comprises a number of elements corresponding to those in the transmitter.

The signal supplied by the receiving aerial 16 is amplified in amplifier 17. The signal, which has the same variable frequency as the transmitted signal, is transposed into a fixed intermediate frequency equal to the frequency which, in the transmitter, is applied to mixer 7. This transposition is brought about by the frequency-changer stage formed by mixer 18 followed by band-pass filter 19. The transposition frequency controlling mixer 18 is the same frequency varying discontinuously in a given rhythm in accordance with a periodically repeating code) as the frequency applied to the transmitter mixer 7. The transposition frequency is provided by a synthesizer 20 identical with the transmitter synthesizer 11 and frequencycontrolled by a code generator 21 providing the same code as the transmitter.The rhythm R' of the frequency discontinuities is provided by a clock generator 22 comprising a crystal oscillator 23 follwed by a frequency divider 24. If rhythm H' is the same as the rhythm H supplied by generator 13 in the transmitter, and if the code generators 13 and 20 supply control signals in phase agreement, a fixed intermediate frequency is obtained at the output of filter 19.

The intermediate frequency is transposed to a lower frequency by a second frequencychanger stage formed by mixer 25 and band-pass filter 26, the transposition frequency being supplied by a fixed-frequency oscillator 27. The signal supplied by filter 26 is applied to demodulator 28, which restores the transmitted information. Since the system described in Figure 1 is assumed to use frequency modulation, the frequency demodulator 28 is preceded in conventional manner by an amplitude limiter 29 disposed between mixer 25 and filter 26.

Limiter 29 is a high-gain amplifier which supplies a clipped signal at a constant value.

Clearly, if the system is to operate, synthesizers 11 and 12 must be synchronized by code generators 12 and 21 so as to provide the same frequencies at each instant. According to the invention, this synchronization is obtained by a particularly simple means.

According to the invention, in the frequency-modulation receiver in Figure 1 the output of amplitude limiter 29 is connected to a set of circuits 30 actuated so as to provide a signal Vm representing the average noise level at the limiting-circuit output. To this end, set 30 comprises the following in cascade: a filter 31, an amplifier 32, a detecting circuit 33, a shaping circuit 34 and an integrating circuit 35. Filter 31 has a pass band adapted to transmit a signal representing the noise level at the output of limiter 29. The filter has the maximum possible band width, but must not transmit any component of the useful signal. For example, at a carrier frequency of 700 kHz at the input of limiter 29, a low-pass filter having a pass-band of 0-200 kHz has been chosen. The noise-level average-value signal Vm supplied by the integrating circuit 35 is applied to a device 36 controlling the frequency H' of clock generator 22 and actuated so as to reduce signal Vm to a minimum. In its simple form shown in Figure 1, the control device 36 is a comparator circuit, one input of which receives the average-value signal Vm and the other input receives a threshold signal Vs. The comparator supplies a logic signal E having a value dependent on the sign of the difference Vm - Vs, the signal being applied to a control terminal 37 of frequency divider 24.By means of the logic signal applied to the control terminal, frequency divider 24 can be operated at two division ra.ios, one for obtaining a clock frequency H' practically equal to the transmitter clock frequency H, and the other for obtaining a clock frequency H' which, as will be seen hereinafter, may be slightly higher or slightly lower than the clock frequency H.

The operation of synchronization device which has just been described is based on the fact that limiter 29 produces a relatively high noise level when the receiver synthesizer 20 supplies a frequency different from the transmitter synthesizer 11, whereas the noise level is very low when the two synthesizers deliver the same frequency.

In the first case, if the frequencies supplied by the synthesizers are sufficiently spaced apart (e.g. 0.1 MHz), the signal supplied by mixer 18 falls outside the relatively narrow pass-band of filter 19, since the filter can select only the information signal band (e.g. + 30 kHz) situated around a fixed intermediate frequency; consequently there is no useful signal at the input of limiter 29, which first generates a relatively high noise level, due mainly to its input elements.

In the second case on the other hand, corresponding to normal operation of the system, the clipping effect of the limiter practically eliminates any noise signal at the output thereof.

Between the two noise levels corresponding to lack of agreement or to agreement between the frequency of the two synthesizers, there may be a ratio of the order of 60 dB.

According to the invention, in order to synchronize the configurations of identical frequencies supplied by the transmitter synthesizer 11 and the receiver synthesizer 20, use is made of the noise signal at the output of limiter 29, the average value of the noise signal being represented by the signal Vm at the output of the integrator circuit 29. The average value is characteristic of the lack of agreement between the two synthesizers, as will be shown with reference to the diagrams in Figure 2.

In diagram 2A, arrows denote the transmitter clock pulses of frequency H, hereinafter called H pulses. The diagram also shows the sequence of frequencies supplied by the transmitter synthesizer 11. The sequence is obtained by periodically repeating a configuration of at least 10 frequencies fl to fl0, each frequency being delivered for a time T= 1/H.

Diagrams 2B and 2D show the receiver clock pulses, which have a frequency H' which is assumed equal to the transmitter clock frequency H. Hereinafter, the receiver dock frequen cies will generally be called H' pulses. The drawing also shows the same frequency sequence as the transmitter sequence but delivered by the receiver synthesizer 20. However, there is a time shift z between the corresponding frequency configurations in diagrams 2A and 2B, corresponding to the delay of the receiver clock signal compared with the transmitter clock signal. Between the corresponding frequency configurations in diagrams 2A and 2D, there is a time shift 7 corresponding to the lead of the receiver clock signal over the transmitter clock signal. In the diagrams, the forward or back shift is less than C.

In diagram 2c, the rectangular curve constructed from diagrams 2a and 2b represents the signal which appears at the output of the shaping circuit 34 and represents the noise signal Vb at the output of limiter 29. In diagram 2e the rectangular curve constructed from diagrams 2a and 2d represents a signal having the same meaning as in diagram 2c. In the two diagrams 2c and 2e, in accordance with what has been said previously, it can be seen that the noise signal Vb has a relatively high value Vb max when the frequencies provided by the two synthesizers are different, but has a low value Vb min when the frequencies are the same. The continuous horizontal line represents the average value Vm of the noise signal Vb as delivered by the integrator circuit 35.It can be seen from the diagrams in Figure 2 that when the shift x is zero, i.e. when there is perfect synchronism between the two synthesizers, the average value Vm has a maximum value equal to Vb min. When the shift 7 is equal to or greater than T, i.e. when there is a permanent discord between the frequencies supplied by the synthesizers, the average value assumes a maximum value equal to Vb max.

In order to explain the synchronous operation of the two frequency synthesizers 11 and 12, we shall first assume that, when actuated by a logic signal E supplied by comparator 36, the receiver clock frequency H' takes a value either equal to the transmitter clock frequency H (H' = H when E = O) or slightly greater than H (H' = H+ A H when E = 1).

We shall start from a system of permanent discordance at which the average-value signal Vm has the value Vb max. This situation is very likely to occur when the system starts up. The system Vm is compared in comparator 36 with a threshold signal Vs < Vb max. The threshold signal is indicated in diagrams 2c and 2e by horizontal chain lines. The threshold signal Vs corresponds to a shift 7 S. As long as the signal Vm is greater than Vs, comparator 36 supplies the control terminal 37 of frequency divider 24 with a logic signal E having the value "1", so that the frequency H' supplied by the frequency divider is equal to H + A H. Consequently, the receiver clock signal having the frequency H + A H tends to overtake the transmitter clock signal, which has the frequency H.Thus, the shift 7 and the value of signal Vm decrease.

When the signal Vm decreases to the threshold signal Vs, comparator 36 supplies a logic signal having the value "0", so that the frequency divider 24 delivers a clock frequency H' equal to H. The two synthesizers are then synchronized and the value of signal Vm theoretically falls to Vb min.

In practice, however, the frequencies of the crystal oscillators 14 and 23 determining the clock frequencies H and H' cannot be exactly equal and may be subject to different drifts. For either or both of these reasons, the two synthesizers cannot be exactly synchronized and, after a certain time, an increasing shift 7 inevitably appears between the clock signals H and H', resulting in an increase in the average noise signal Vm. The following two cases may occur.

In the first case, the shift 7 which appears corresponds to a phase delay of the receiver clock signal having the frequency H' with respect to the transmitter clock signal having the frequency H. When the resulting increasing signal Vm passes through the threshold signal Vs, the logic signal E delivered by comparator 36 takes the value "1" so that the receiver clock frequency becomes H' + A H, i.e. greater than the frequency H of the transmitter clock signal. Consequently the receiver clock signal, which has the frequency H' + A H tends to overtake the transmitter clock signal, resulting in an immediate decrease in the delay 7, which thereupon does not exceed the value 7 S corresponding to Vs.Owing to the different time constants, inter alia the time constant of circuit 35, signal Vm does not decrease immediately and for some time remains greater than the threshold signal Vs, so that the delay 7 continues to decrease. After this time, signal Vm decreases in value and passes through the threshold signal Vs, the logic signal E takes the value "0" and consequently the receiver clock frequency takes a value H' very near the transmitter clock frequency H. Thus, the transmitter and the receiver clocks are brought back into phase and the process recurs whenever the delay 7 reaches the value 7s corresponding to the threshold signal Vs. Finally, in the first case the delay 7 does not exceed the value 7s, which can be very small.

The second case is when the shift 7 appearing after synchronism is obtained corresponds to a phase lead of the receiver clock signal over the transmitter clock signal. In that case, at the instant when the resulting increasing signal Vm passes through the threshold signal Vs, the receiver clock frequency likewise becomes H' + AH. Since, however, the receiver clock signal has the same frequency H' + A H greater than the transmitter clock frequency H, the signal cannot immediately correct the phase lead by reducing it. The correction is made by increasing the phase lead until it reaches a value near the duration of a frequency configuration (i.e. 10 Tin the example of a 10-frequency configuration), whereupon the two synthesizers can be resynchronized.However, synchronism is lost during the relatively long adjustment period. This second case of operation, therefore, is to be avoided.

This operation can be avoided and a return can be made to the first case by choosing the transmitter and receiver crystal oscillators 14 and 23 so that the receiver clock frequency H' is slightly less than the transmitter clock frequency H and so that their derivatives produce only a phase delay of the receiver clock signal compared with the transmitter clock signal.

We shall now describe other means of avoiding any operation similar to the second case.

First, however, it should be noted that the system in Figure 1 can operate equally well if the receiver clock frequency takes a value H' - AH slightly less than the transmitter clock frequency H, when actuated by the logic signal E of value "1" delivered by comparator 46.

Synchronism is obtained in similar manner, after complete discordance between the two synthesizers, except that in the present case the correction is made by delaying the receiver clock signal with respect to the transmitter clock signal. It can be seen from the preceding that in this case, synchronism is maintained with a shift 7 less than the threshold value TS, when the shift corresponds to a phase lead of the receiver clock signal over the transmitter signal. When the shift corresponds to a delay, losses of synchronization occur. As before, the latter operation may be avoided by a suitable choice of oscillators 14 and 23.

The other method of avoiding operation capable of producing losses of synchronization is to detect whether the shift 7 is a phase delay or a phase lead and to adjust the receiver clock frequency H' accordingly so as to correct the shift in the right direction. One possible method of detecting whether the shift 7 is a lead or a delay will be explained with reference to diagrams in Figures 3 and 4, some of which are an enlarged version of the diagrams in Figure 2.

In diagrams 3a and 4a, arrows denote the transmitter clock pulses H. In diagrams 3b and 4b, the longer arrows denote the receiver clock pulses H'. In diagram 3b, pulsed H' lag by a time 7 with respect to pulses H, and in diagram 4b pulses H' lead by a time T over pulses H.

Diagrams 3c and 4c show the rectangular signal at the output of the shaping circuit 34, resulting from the noise at the output of limiter 29. The signal is made up of non-zero pulses of duration T, one flank of which coincides with the H' pulses and the other flank of which leads over the H' pulses in diagram 3c and lags behind the H' pulses in diagram 4c.

In diagrams 3b and 4b, the shorter arrows represent two sequences of pulses H'1 and H'2 accompanying the clock pulses H'. Pulses h' 1 have a small lead dover pulses H' and pulses h'2 have a lag d behind pulses H'. If the noise signal 3c is sampled at the instants of pulses h'1 and h' it can be seen that non-zero signal samples are obtained only at the instants of pulses h' i.

T'ke samples xl in diagram 3d occur in advance with respect to pulses H'. It can easily be seen that, if the noise signal 4c is sampled in the same manner, samples x2 are obtained as shown in diagram 4d and occur at the instants of pulses h'2, i.e., lag behind pulses H'. This process of sampling the noise signal can be used to find whether the shift 7 of the receiver pulses H' compared with the transmitter pulses H is a delay or a lead, so that the frequency of the receiver pulses H' can be suitably adjusted.

This method is applied in the diagram in Figure 5, which shows some receiver components referred to the in the explanation, the references being the same as in Figure 1.

Frequency divider 24 has two control terminals 40 and 41. Depending on the values of the logic signals S1 and S2 applied to terminals 40 and 41 respectively, the frequency H' of the pulses supplied by frequency divider 24 become either practially equal to the transmitter clock frequency H or slightly greater (H + A H) or slightly less (H - A H), in accordance with the following Table I: TABLE I S S2 S2 H 0 0 H 1 0 H + AH 0 1 H AH The pulses supplied by frequency divider 24 are applied to two delay circuits 42, 43, in cascade, each producing a delay equal to d. The signal between the two delay circuits is the receiver clock signal H controlling the code generator 21.Sampling pulses h'1 in advance by d of the clock pulses H' are obtained in front of circuit 42, and sampling pulses h'2 laggmg behind clock pulses H' by d are obtained after circuit 43. Pulses h'1 and h'2 are interlaced at the interconnecting point 44 and actuate sampler 45, which receives the output signal from shaping circuit 34. Phase detector 46 detects whether the samples supplied by sampler 45 have a phase lead or a phase lag compared with the clock pulses H'. Depending on whether the samples are in advance (samples x1 in diagram 3d) or delayed (samples x2 in diagram 4d), the phase detector supplies a logic signal X equal to "1" or "0".

The logic signal X is directly applied to an input of AND gate 47, and is applied via an inverting circuit 49 to an input of AND gate 48. The logic signal E supplied by comparator 36 is applied to the other inputs of AND gates 47 and 48. The outputs of the AND gates deliver logic signals Sl and S2 controlling the frequency H' supplied by the frequency divider 24.

Table II hereinafter shows the values of the control signals Si, S2 in dependence on the logic signals E and X. The Table also shows the resulting frequency H', in accordance with Table II.

TABLE H S X Si S2 H' 0 0 0 O H 0 1 0 0 H 1 0 0 1 H AH 1 1 1 0 H+ AH The first two lines of Table II indicate that when the shift 7 corresponding to an advance or a delay is less than the threshold shift Ts (E = 0), the clock frequency H' is made equal (or practically equal) to the transmitter clock frequency H. The third and fourth lines indicate that when the threshold shifts is reached (E = 1), the frequency H' is made equal either to H - AH in order to correct an advance of pulses H' over pulses H (X =0), or H + A H in order to correct a delay of pulses H' behind pulses H (X = 1).

In the system according to the invention described hereinbefore, the reduction in the shift 7 between the transmitter and receiver clock signals is always made at the same speed, depending on the frequency deviation A H which is imposed in order to make this reduction.

The system can be improved by reducing the shift at a number of speeds, e.g. two speeds, i.e. a high speed to obtain rapid synchronization at the start of the system and a slow speed for maintaining synchronism with high accuracy, avoiding instability. This improvement, applied to the receiver in Figure 1, is shown in the diagram in Figure 6, which also shows more details of the construction of a frequency divider having a variable division ratio.

Figure 6 shows only those components of the receiver which are necessary for understanding the invention, i.e. the receiver clock generator 22 supplying frequency H' and the elements for controlling the frequency in accordance with the average noise signal Vm. The following example is given by way of illustration: The frequency H' corresponding to synchronism is 1000 Hz and is obtained from a crystal oscillator 23 supplying a frequency of 10 mHz. The frequency of 1000 Hz is obtained by frequency divider 24, which comprises three modulolcounters 50, 51, 52 connected in cascade, a modulo 2 counter 53 and a modulo 3 counter 54.

The output of counter 53 is connected to one input of AND gate 55, the other input of which receives logic signal El. The output of AND gate 55 is connected to an input of counter 52, so that when the logic signal El has the value "1", counter 52 is forced to assume position 1 at each pulse coming from counter 53; it can be seen that, in this case, divider 24 divides the frequency of 10 MHz by 9 600 and supplies a frequency H' of approx 1 042 Hz. When the logic signal Ei is "0", counter 52 operates normally.

The output of counter 53 is also connected to an input of AND gate 56, whose second input receives logic signal E2. The output of AND gate 56 is connected to an input of counter 51, so that when the logic signal E2 is "1", counter 53 is forced to assume position 1 at each pulse coming from counter 53; it can be seen that in this case, divider 24 divides the frequency of 10 MHz by 9 600 and supplies a frequency H' of approx. 1 004 Hz. When the logic signal E2 is "0", counter 52 operates normally.

The average-noise signal Vm is applied to the two comparators 57, 58. Comparator 57 compares Vm with a threshold signal Ssl and delivers logic signal El, which has the value "1" if Vm > Vsi and "0" if Vm < Vsl. Comparator 58 compares Vm with a threshold signal VS2 less than Vsl and delivers a logic signal E2 which has the value 1 if Vm > Vs2 and the value 0 if Vm < Vs2. However, owing to AND gate 59 and inverting circuit 60, logic signal E2 is not transmitted to AND gate 56 unless logic signal Ei has the value 1.

By means of the device, synchronous operation is obtained in two stages. Starting from a situation of permament discordance where the value of signal Vm is greater than the threshold value Vi, it can be seen that the AND gate 55 is made conductive by the logic signal E = 1 and AND gate 56 is blocked by the logic signal E2 = 0. In that case, divider 24 supplies a frequency H' = 1042 Hz. Since the transmission clock frequency H is 1 kHz, synchronism is approached at a speed corresponding to the difference A H1 = 1042 Hz = 1000 Hz = 42 Hz, and the average-noise signal Vm decreases to a first threshold Vsl corresponding to approximate synchronism.When the value of signal Vm becomes smaller than the threshold value Vsl but is still above the threshold value Vs2, AND gate 55 is blocked by the logic signal El = 0 and AND gate 56 is made conductive by the logic signal E2 = 1. Divider 24 then supplies a frequency H' = 1004 Hz. Synchronism is now approached at a relatively low speed corresponding to the difference A H2 = 1004 Hz = 1000 Hz = 4Hz. When the value of signal Vm becomes less than the threshold Vs2, both the AND gates 55,56 are blocked and divider 24 supplies the clock frequency H' = 100 Hz, equal to the transmission clock frequency H.The threshold Vsl corresponding to approximate synchronism can be adjusted e.g. to correspond to a shift T Si of 50 ,us, and the threshold Vs2 corresponding to fine synchronism can be adjusted to correspond to a shift 7 sz of 5 CLs. Once synchronism has been obtained, it can be maintained with a shift equal to 7 s2, the shift corrections being made at a relatively low speed corresponding to the difference A H = 4 Hz.

The skilled addressee can easily see that the improvement which has just been described applies equally to the system in Figure 5.

In Figure lit was assumed that the transmission system according to the invention used frequency modulation, so that the amplitude limiter normally included in the receiver could be used for synchronizing the two synthesizers. In the case where the transmission system uses another kind of modulation not comprising a limiter, e.g. amplitude modulation, an amplitude limiter is connected in parallel in the frequency transposition circuit in the receiver. This is shown in Figure 7 which, with the same references as in Figure 1, shows a limiter 29 connected in parallel between a mixer 25 and filter 26. The noise signal at the limiter output is processed in the same manner as in the embodiments previously described.

WHAT WE CLAIM IS: 1. A radioelectric system for transmitting information by modulating a discontinuously varying frequency carrier, the transmitter and the receiver each comprising a frequency changing stage actuated by a frequency synthesizer which varies discontinuously in accor dance with a rhythm determined by a clock generator and a periodically repeating code, characterised in that the receiver, upstream of the demodulator, comprises an amplitude limiting circuit whose output is connected to a set of circuits adapted to provide a signal representing the average value of the noise level at the limiting-circuit output, the average value signal being applied to a frequency-control device in the receiver clock generator so as to reduce said average-value signal to a minimum.

2. A radioelectric information-transmitting system according to claim 1, characterised in that the set of circuits connected to the limiting-circuit output comprises an input filter having a passband adapted to transmit a signal corresponding to the noise signal present at the limiting-circuit output.

3. An information-transmitting radioelectric system according to claim 1 or 2, character

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. oscillator 23 supplying a frequency of 10 mHz. The frequency of 1000 Hz is obtained by frequency divider 24, which comprises three modulolcounters 50, 51, 52 connected in cascade, a modulo 2 counter 53 and a modulo 3 counter 54. The output of counter 53 is connected to one input of AND gate 55, the other input of which receives logic signal El. The output of AND gate 55 is connected to an input of counter 52, so that when the logic signal El has the value "1", counter 52 is forced to assume position

1 at each pulse coming from counter 53; it can be seen that, in this case, divider 24 divides the frequency of 10 MHz by 9 600 and supplies a frequency H' of approx 1 042 Hz. When the logic signal Ei is "0", counter 52 operates normally.

ised in that the device for controlling the frequency of the receiver clock generator comprises a comparator circuit for comparing the noise-level average-value signal with a threshold signal, the comparator circuit providing a logic signal which controls the frequency of the receiver clock generator, one value of the logic signal making the receiver clock frequency practically equal to the transmitter clock frequency whereas the other value makes the receiver clock frequency different by a predetermined amount from the transmitter clock frequency.

4. An information-transmitting system according to claim 1 or 2, characterised in that it comprises phase-comparison means for detecting if the noise signal at the limiting-circuit output occurs in advance or in arrear with respect to the receiver clock pulses, the receiver clock generator frequency control device comprising a comparator circuit for comparing the noise-level average-value signal with a threshold signal, the comparator circuit providing a logic signal which, together with the logic signal supplied by the phase comparison means, controls the receiver clock generator frequency, two configurations of the two logic signals making the receiver clock frequency practically equal to the transmitter clock frequency, whereas a third and a fourth configuration of the two logic signals makes the receiver clock frequency lower or higher respectively than the transmitter clock frequency.

5. An information-transmitting system according to claim 3 or 4, characterised in that the receiver clock generator frequency control device comprises at least a second comparator circuit for comparing the noise-level average-value signal with a second threshold signal lower than the first threshold signal, the second comparator circuit providing a logic signal which controls the receiver clock generator frequency, one value of the logic signal being used to make the receiver clock frequency practically equal to the transmitter clock frequency whereas the other value is used to make the receiver clock frequency different from the transmitter clock frequency, the frequency different being smaller than the difference determined by the first comparator circuit.

6. An information-transmitting system according to any of claims 1 to 5, the system using frequency modulation and being characterised in that the amplitude-limiting circuit is inserted in series in the frequency-transposition circuit of the frequency-modulation receiver.

7. An information-transmission system according to any of claims 1 to 5, the system using amplitude modulation and being characterised in that the amplitude limiter is connected in parallel in the receiver frequency transposition circuit.

8. A system substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawings.