FI65877C - ANGLE ATTACHMENT TO RADIO FREQUENCY RECEIVABLES - Google Patents

Description

2 65377 in the application ICAN-6716 of "grooved circuits" entitled "low power digital frequency synthesizer using COS / MOS integrated circuits" by R.E. Funk, published in 1972 in RCA Solid State Databook, is a COS / MOS Digital Integrated Circuits (SSD-203) booklet published by RCA Corporation.

One type of PLL circuit for television tuning equipment, described in detail in U.S. Patent No. 3,821,650, is controlled by a tuning voltage obtained from a phase detector that operates on the basis of differences between the intermediate frequency (I.F.) signal image carrier and the reference frequency. The control loop is cut off when switching channels so as to optionally shift the tuning voltage up or down until the next channel is reached. At this time, the intermediate frequency signal is switched back to the phase detector so that tuning is maintained for the new selected channel. Arrangements are also made to distinguish between video carriers and audio carriers to prevent incorrect tuning of the circuit to the audio carrier.

Although such a frequency synthesizer is known for tuning standard frequency broadcasts, not all television signals are transmitted on standard broadcast frequencies. Some television distribution systems, such as those used in cable television (CATV) or apartment and hotel central antennas (MATV), connect television signals to receivers via cables. In such a cable system, the information modulated on the standard broadcast carrier can be transmitted at a frequency before it is transmitted to the receiver. The resulting carrier may not be suitable for frequency standards, e.g. in central antenna cases the error may be as much as _ + 2 MHz of the standard carrier frequency. As a result, it is desirable to provide hardware for tuning receivers to non-standard frequency carriers, as well as standard frequency carriers. One such apparatus is described in GB Patent 1,561,544 to John G.N. Henderson.

The tuning apparatus of the present invention for tuning a television receiver to a radio frequency carrier is characterized in that it comprises switching control means operating on the basis of a local oscillator signal and an intermediate frequency signal, optionally providing either a first signal with a frequency equal to the local frequency. N) corresponding to the selected channel, or a second signal including a frequency component proportional to the intermediate frequency carrier to the second input of the phase comparator means, wherein the ratio of the frequency of said local oscillator signal to said first number is substantially equal to the nominal value of said frequency component; switching control means for supplying control signals thereto when the signals connected to the first and second inputs of the phase comparator members have a predetermined phase the e- and frequency dependence and the frequency of the frequency component are within a predetermined deviation range from its nominal value, the switching control means first switching the first signal to the phase comparator and then disconnecting the first signal from the phase comparator and switching the second signal to the phase comparator in response to control signals.

In the accompanying drawings:

Figure 1 is a block diagram of a television receiver incorporating a tuning apparatus according to the present invention.

Figure 2 is a logic diagram for a portion of the channel selection unit 32 of Figure 1.

Figure 3 is a logic diagram for the phase comparator 72, active low pass filter 112, and lock detector 124 of Figure 1.

Figure 4 is a diagram of the weak signal detector 128 of Figure 1.

Fig. 5 is a diagram of the remote detector 136 of Fig. 1.

Fig. 6 is a diagram of the sound lock blocking unit 162 of Fig. 1.

Fig. 7 is a logic diagram of the mode control unit 194 of Fig. 1.

Fig. 8 is a graphical representation of a timing diagram useful in understanding the operation of the apparatus of Fig. 1.

Fig. 9 is a logic diagram of the synchronous mode switch 68 in Fig. 1.

Figure 10 is a logic diagram of the number B of the divider 142 in the figure

Figure 11 is a logic diagram of the number K of the divider 84 in Figure 1.

1.

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In the receiver shown in Figure 1, the receiver system 12 is arranged to receive standard frequency broadcast signals, as well as non-standard MATV or CATV other frequency converted signals.

The received modulated radio frequency carriers are fed to a mixer 16. The mixer 16 combines the amplified radio frequency carrier with a local oscillator signal applied to it either via line 18 or line 20 from local oscillator (LO) 116 so as to generate an intermediate frequency (I.F.) signal with a predetermined fixed carrier.

45.75 MHz. Either the VHF portion 116a or the UHF (range) portion 116b of the local oscillator 116 is actuated according to the frequency band of the selected channel so as to provide a suitable frequency range.

Received I.F. the signal is amplified by I.F. an amplifier 22, the output of which is input to the video detector 24. The video detector 24 demodulates the amplified I.F. a signal generating, e.g., luminance - chrominance and clock signal components, which are input to the video processing unit 26 and the synchronization processing unit 28, respectively.

Sound processing equipment (not shown) connected to I.F. amplifier 22 is also provided.

The receiver parts described so far correspond to conventional circuits, which may be, for example, the type used in a CTC-68 type color television receiver described in the RCA color television service bulletin "File 1974 C5" published by RCA Corporation, Indianapolis, Indiana, U.S.A.

The remaining portion of the receiver of Figure 1 includes hardware for automatically tuning the receiver to the selected channel, then the carrier system 12 received a modulated carrier at a standard or non-standard frequency.

The viewer selects a channel using a channel selection unit 32, which includes, for example, a calculator-type keypad for converting decimal channel numbers to binary coded decimal (BCD) signals. These BCD signals are input to the display unit 186 so that the selected channel can be assigned as a display.

These BCD channel number signals are also provided along the path 34 to the channel number comparator 36 in the N division dividering control unit, generally indicated at 38. As will become apparent, the unit 38, in addition to implementing the 656577 tuning apparatus phase locked loop portion N also performs the N division division function. other functions, such as band switching control, i.e. generating control signals depending on the frequency band in which the selected channel is currently located. The N-splitting control unit 38 is described in detail in co-pending U.S. Patent 4,009,439 entitled "Divide by N Control Circuit for a Television Synthesizer".

The control unit 38 dividing by N is included in one of the two phase-locked loops in the tuning apparatus. The first tuning phase-locked loop, which provides a local oscillator signal with frequencies corresponding to a nominal or standard frequency carrier allocated to different channels, includes a reference frequency oscillator 80, an R multiplier unit 76, a phase comparator 72, an active low pass, a low pass K divider preselector 84 and N divider control unit 38. A second, precision-tunable phase-locked loop structure that adjusts the local oscillator signal so as to minimize the frequency deviation of the actual image carrier IF sigaanlin and I.F. between the nominal frequency of the image carrier (e.g., 45.75 MHz) includes a reference frequency oscillator 80, an R divider 76, a phase comparator 72, an active low pass filter 112, a local oscillator 116, a mixer 16, I.F. amplifier 22, amplifier 150, divider A 146 and divider B divider 142.

It can be seen that the two loops share a reference frequency oscillator 80, an R divider 76, a phase comparator 72, an active low pass filter 112 and a local oscillator 116. The remaining portions of these two loops are optionally connected to these common parts via a synchronous mode switch 68 , which are generated by the mode control unit 194. The mode control unit 194, in turn, operates on the basis of control signals from the lock detector 124, the low level detector 128, the remote position detector 136, and the anti-lock unit 162, the operation of which will be described later.

When the viewer selects a particular channel, the CHANNEL SELECT unit 32 CHANGES and CHANGES THE DETECTION pulse signals to the mode control unit 194 along wires 188 and 180, respectively, returning the mode control unit 194 to the output state. As a result, the mode control unit 194 connects the control signal (via line 172) to the synchronous mode switch 68, whereby the switch 68 connects the output signal of the divider control unit 38 (in line 66) to an input in phase comparator 72 (along line 70).

The second input to the phase comparator 72 is fed from the output of the programmable number R divider 76 via line 74. At R, the splitter 76 divides the frequency of the reference signal generated by the reference oscillator 80 by a number that depends on the band in which the selected channel is located as a result of the band selection control signals 104 and 108 provided by the band detector 44 in N splitter control unit 38.

The phase comparator 72 generates an error signal consisting of a series of pulses whose average amplitude depends on the phase and frequency deviation of the number N between the output signal of the divider control unit 38 and the number R of the output signal of the divider unit 76. The output signal of phase comparator 72 is applied via line 110 to an active low pass filter 112 where it is filtered and amplified to provide a DC control voltage for the VHF and UHF portions of the voltage controlled oscillator 116 via respective lines 118 and 120.

Depending on the band in which the selected channel is located, only one of the two parts of the local oscillator 116 is actuated depending on the control signals connected to it from the power unit 114 of the divider control unit 38 along conductors 98 and 102.

The output switching terminals of the local oscillator VHF portion 116a and the UHF portion 116b are connected to the separate input terminals of the splitting preselector 84 along the respective conductors 90 and 88. The preselector 84 divides the frequency of the VHF local oscillator signals by 16 and the frequency of the UHF local oscillator signals by 64 (i.e., 4 x 16). The number K is selected to provide signals to the control unit 38 that divides by the number N, the frequencies of which are compatible with its operating characteristics.

The output signal of preselector 84 is input to divider control unit 38 via line 86. The control unit 88 dividing by a number N divides the frequency of the output signal of the preselector 84 by a number N equal to the frequency of the local oscillator signal corresponding to the selected channel in megahertz. In such a structure 65877, when the local oscillator signal corresponding to the selected channel is combined with a standard radio frequency carrier, I.F. the signal at which the image carrier is located at a nominal frequency (e.g., 45.75 MHz).

Reference oscillator 80 may typically include a 4 MHz crystal oscillator. In this case, when the selected channel is in the lower VHF band (channels 2-6) or in the upper VHP band (channels 7-13), the divider 76 is set to divide by 64 so as to provide an output at 62.5 kHz. For the selected channel in the UHF band (channels 14-83), the divider 76 is set to divide by 4 x 64, i.e. 256, so that an output of 15.65 kHz is obtained.

Initially, when the viewer selects a particular channel and the programmable N divider control unit 38 and the R divisible divider 76 are set, the local oscillator begins to oscillate at an arbitrary frequency (e.g., in a band selected at a particular midpoint point). The operating frequency of the local oscillator is changed as a result of the DC control signal generated by the active low pass filter 112 until the error signal generated by the phase comparator 72 indicates substantially no phase or frequency difference between the N divider control unit 38 and the R divider 76 output signals. At this time, the first phase-locked loop provides a local oscillator signal to the mixer 16 at a frequency fLQ which depends on the reference frequency fjyjp * provided by the reference oscillator 80 according to the expression below: f = -N— f (1)

If the radio frequency carrier provided by the receiving system 12 is close enough (e.g., + _50 kHz) to the standard carrier frequency associated with the selected channel (as is the case for standard broadcast reception), the operation of the first phase locked loop is sufficient to tune the local oscillator. This first phase-locked loop typically develops I.F. a signal with an image carrier within + 10 kHz relative to the nominal image carrier (e.g. 45.75 MHz). Any deviation is primarily indicative of the frequency tolerance of the reference crystal oscillator 80.

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When certain additional conditions occur, as will be shown later, the mode control unit 194 generates a control signal from the lock detector 124, the remote position detector 136, the weak condition detector 128, and the anti-lock blocking unit 162 from the control signal, which causes the synchronous mode the output of the divider 142 to one of the inputs of the phase comparator 72. In this case, the second phase-locked loop adjusts the local oscillator frequency to automatically fine tune the receiver, i.e. the actual I.F. the nominal I.F. to reduce the frequency offset between the image carrier (e.g., 45.75 MHz).

In the second phase-locked loop, the output I.F. from amplifier 22 is connected via conductor 154 via amplifier 150 to number divider 146. In number A, divider 146 divides the quantities R

and K, which are used as exemplary in this specification, the established I.F. signal frequency at number 4 and connects this split signal along line 148 to number B to divider 142. In number B, divider 142 divides for the values of the quantities fREF »R, K and A, number A to divider 146 output frequency number 183 when the selected channel is in VHF band and number 732 ( that is, at 4 x 183) when the selected channel is in the UHF band. At number B, the coefficient of divider 142 is adjustable based on the lane-change control signals connected to it via wires 156 and 160 from band-decoder 144 in N-divider control unit 38 in the same manner as at r-divider 76, lane-change control.

It can be seen that the values of K, N, A and B are chosen so that the ratio ίΕ0 / Κ x N and I.F. the ratio of the nominal value of the image carrier (e.g. 45.75 MHz) to the input A x B is each equal to the ratio of the reference frequency signal to the number R when the local oscillator is properly fine tuned.

The phase comparator 72 generates an error signal representing the phase and frequency deviation of the number R from the output signal of the divider 76 between the output signal of the divider 142, which signal is filtered and amplified by an active low-pass filter 112 to adjust the frequency of the local oscillator.

To initiate operation of the second phase-locked loop, the lock detector 124 is connected to the phase comparator 72 along the multi-conductor path 122 and the lock detector generates a LOCK control signal when the operation loop is locked (i.e., when the error signal is less than a predetermined level) and generates LUK logical complement to the LOCK signal) when this lock has not occurred, and these signals are connected to the mode control unit 194 via the multicore path 126.

The fault condition detector 128 is connected to the output of the video detector 24 via line 132 and the output of the synchronous signal processing unit 28 via line 134 and determines when the average amount of noise present in the video signal during the vertical return interval is below a predetermined threshold level to indicate a signal. The low level detector 128 provides a WEAK control signal to the operating mode control unit 194 via line 130 when the received radio frequency signal has an amplitude, e.g., above level 50 microvolts. The low level detector 128 prevents the operation of the second phase locked loop under low signal conditions because the divider A at 146 and the divider 142 at B do not operate properly when the I.F. relatively large amounts of noise are present in the signal.

It can be seen that when receiving cable television or other wired signals, the amplitude of the radio frequency signal is relatively high, which is typically in the range of 1 millivolt, and under these conditions the low power detector 128 produces a WEAK output signal. It can further be seen that when non-Broadcasting carriers are provided by the receiving system 12, a WEAK signal may be generated, thus preventing the operation of the second phase locked loop structure. However, under these conditions, no second phase-locked loop structure is required because the carriers are at standard frequencies.

The far position detector 136 is connected at R to the output of divider 76 via conductor 140 and at B to the output of divider 142 along conductor 144 and determines whether the actual image constant wave I.F. in the signal in a predetermined range from the standard I.F. image of the carrier or not. The remote position detector 136 generates REMOTE and REMOTE control signals when the I.F. the image carrier is e.g. relative to a distance greater than or less than 2 MHz from the standard I.F. image carrier. These control signals are applied to the mode control unit 194 via the multi-conductor path 138.

65877 The anti-lock unit 162 is connected to the low level detector 128 via wire 164 and to the synchronization processing unit 28 via wire 166 to determine whether the signal provided by divider 142 to the audio carrier or the image carrier is associated. If the signal generated by the divider 142 is based on a sound carrier such as a lower adjacent sound carrier, the anti-lock unit 162 generates a SOUND LOCK control signal which is input to the mode control unit via line 168.

As previously noted, when a viewer selects a particular channel, the first phase-locked loop structure controls the frequency of the local oscillator 116 relative to the nominal frequency of the local oscillator corresponding to the standard frequency carrier to which the selected channel is associated. When a lock is provided as determined by the output of the phase comparator 72, the lock detector 124 LOCK generates a control signal. At this time, the control signal remote from the position detector 136 is viewed in the mode control unit 194.

Providing now a LOCK control signal, the presence of a REMOTE control signal indicates that there may be an I.F. carrier + 2 MHz at a distance of 45.75 MHz. Providing the presence of both LOCK and REMOTE control signals, the signals received from the weak condition detector are next considered in the mode control unit 194. In this case, the WEAK control signal indicates either that no signal exists or that the receiver system 12 generates only a weak broadcast type signal. In both cases, the tuning operation is complete and the operation of the second phase-locked loop is not started.

Now, however, the WEAK control signal, together with both the LOCK and REMOTE control signals, indicates that the receiver system 12 is receiving a strong wired MATV or CATV signal prone to broadcast or frequency error. In this case, the tuning operation is transferred to its other mode of operation. The mode control unit 194 now causes the output of the divider unit control unit 38 (in conductor 66) to disconnect from the phase comparator 72 at number N and instead connects the output of divider 142 at number B. The second, i.e. fine-tuning, phase-locked loop structure then adjusts the frequency of the local oscillator so as to minimize the frequency deviation of the actual I.F. between the image carrier 11 65877 lon and the frequency 45.75 MHz.

It should be noted that although it was said above that the REMOTE control signal is generated when the carrier is located _ + 2 MHz away from the 45.75 MHz frequency then if tuning equipment is used in the receiver, where I.F. the frequency response of the circuits is asymmetric around 45.75 MHz so that frequency components above 45.75 MHz are attenuated compared to frequency components below 45.75 MHz and if the remote position detector 136 has generated REMOTE (instead of developing REMOTELY) the control signal remains two possible . Either + _ 2 MHz at a distance of 45.75 MHz there is no picture carrier to which the local oscillator of the selected channel could be tuned or the picture carrier is located above this, e.g. at 46.25 MHz but still below 47.75 MHz. To account for the latter possibility when the LOCK and REMOTE control signals are provided, the mode control unit 194 controls the STEP of the control signal and connects it to the number 7 divider 52 in the number N divider control unit 38 along the conductor 178.

The STEP control signal causes the number N to decrease by two. Since the operation of the second phase-locked loop has not yet started at this stage, the output signal of the divider control unit 38 is further connected to the phase comparator 72 and the first phase-locked loop now adjusts the local oscillator frequency to a frequency corresponding to 2 MHz lower than the standard frequency. channel. As a result, all I.F. carriers with a downward frequency of 2 MHz and an image carrier that has been between 46.25 MHz and 47.75 MHz is now I.F. within the emission band of the circuits. After this coarse tuning is performed, the lock detector 124 again generates a LOCK control signal.

At this point, if the actual image carrier had been present I.F. in the upper portion of the range, a low level detector 128 would generate a control signal WEAK and a remote location detector 136 would generate a REMOTE control signal. As a result of said LOCK, WEAK and REMOTE control signals, the mode control unit 194 implements the coupling of the output signal of the divider 142 to the input of the phase comparator 72 instead of the N of the divider control unit 38 output signals. After that 12,658,777, the second or fine-tuning phase-locked loop adjusts the frequency of the local oscillator so as to minimize the frequency deviation of the actual I.F. between the image carrier and the frequency 45/75 MHz.

It is possible / that the audio carrier (associated with either the selected channel or the adjacent lower channel) could temporarily reach a sufficiently large amplitude and, as a result, the fine-tuned phase-locked loop could erroneously tune this receiver to such an audio carrier. As previously noted, the sound lock inhibit unit 162 SOUND LOCK generates a control signal when the second phase locked loop has tuned the receiver to the sound carrier. As a result of this SOUND LOCK control signal, the mode control unit 194 starts tuning again by disabling the fine-tuning phase-locked loop operation and restarting the operation of the first phase-locked loop. In this way, the situation which may have caused a temporary high amplitude in the sound carrier has already passed and the correct tuning as already described above can now be realized.

Transmission deviations due to e.g. aircraft jitter and coupling from one transmitter to another, in addition to momentarily causing the sound carrier to reach a sufficiently high amplitude to cause the second phase locked loop to lock the local oscillator, may also cause the lock to disappear. This is confirmed by the development of a control signal for the LOCK detector 124 LOCK. As a result of this LOCK control signal, the mode control unit 194 resets the tuning, preventing the operation of the second phase-locked loop and starting the operation of the first phase-locked loop.

When the channel is tuned, the first control transfer to the fine tuning phase locked loop is performed by the STEP control signal 178 in the state storage mode control unit 194. Thus, if for some reason, such as due to signal loss, no STEP control signal status change. This state is maintained until a new channel request is entered. Preserving this state increases the tuning recovery time in its name and reduces the possibility of incorrect tuning.

It should be noted that at the time when the operation of the first phase-locked loop is disabled and the operation of the fine-tuning phase-locked loop is started, the lock detector 124 may generate the character LOCK. This does not necessarily indicate an error condition and should not cause the tuning operation to be restarted. As a result, during the switching interval, the mode control unit 194 does not operate based on the LOCK control signal. In addition, instead of using a lock detector 124 during the switching interval between the first and fine-tuning phase-locked loop, a remote position detector 136 is used to determine if the loss of lock has occurred due to some interference. Since a REMOTE control signal must be generated with a fine-tuning phase-locked loop before starting operation, if a REMOTE control signal is generated during the switching interval indicating that the actual carrier is shifted (by a transient phenomenon or the like) farther than 2 MHz from the 45.75 MHz the operation of the phase-locked loop is restarted.

Further, since the UHF signals are not susceptible to frequency transmission errors in the cable transmissions, a control signal indicating that the UHF channel is selected is applied to the mode control unit 194 at N splitter control unit 38 via line 196 to prevent the start of the second phase locked loop.

In order to initially synchronize the operation of the second phase-locked loop with the operation of the first phase-locked loop when the operation of this second phase-locked loop is started, a side-setting matching pulse is connected to the synchronous mode switch 68 via line 192. The synchronous mode switch 68 also initially synchronizes the operation of the first phase-locked loop with the operation of the second phase-locked loop when the operation of the first phase-locked loop is initiated after the operation of the second phase-locked loop.

This synchronous switching operation can be more easily understood by referring simultaneously to Figures 8, 9, 10 and 11. Figure 8 e-shows the different waveforms associated with the synchronous mode switch 68. Figures 9, 10 and 11 show logic applications of the synchronous mode operation, respectively. switch 68, number B for divider 142, and preselector number K for divider 84.

Fig. 8 shows three time intervals of operation of the tuning apparatus of Fig. 1, namely with the first phase locked loop locked (designated coarse mode locked phase) when the second phase locked loop enters its unlocked locked state (called fine tuning mode unlocked the local oscillator after the channel is changed (what is called the coarse tuning mode case after the channel change). When the first phase-locked loop is locked, the rising edges of the output signals of the divider N and the divider R are synchronous with each other, while the rising edges of the output signals of the divider B and the divider R are not synchronous with each other. This is because when the first phase-locked loop is running as a closed loop with respect to the reference oscillator 80, the second phase-locked loop acts as an open loop with respect to the reference oscillator 80. and in the number R between the divider output signal, it is conceivable and probable that the excitation voltage applied to the local oscillator 116 by the phase comparator 2 would cause an unnecessary delay before the second phase-locked loop would provide a lock. As a result, the logic of the synchronous mode switch 68 blinks synchronously at step B the rising edge of the first pulse of the divider output signal, which pulse is applied to the phase comparator 72 at N with respect to the rising edge of the dividing

The blinking synchronization of the output signal of the divider at number B to the output signal of the divider at N when the operation of the second phase-locked loop is initially started is carried out as described below. When the first phase-locked loop is operating, the output of the D-type flip-flop 916 from the Q synchronous mode switch 68 is in a logic "1" state while its Q output is in a logic "O" state. These outputs Q and Q of the D-type flip-flop 916 are connected to "and" gates 924 and 926, respectively. As a result, the output signal to N from the divider control circuit 38 (on line 66) is applied through gate "and" port 924 to phase comparator 72 while the output signal at B from the divider (along line 190) is prevented from entering phase comparator 72 because it would pass through blocked "and" gates 926. Furthermore, the "and no" input 920 of the gate 912 in the synchronous mode switch 68 is in the logic state "1" because it is connected to the output Q of the D-type flip-flop 916.

When the correct situations for starting the operation of the second phase-locked loop, as already described above, are detected in the mode control unit 194, a logic state "1" is applied to the second input 918 from this "and not" port 912 and the synchronous mode switch 68 cross-set to input 928. As a result, the set-reset flip-flop 914 generates a logic state "0" which is input to input D of the D-type flip-flop 916. However, the state of the D-type flip-flop 916 does not change until the next positive pulse is applied to its clock input (CK).

Since at this time the inputs 918 and 920 from said "and not" port 912 are both in logic state "1" when a positively moving SIDE SET ADJUSTMENT pulse is applied to the third input 922 from said "and not" port 912, a negative negative pulse is now generated and no " at gate 912 and introducing a logic state "0" along line 174 at number B to divider 142. As a result, at number B, divider 142 is cleared and stops counting.

When the negative direction pulse generated by the "and no" gates 912 ends as a result of the SIDE SETTING ADJUSTMENT pulse, the logic state "0" previously applied to the conductor 174 exits and at B the divider 142 begins to count again. However, the output pulses in the number B from the divider 142 do not have to be connected via the synchronous mode switch 68 to the phase comparator 72 because at this stage the output Q of the D-type flip-flop 916 is still in the logic state "1" while the output Q of this device is in the logic state "0". As a result, the output signal of the divider at N is further applied to the output of the synchronous mode switch 68.

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Since the output of the synchronous mode switch 68 (in the conductor 70) is connected to the input CK of the D-type flip-flop 916, the next edge of the divider output signal in the positive direction causes the D-type flip-flop 916 to input the logic state "O" at the input D. As a result, the Q output goes from the D-type flip-flop 916 to the logic state "O" and its O output goes to the logic state "1". As a result, the "and" gates 926 are enabled and the other "and" gates 924 are blocked, thus disconnecting the divider output signal from the phase inverter 72 and connecting the divider output signal to the phase comparator 72 instead.

the above-described initial blinking synchronization of the number B splitter output signal to the number N splitter output signal when the operation of the second phase-locked loop is terminated is illustrated in Figure 8 by dashed lines marked "switching from coarse to fine-tuning mode". It can be seen that the number B divisor output signal is synchronous with the number N divider output signal at the time when the operation of the first phase-locked loop is stopped and the operation of the second phase-locked loop is started. Since the divider output signal at N has already been synchronized to the divider output signal at R during the operation of the first phase-locked loop, the divider output signal at B is initially synchronous with the divider output signal at R. Thereafter, the synchronization of the divider output signal with the number B and the output signal of the divider with the number R takes place under the control of the second phase-locked loop, as already described previously. This is illustrated in the part of Figure 8 labeled "transition from unlocked to locked mode of fine tuning".

The synchronous mode switch 68 initially conspicuously synchronizes the divider output signal at N to the divider output signal when the operation of the first phase-locked loop is initiated and the operation of the second phase-locked loop is disabled to avoid the unnecessary delay due to the initial error. When the second phase-locked loop is in operation, the output Q of the D-type flip-flop 916 is in the logic state "0", and at number B, the output signal of the divider is applied through the allowed "and" gates 926 to the phase comparator 72.

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Further, the logic state "O" at the output Q of this D-type flip-flop 916 is applied to the input (CLR) at the input JK at the flip-flop 1112 in the division K selector 84. As a result, no input pulse is applied at the divider control unit 38 during the operation of the second phase-locked loop and at number N, the output of divider 38 remains in logic state "1".

When the viewer selects a new channel or when there is a temporary loss of locking due to temporary degradation, the mode control unit 194 connects the logic state "0" setting to input 928 from set reset flip-flop 914 along line 172. As a result, the output of set reset flip-flop 928 -type flip-flop 916 to input D, enters logic state "1". The input D of this D-type flip-flop 916 with its logic states "1" does not enter until the next positive pulse input to the clock (CM) input in this D-type flip-flop 916. Since at this time the input of the phase comparator 72 (in conductor 70) and as a result, the clock input of the D-type flip-flop 916 is further combined with the output of divider B at 142, the next positive direction pulse applied to the input of D-type flip-flop 916 D is provided by the output signal of divider B at 916.

When the logic state "1" at the input D of the D-type flip-flop 916 is input as a result of a positive pulse in the number B in the output signal of the divider, the output Q of the D-type flip-flop 196 switches to the logic state "1" and the output Q of the D-type flip-flop 916 O ". As a result, the reset signal is removed from the division divider 84 at division K and the divider output circuit 38 begins to count the input signal pulses again. At the same time," and "gates 924 are turned on and port 926 is closed, thus connecting the divider output signal 72 to phase divider 72 and disconnects the divider output signal from the phase comparator 72. Thus, the divider N output signal is started and simultaneously connected to the phase comparator 72 synchronously with the first pulse of the divider output signal after the mode control unit 194 generates the command signal, thereby phase-locked loop starts operating. This synchronous switching operation is illustrated in the part of Figure 8 labeled "coarse tuning mode to handoff".

Referring now to Figure 2, there is shown a logic application of a portion of a channel selection unit 32. When the viewer selects a new channel, a second portion (not shown) of channel selection unit 32 generates a SELECTION PULSE pulse which is processed to form its complement SELECTION PULSE and another longer duration PULSE CHANGE. These pulses are applied to the mode control unit 194 and the weak condition detector 128 to reset their logic. The application case shown in Figure 2 uses a conventional logic inverter and an integrated monostable multivibrator.

Figure 3 shows logic applications for phase comparator 72, active low pass filter 112, and lock detector 124. Phase comparator 72 consists of two D-type integrated flip-flops. These D-type flip-flops operate on the basis of the output signals R from the divider 76 and the output signal from the synchronous mode switch 68, respectively, and are arranged so that their outputs are connected to a summing point (conductor 110) to provide a pulse signal with momentary width the frequency difference at R between the output signal of the divider 76 and the output signal of the synchronous mode switch 78. The pulse signal is integrated with an active low-pass filter 112, which includes, for example, an integrated operational amplifier, such as that available from RCA Corporation and whose type number is shown in the figure, to generate a control voltage for the local oscillator 116.

The signals generated at the Q outputs of the D-type flip-flops forming the phase comparator 72 are connected to the NO gate 312 of the lock detector 124, which adds them up. Thus, the resulting sum signal is inverted and its peak is detected by the peak detector 314. If the resulting sum signal contains pulses with a duration signal long enough to charge the capacitor of the peak detector 314, a positive pulse is connected to input D of the D-type flip-flop 316. and accordingly accordingly turned on once in each period of the sum signal provided at the OR gate 312. Thus, if the sum signals contain pulses having a sufficiently long duration to indicate that no lock has been provided, the Q output is set to the logic state 19 65877 "O" while if the sum signal does not contain pulses with a sufficiently long duration, indicating that a lock has been provided, the Q output is brought to a logic state "1".

Figure 4 shows an embodiment of a weak state detector 128. The integrator 412 of the weak state detector 128 is connected to an output of the synchronization processing unit 28, which provides an incomplete combined clock signal including only vertical and horizontal sync pulses from the combined video signal 4 from the video detector 24. an incomplete combined clock signal generating a pulse corresponding to a vertical pulse when the image carrier is in the passband of the intermediate frequency portion of the receiver. The output of integrator 412 is connected to a monostable multivibrator that generates a PORTING PULSE signal that begins immediately after a vertical pulse.

The weak condition detector 128 also operates on the basis of the video signal provided by the video detector 124. The video output signal is amplified and the passband is filtered by the circuit 414 so that the synchronous and color components are removed. As a result of the PORTING PULSE signal, approximately three horizontal lines from the passband filtered video signal are combined within a vertical blanking interval with the low state detector circuit 416. If the radio frequency signal is strong, the video signal is relatively low and However, if the radio frequency signal is weak, the noise concentration is relatively high and the signal detected from the peak provided by the peak detector circuit 416 has a relatively large amplitude. If the signal detected from the peak has a sufficiently small amplitude, the D-type flip-flop whose input D is connected to the output Q of the peak detector 416 from its output to the logic state "1" which indicates a strong signal (WEAK). Thus, by determining the amount of noise present during the PORTING PULSE interval, the weak situation detector 128 provides an indication of whether a strong or weak video signal is present.

Fig. 5 shows an embodiment remote from the position detector 136, which operates on the basis of the input signals by the number R from the divider calculator 76 (along the conductor 140) and the number B from the divider counter 142 (along the conductor 144). The "exclusive or" port 512 generates frequency components that are proportional to the frequency between its internal input signals. Circuit 514 includes a low pass filter, an inverting amplifier, and an inverter. The output signal from the inverter generates pulses moving in the positive direction, the repetition frequency of which is the difference frequency between the output signal of the divider at R and the output signal of the divider at B. The portions of the pulses moving in the positive direction restart the Transparent monostable multivibrator, which develops a pulse of a predetermined width moving in the positive direction to its own Q output. This width is chosen so that if the monostable returns before the next positive transition at its input, the differential frequency I.F. between the carrier and the 45.75 MHz frequency is then less than 2 MHz. The output signal from the monostable multivibrator is tested with a D-type flip-flop, which is driven by the same pulses that touch the monostable multivibrator. The output Q of this D-type flip-flop is a REMOTE control signal whose state "1" indicates that I.F. the carrier is more than 2 MHz offset from 45.75 MHz.

Fig. 6 shows a logic application of the anti-lock blocking unit 162. The anti-lock blocking unit 162 actually compares the repetition frequency of the PORT PULSE signal generated by the signal weak state detector 128 with the repetition frequency of a conventional vertical shutdown pulse generated by the synchronization processing unit 28. If the receiver is tuned to the image carrier, the repetition frequencies of the PORTING PULSE and the vertical shutdown pulse provided by the receiver are equal to each other. However, if the receiver is locked to an audio carrier, their respective repetition frequencies are different and more than one PORTING PULSE is generated for each vertical shutdown pulse. Thus, the anti-lock blocking unit 162 includes a counter 612 that is timed based on the PORTING PULSE signal and reset as a result of the vertical shutdown pulse. If three PORTING PULSES are counted between resets, the output Q of the D-type flip-flop 614 is set to a logic state of "1" (SOUND LOCKING) which thus indicates that the receiver is locked to the audio carrier.

Figure 7 shows an embodiment of a mode control unit 194 using conventional logic components, D-type flip-flops, and a monostable multivibrator. The function of the mode control unit 194 has already been described in detail with its input and output signals, and no detailed description of its logic operation will be realized because it can be easily understood by one skilled in the art by looking at its input and output signals.

It should be noted that although the tuning arrangement of the present invention has been described with reference to the particular embodiment shown in Figure 1 and embodiments of certain portions thereof illustrated in Figures 2-7 and 9-11, modifications of this arrangement and embodiments within the scope of the present invention .

In Figures 2-7 and 9-11, the logic components available in the form of an integrated circuit from Texas Instruments Corporation are identifiable in the figures by their commercial type numbers. In Figure 11, the number 4 divider can be implemented with the Plessey SP8616B integrated circuit and the number 8 divider can be implemented with the SP8600B integrated circuit together with the SP8604B integrated circuit.

For example, the R divider 76 may include an integrated counter of type 74393N, such as is available from Texas Instruments Corporation.

Although described in the present tuning apparatus with reference to the NTSC standards used in the United States, it should be understood that modifications to the tuning apparatus that make it suitable for standards used in other countries are within the scope of the present invention.

It should further be noted that although the two phase locked loops of the current tuning apparatus have been described as having a common reference oscillator 80, an R divider 76 and a phase comparator 72, the tuning apparatus may also be fabricated in accordance with the present invention with two phase locked loops. common parts. For example, the local oscillator signal and the I.F. the signal is optionally connected to the inputs of a frequency divider, the output of which in turn is connected to a phase comparator. In this case, this divider is adjusted during the operation of the first phase-locked loop so that the frequency of the local oscillator signal (such a signal at N is the proportion of divider 38) is adjusted based on the selected channel. During operation of the second phase-locked loop, this divider is adjusted (as is now dividered by 142 in division B) so that the frequency of the image carrier component is divided by so that the signal connected to the phase-locked phase comparator during operation of the second phase-locked loop is substantially equal to 22 65 877. a signal provided to the phase comparator during operation of the first phase locked loop.

In addition, these two phase-locked loops may use signals generated elsewhere in this receiver as reference frequency signals. For example, a 3.58 MHz reference signal used to process color signals may be in use. When the color comparison signal is used as a frequency comparison in phase locked loops, number A should most preferably be selected as number 4, number B should be selected as number 4026, number K should be selected as number 352, and number R should be selected as number 1260 for both UHF and VHF channels.

Claims (19)

An apparatus for tuning a receiver in a television receiver to a radio frequency carrier assigned to a selected channel, comprising means (76/80) for generating a reference frequency signal, phase comparator means (72) including first (74) and second (70). inputs and a frequency control output (110), wherein the reference frequency signal is coupled to the first input (74), oscillator means (116) coupled to the frequency control output (110) for generating a local oscillator signal, and means (16) operable as a response to the local oscillator signal and the radio frequency carrier and generates an intermediate frequency signal which includes an image carrier path, characterized in that it comprises switching control means (38, 68, 84, 142, 146) which are operable depending on the local oscillator signal and the intermediate frequency signal selectively providing either a first signal, frequency is equal to the frequency of the local oscillator signal divided by a first tai (K, N), which responds to the selected channel, or a second signal including a frequency component proportional to the medium frequency carrier path, to the second input (70) of the phase comparator means (72), the relationship between the frequency of the local oscillator signal and said first tai (B) being substantially equal to a nominal value of said frequency component, and means (32, 124, 128, 136, 194) coupled to the switching controls (38, 68, 84, 142, 146) to supply control signals to these when the signals coupled to the first (74) and second (70) inputs to the phase comparator means have a predetermined phase and frequency relationship and the frequency of the frequency component is within a predetermined deviation from its nominal value, the switching control means (68) first coupling the first signal to the phase comparator (72) and then disconnects the first signal from the phase comparator (72) and switches the second signal to the phase comparator in response to controlled signals. Device according to claim 1, characterized in that the switching control means (38, 68, 84, 142, 146) include first splitting means (38, 84) for sharing the frequency of the local oscillator signal with said first tai (K, N) corresponding to the selected the channel for generating the first signal, second dividing means (142, 146) for dividing said intermediate frequency signal by a second tai (A, B) for generating the second signal, the relationship between the frequency of the local oscillator signal and the first number (K, N) is substantially equal to the ratio of the nominal value of the image carrier frequency to the second number (A, B), and means (68) to selectively couple the first and second signals to the second input (70) to the phase comparator (72). Device according to claim 1 or 2, characterized in that the means (32, 124, 128, 136, 194) for supplying control signals to the switching control means (38, 68, 84, 142, 146) include channel selection means (32 ) for controlling the first number (K, N) according to the selected channel and for generating a channel change control signal when a new channel is selected, first detection means (124) for generating a read control signal when the signals associated with the first (74) ) and the second (70) inputs of the phase comparator means (72) have a predetermined phase and frequency relationship, second detector means (136) for generating a near-signal when the frequency of the image carrier is within a predetermined frequency deviation from its nominal frequency value, and third detector means (24, 28, 128) for generating a strong control signal when the radio frequency carrier has a comparatively large amplitude, the switching control means (38, 68, 84, 142, 146) first coupling the first control signal to the phase comparator means responsive to the presence of said channel change control signal and thereafter disconnects the first control signal from the phase comparator means and engages the second control signal to the phase comparator means solely as a response to the presence of all of the read, weak and strong control signals. 4. Apparatus according to claim 3, characterized in that the switching control means (38, 68, 84, 142, 146) disconnect the second signal from the phase comparator means and connect the first signal to the phase comparator means in response to the presence of the channel change control signal, the absence of the read control signal or the absence of the read control signal. . 5. Device according to claim 3 or 4, characterized in that the means (16) for generating the intermediate frequency have a corresponding pass band with amplitude set against frequency and that the switching control means (38, 68, 84, 142, 146) 65 877 generates a step control signal responsive to the presence of the read control signal and the absence of the proximity signal, wherein the frequency of the local oscillator means is changed by a predetermined amount sufficient to cause the image carrier path to be within said pass band as a response to the step control signal. 6. Apparatus according to claim 3, 4 or 5, characterized in that the frequency of the local oscillator signal is reduced by said predetermined amount. Device according to claim 2, 3 or 6, characterized in that the first dividing means change the value of the first number in response to the presence of said step signal. 8. Device according to claim 5, 6 or 7, characterized in that the switching control means (38, 68, 84, 142, 146) disconnect the second signal from the phase comparator means, connect the first signal to said phase comparator means and terminate the step control signal. in response to the presence of the channel change control signal and the switching control means disconnecting the second signal from the phase comparator means, coupling the first signal to the phase control means and maintaining the step control signal in response to the absence of the read control signal. 9. Device according to claim 4, characterized in that the switching controls (38, 68, 84, 142, 146) include synchronizing means (Fig. 9) to first synchronize the second signal with respect to the frequency reference signal as a response to the presence of said read, near and weak control signals. 10. Device according to claim 9, characterized in that the first dividing means (38, 84) provide a first pulse signal, that the second dividing means (142, 146) provide a second pulse signal, that the synchronizing means (Fig. 9) are coupled to the second splitting means (142, 146) to cause the second splitting means to synchronize the generation of the first pulse of the second pulse signal after the generation of said read, near and strong control signals with the first pulse of said first pulse signal generated after the generation of read -, the near and strong control signals, and said switching control means coupling the second pulse signal to said circuit point and disconnecting the first pulse signals from said circuit point in synchronism with the first pulse of the first pulse signal generated after the generation 65877 of read, close and strong control signals. 11. Device according to claim 9, characterized in that the synchronizing means first synchronize the first signal with respect to the frequency reference signal as a response to the presence of the channel change control signal. 12. Device according to claim 11, characterized in that the first dividing means (38, 84) provide a first pulse signal, that the second dividing means (142, 146) give a second pulse signal, that the synchronizing means (Fig. 9) are coupled. to the first splitter means to cause the first splitter means to synchronize the generation of the first pulse signal after the generation of the channel change control signal with the first pulse of the second pulse signal generated after the generation of the channel change control signal, and the switching control means (38, 68, 84, 142 146) couples the first pulse signal to said circuit point and disconnects the second pulse signal from said circuit point in synchrony with the first pulse of the second pulse signal generated after the generation of the channel change control signal. 13. Device according to claim 3, characterized in that said predetermined frequency deviation in connection with the maximum expected frequency deviation between a standard frequency carrier allocated to said selected channel and a non-standard frequency carrier associated with the selected channel. Device according to Claim 3, characterized in that it includes fourth detector means (162) for generating a noise reading control signal when the frequency of the second signal is in direct relation to the frequency of a sound carrier associated with the intermediate frequency signal in accordance with the reciprocal value of the the second signal while the second signal is coupled to the phase comparator means (72), the switching control means (38, 68, 84, 142, 146) disconnecting the second signal from the phase comparator means (72) and coupling the first signal to the phase comparator means in response to the audio reading signal. Device according to claim 3, characterized in that the first detector is coupled to the phase comparator means.