SU1478363A1 - Device for synchronization of equally-available multiaddress radio communication systems - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the synchronization accuracy (C). The device contains a matched filter 1, block 2 of clock C, block 3 of channel C, consisting of adder 12 modulo two, averaging block 13, control element 14 and controlled frequency divider 15, time discriminator 4, integrator 5, block 6 coarse phasing, r-7 frequency grid, correction block 8, frequency divider 9 and distributors 10 and 11. On the phase signals coming from the communication channel, time-channel marking pulses are generated. This produces a selection of the pulses C using the filter 1, which, through the coarse phasing unit 6, performs the coarse phasing of the channel C by setting the registers of the distributors 10 and 11 to the appropriate state. Precise phasing of channel C is performed by block 3 of channel C, made in the form of a tracking system. The resulting current estimate of channel C is used for C of the distributor 10. The process of correcting the phases of the distributor 11 is divided into two stages: determining the average delay and correcting the phase from the measurement results. The average delay is determined using discriminator 4 and integrator 5, and phase correction using correction unit 8. 3 sludge.

Description

The invention relates to telecommunications and can be used to synchronize multi-channel synchronous-address communication systems with time division multiplexing.

The aim of the invention is to improve the synchronization accuracy.

Fig. 1 shows a structural electrical circuit of a sync device for equally accessible multicast radio communication system; figure 2 and 3, respectively, the structural electrical circuits of the matched filter and integrator.

The synchronous equitable multicast radio system synchronization device contains a matched filter 1, a clock synchronization unit 2, a channel synchronization unit 3, a time discriminator 4, an integrator 5, a coarse phasing unit 6, a frequency grid generator 7, a correction unit 8, a frequency divider 9, a distributor 10 and additional distributor 11.

The channel synchronization unit 3 comprises an adder 12 modulo two, an averaging unit 13, a control element 14, and a controllable frequency divider 15.

The matched filter 1 contains a switch 16, a shift register 17, a reference generator 18, a multiplier 19, an AND element 20, a pulse counter 21, and a decoder 22.

The integrator 5 contains elements AND 23-29, a reversible counter 30, decoders 31-36, elements OR 37 and 38, RS flip-flop 39.

The synchronization device of the equally-available multicast radio communication system operates as follows: The communication system, in which synchronization is performed using the synchronization device of the equally-available multicast radio communication system, consists of M mobile transceiver stations operating on the same frequency, randomly located on the ground and located one from another on different distances x. The duration of the time channel and the time cycle are assumed to be the same for all stations of the system. To avoid overlapping time channels between them, a guard interval is introduced, the duration of which is equal to twice the time ()

propagation of the radio signal to the limiting distance between stations in the system.

The synchronicity of the time channels of all stations is established by the signal of the transmitter that started operation first. In this case, the asynchronous markup is terminated.

time channels at the remaining stations, and from the received phasing signal, which is transmitted at the beginning of the time channel, a new marking is started, synchronous for all. With

including new transmitters, the synchronization of the receiving and transmitting valves in each device is made on the basis of averaging the parameters of all received phasing signals. Moreover, the transmitting distributor generates an output signal taking into account the phase advance relative to the receiving distributor by an average delay between

5 temporary channels.

Phasing signals coming from the communication channel provide the formation of markings of the time channels. At the same time, it produces 0 with the selection of synchronization pulses using a matched filter 1, which, through coarse phasing unit 6, performs the initial (coarse) phasing of channel sync by setting the registers of the distributor 10, the additional distributor 11 and the controlled divider 15 to the appropriate state (Fig. one).

0 The selection of the synchronization pulse is performed as follows.

The samples of the input signal with each clock pulse received by the phasing signal are put into the first

5 is a register 17 register of filter 1 (FIG. 2). Then the input of register 17 is closed for V cycles following the frequency BfT (where B, fT are the base and clock frequency of the phase signal, respectively), the sample is recirculated. Since the length of register 17 is equal to B-1 bits, then at the time of entering the next sample into the first bit the previous sample is in the second bit. When register 17 is completely filled with samples from the phasing signal, the first sample is last fed to multiplier 19 and disappears,

0

five

and for the first time a new sample is entered. The reference signal is generated at the output of the reference oscillator 18, the advancement of which is carried out with the same clock pulses as in register M. Therefore, the input signal is compressed with time B times and the samples slide relative to the reference signal. During the period of the phasing signal, the phases of the reference and the samples of the phasing signal coincide. The correlation integral is calculated by a multiplier 19, a counter 21, and a decoder 22.

The synchronization pulses from the output of the decoder 22 are fed to the input of the coarse-phase unit 6 and provide the synchronism establishment mode. The signal from the output of the multiplier 19 is fed to the input of the adder 1 and is information for accurate phasing and maintaining synchronism.

Accurate phasing of the channel synchro- nization is performed by the channel synchronization unit 3, made in the form of a tracking system. The formation of the discriminating characteristic of the block is carried out by summing modulo two signals from the output of the multiplier 19 and the meander function from the output of the controlled divider 15. The misalignment of the peak signal relative to the in-phase condition predominates one or another sign. The magnitude of the error is represented as the code of the averaging block 13 {reversible counter). If the reference signal lags (leads) from the center of the discharged pulse, determined by the last bit of the phasing signal, then the frequency at the output of control element 14 is changed by adding (excluding) pulses to the original sequence. After dividing this sequence in the control divider 15, the current estimate of channel synchronization is formed at the first output of the latter. This estimate is used to synchronize the distributor 10.

The process of adjusting the phases of the additional distributor 11 is divided into two stages: the determination of the average delay and the adjustment

ten

15

20

25

phases of the transmitting distributor according to the measurement results.

The determination of the average delay in the synchronous access device of the multicast radio communication system is performed using the time discriminator 4 and the integrator 5.

The time discriminator 4 generates a mismatch signal (the sign and magnitude of the mismatch) between the input (from matched filter 1) and reference (from the controlled divider 15) signals in each time channel. The mismatch limits are set by the distributor 10 and are calculated on the maximum range of the system (double delay 2Cj barking)

Averaging the obtained mismatch values is performed in integrator 5 (Fig. 3) using the following operations: accumulation of mismatches in the reversible counter 30

N

(- as

a ((where a., - increment

one

counter code 23 in the i-th time channel), comparing the current value of the total code with threshold values (using decoders 31-34), generating setup signals when comparing pulses from the outputs of decoders 32 and 33 and decoders 35 and 36.

As a result of the coincidence of the signals from the outputs of the decoders 32, 33, 35 and 36, pulses appear at the corresponding output of the integrator 5, the last of which sets the register of the phase shifter of the correction unit 8 to the code corresponding to the advanced transmission of the output signal.

The advance of information transfer is carried out in accordance with the expression

0

five

N

i-apt L m (x & ii)

 l- {

where xMi and x ,,

AND)

- the time coordinates of the input (from the output of filter 1) and the reference (from the output of the controlled divider 15) signals;

-number of averaging channels.

To prevent the counter-code of the reversible counter 28 from changing in the directions 00 ... O, 11 ... 1 and 11 ... 1.00 ... 0, blocking the arrival of pulses to the clock input of the reversing counter 30 is performed. Such blocking provided that the value of the signals on the add and subtract buses does not change. The operation of prohibiting the counting is provided by the signal from the output of the RS flip-flop 39. When the reversible counter code 30 reaches the value 11 ... 1, a pulse is generated at the output of the decoder 31, which through the elements 24 and OR 3 tilts the RS flip-flop 39 to zero This leads to the cessation of the arrival of pulses at the clock input of the reversing counter 30. In this state, the reversing counter 30 remains until the signals on the add and subtract buses change. In this case, the RS flip-flop 39 is set to one, which permits the arrival of pulses to the clock input of the reversible counter through the AND 23 element.

When the code of the reversible counter 30 is 00 ... O, similar actions are taken to block the AND 23 element using the decoder 34, the AND 26 and, 27 elements, the OR 38 element and the RS flip-flop 39.

Claims (1)

Invention Formula A synchronous equitable multicast radio system synchronization device containing a coarse phasing block connected in series to a matched filter, a distributor and a clock synchronization unit whose output is connected to a clock input of a matched filter, as well as a frequency grid generator, a frequency synchronizer and channel synchronization block, information input which is connected to the second output of the matched filter, the second output of the distributor is connected to the clock 5 o Q five five 0 inputs of the coarse phasing unit and the channel synchronization unit, the additional clock input of which and the clock inputs of the distributor and the clock synchronization unit are connected to the corresponding outputs of the frequency grid generator, and the information input of the matched filter is connected to the information input of the clock synchronization unit, the information input of the matched filter and the first output The distributor is an input and an output of the device, respectively, characterized in that, in order to improve the synchronization accuracy serially connected time discriminator, integrator and correction unit, as well as an additional distributor, while the first and second information inputs and the channel synchronization signal input of the time discriminator are connected respectively to the outputs of the matched filter, distributor and channel synchronization block, the control input and the first output of which is connected respectively to the output of the coarse phasing unit and the input of the signal of the channel synchronization of the distributor, the inputs sig The channel synchronization of the integrator and the correction block is connected to the second output of the channel synchronization block; the combined inputs of the coarse phasing signal of the correction block and the additional distributor and the coarse phasing signal input of the time discriminator are connected to the output and the auxiliary output of the coarse phasing block; to the input of the correction signal of the additional distributor, the clock input of which and temporary assembly distributor input connected to the corresponding outputs of the frequency generator the grid, wherein the distributor further output is an additional output device.