SU1295520A1 - Frequency-to-voltage converter - Google Patents

Abstract

The invention relates to information-measuring technology and can be used in automatic control systems. The purpose of the invention is to increase the resolution of the converter at the mid and high frequencies of the range by automatically selecting the conversion period depending on the input frequency range. The number of periods of the input frequency, for the duration of th with C SL | C

Description

which it is necessary to carry out the next conversion, is determined by the sensor 19 of the conversion range. The code for this number is stored in registers 10, 11 and is a unit of the division factor for the controlled divider 20 of the input frequency. The control unit 7 on the front of the input signal coming from the imaging unit 1 generates through successive control signals having a duration equal to several periods of the signal of the reference frequency generator 15. Elements 2, 3, 4, 5, 6, controlled divider 20 with register 9 and block 7 ensure the operation of counter 8 and the storage of the code of the accumulated number proportional to the duration of the specified number

one

The invention relates to information-measuring technology and can be used in automatic control systems.

The purpose of the invention is to increase the resolution of the converter at medium and high frequencies of the range by automatically selecting the conversion period depending on the input frequency range.

Fig. 1 shows a functional diagram of a frequency converter in a code and voltage) in Fig. 2, control unit J in Fig. 3 are timing diagrams of signals at its inputs and outputs; Fig. 4 shows a transducer range sensor.

The frequency to voltage converter contains a pulse former 1, elements AND 2-6, control block 7, pulse counter 8, registers 9-11, resistive matrix 12, key groups 13 and 14, reference frequency generator 15, operational amplifier 16, source 17 reference voltage, a digital-to-analog converter (D / A converter) 18, a conversion range sensor 19, a controllable frequency divider 20, elements NOT 21-23 an input bus 24, an output bus 25.

periods of the input signal, and the first 13 and the second 14 groups of keys, the resistive matrix 12, the operational amplifier 16, the digital-to-analog converter (1SC1) 18 and the source 17 of the reference voltage convert the code to an inversely proportional voltage. Thus, the output voltage of the converter on the output bus 25 is inversely proportional to the duration of the number of input signal periods detected by sensor 19. At the same time, it is proportional to the output voltage of the DAC 18, which ensures the linearity of the characteristics of the device, respectively, increasing its output voltage, which is a reference for the operational amplifier 16. 2 Cp. f-ly, 4 ill.

Block 7 contains the element And 26, the counter 27 pulses, the element AND-OR 28, the elements And 29-31.

The conversion range sensor 19 comprises an HE element 32, the AND elements 33 and 34, a trigger 35, a pulse counter 36, a memory device 37. The control unit 7 is designed to absorb at the beginning of the output pulse of the driver 1, following each other and outputted on different chains , control commands U1, U2, U3, U4. The duration of each of them is equal to the duration of a certain constant number of periods of the signal of the reference oscillator.

Managed divider 20 (input) frequency is designed to form at its output at the beginning of each tth period a frequency to be converted that allows control commands to pass through I4-I6 elements and has a duration longer than the total duration of U1-U4 commands. The code corresponding to the number t is supplied to the bit inputs of the divider from the bit outputs of the sensor 19 of the range.

Sensor 9 is a block at the bit outputs of which, at each period of the frequency to be converted, a digital code appears at the commands U1, U4 corresponding to the number of the frequency in which the frequency of the input signal is currently located. In each range, the conversion is performed for a certain number of periods of the input frequency w, predefined for each range. The command U1 stops the operation of the range sensor so that it terminates all transients, after which the code of the range number in which the input frequency is located appears on its bit outputs. After reading the code into the controlled frequency divider 20 and the register 10, the U4 command sets the band sensor 19 to the initial state for operation at the next period of the input frequency. The range sensor may have a hysteresis characteristic.

The Converter operates as follows.

The input signal is fed to the input of the imager 1, where it is converted into a pulsed form necessary for the operation of logic and scaling circuits. The frequency of the signal is saved.

When the output of the imager 1 t-th. (From the end of the previous conversion interval) pulse controlled by the divider 20 of the input frequency raises the signal, opening elements I4-6. Otherwise, the counter 8 continues counting the pulses of the reference oscillator, the commands U1, U4 are sent only to the inputs of the range sensor to ensure its operation at the next period of the input frequency, the output code generated by it during the previous period is reset. With the open elements I4-6, the command U1 through the element NOT 23 enters the input of the element I 2 and closes it. The pulses of the reference frequency generator 15 cease to pass to the input of the counter 8, which makes it possible to terminate the transients in it and the code of the number n is set at its outputs. pulse generator 15 reference frequency, counted by the counter for m periods of the input signal. The command U2 through the element NOT 22 continues to close the element I2 and transfers the code

counter 8 to register 9, where it is stored for the next measurement period. The same command in register 11 records the code of the range number corresponding to the number m of periods of the input signal, during the passage of which the pulses of the reference frequency generator 15 were counted. The bit outputs of the register 11 are connected to the bit inputs of the D / A converter 18, at the output of which a voltage appears

 ,

where Uo is the output voltage of the source 17 of the reference voltage i

q is the transfer ratio of the DAC 18. The bit outputs of register 9 control the first 13 and second 14 groups of keys, which, together with the resistive matrix 12 and the operational amplifier 16, are a digital-to-analog converter that translates the code of the number n at the output of the register 9 into voltage inversely proportional to it, which appears at the output of operational amplifier 16 and is equal to

 „And

11-pg p

h

where P is the transfer coefficient of the resistive matrix 12. Given the attenuation for U and the fact that the number n is proportional to the duration m of periods of the input signal

P

 ™

will get

in

and

 ZEN.- qUpf I Pfvyh p

 h

where f is the frequency of the reference oscillator

fgj (is the input frequency. Thus, the output voltage of the operational amplifier 16 is pro, proportional to the input frequency. If the limit number of pulses is recorded in the counter 8, which is set according to the switching on of the FROM element, then the output signal 3 appears the element I 2, which closes through the element NOT 21. Subsequently, until the end of the conversion interval, the voltage at the output of the converter is maintained, which corresponds to the minimum input frequency.The command from counter 8 is set to the initial state at which its output is code of number K,

equal to the number of pulses of the reference frequency generator 15, which is the total duration of the commands Ul, U2, of. This is necessary to eliminate the mismatch, since at the beginning of the U1 command, the next measurement period ends and the next one begins, and if the counter worked, then during the passage of the U1, U2, and U3 commands, the number K would accumulate. At the same time, the same U3 command The new code of the area number m, generated by the range sensor at the last completed period of the input signal, is entered into the to register and into the controlled divider 20 of the input frequency. Consequently, in the next measurement period, the pulses of the reference frequency generator 15 will be counted for and periods of the input frequency, and the register 10 will store the code of the number m. Further, upon receipt of the 1st, 2nd, ..., () th pulses of the input signal, the control unit will generate commands U1-U4, controlling only the range sensor 19, because the I4,5,6 elements will be closed. When a pulse arrives at the output of the controlled splitter 20 of the input frequency, an open signal of elements I4,5,6 appears, after which the whole measurement cycle is repeated. The integer n, accumulated by the counter 8 per hectare of the input frequency, is equal to

1 where CO is whole part of the number. The increment lp corresponding to the increment of the input frequency is given by

  . Since n is an integer, the minimum value, therefore, the minimum increment distinguishable by the transducer: the input frequency is r

min ()

in

1m

mf

Claims (3)

1. A converter to a voltage that contains the first and second groups of keys, the pulse shaper, whose input is the input bus, the source of the reference voltage, and the first And element, the first and second 2955206 the inputs of which are connected respectively to the outputs of the reference frequency generator and the first element NOT, and the output is connected to the counting input of the pulse counter 5, the outputs of which are respectively connected to the information / inputs of the first register, the inverse outputs of which are connected to the corresponding 9 control inputs of the second group 10 J keys, the outputs of which are respectively combined with the outputs of the first group of keys and connected to the corresponding inputs of the resistive matrix, the output of which is connected to the inverting 5 an input of an operational amplifier whose output is an output bus and connected to interconnected switching inputs of the first group of keys, the control inputs of which are respectively connected to the direct outputs of the first register, characterized in that, in order to increase the resolution of the converter on average 25 and high frequencies, the second and third registers, a digital-to-analog converter, a control unit, the second, third, fourth and fifth elements of AND, the second and 30, the third NOT element, a controlled frequency divider and a conversion range sensor, the first input of which is combined with the first input of the control unit and connected to the output of the reference frequency generator, and the second the input is combined with the first input of the third element And and is connected to the first output of the control unit, the second input of which is combined with the frequency 40 by the input of a controlled frequency divider and connected to the output of the pulse driver, the second and third outputs are connected respectively to the first inputs of the fourth and fifth And elements, and the fourth output is connected to the third input of the conversion range sensor, while the information inputs of the second register are combined with the corresponding the information inputs of the controlled frequency divider and, respectively, are connected to the outputs of the conversion range sensor, the recording input of the second register is combined with the installation input 5f ki The initial value of the pulse counter and with the synchronized input of the controlled frequency divider is connected to the output of the fifth element And, and the outputs of the second register are respectively connected 7-1 to the information inputs of the third register, whose recording input is combined with the recording input of the first register and the input of the first element and connected to the output of the fourth element, And, and the outputs of the third register, respectively, are connected to the first inputs of the digital-analog converter, the second input of which is connected to the output of the source and the output is with a non-inverting input of the operational amplifier, the inputs of the second element I are connected to the corresponding outputs of the pulse counter, and the output of the second element I is NOT connected to the third input of the first element I through the third element, the fourth input of which is not connected to the output of the third And element, the second input of which is combined with the second inputs of the fourth and fifth elements And, and is connected to the output of the controlled frequency divider, and the switching inputs of the second group of keys are and are other well-, left potential. 2. The converter according to claim 1, T is characterized in that the control unit is configured on a pulse counter, four AND elements and an AND-OR element, the output of which is the first output of the control unit, and the first input is combined with the first input of the fourth AND element and connected to the first forward output of the pulse counter, the first inverse output of which is connected to the first input of the third element AND, the second input of which is combined with the second inputs of the fourth element AND and the AND-OR element and connected to the second direct output of the pulse counter, the second the inverse output of which is connected to the first input of the second element AND, the output of which is the second output of the block 95520. eight control and the second input is combined with the third inputs of the third and fourth And elements and is connected to the third forward output of the pulse counter 5, the first input of which is connected to the output of the first And element, the first input of which is the first input of the control unit, the second input of which second entrance 0 of the pulse counter, and the third and fourth outputs are the outputs of the third and fourth elements AND, respectively, while the third and fourth inputs of the AND-OR element are connected to the third inverse output of the pulse counter, the fourth inverse output of which is connected to the second input of the first element AND.  3. The converter according to claim 1, wherein the transducer range sensor is configured to. two elements And, the element is NOT, score-. pulse, a memory device and a trigger, the first input of which is connected to the output of the first element I, the first input of which is connected to the transfer output of a pulse counter, the counting input of which is connected to the output of the second element I, the first input of which is connected to the output of the trigger, the second input the first input of the conversion range sensor, and the third input is combined with 35 by the second input of the first element AND and connected to the output of the element NOT, whose input is the second input of the conversion range sensor, whose outputs are the corresponding outputs of the storage device, the inputs of which are respectively connected to the outputs of the bits of the pulse counter, the reset input of which is combined with the second input trigger and is the third input of the diaphragm transducer. 25 thirty 40 45 f.t Editor S.Patrusheva Fig Compiled by V.Voitov Tehred V. Kadar Proofreader M. Samborska Order 627/61 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Chig.3