SU1295407A1 - Interface for linking two computers - Google Patents

Abstract

The invention relates to computing technology and can be used in computer complexes built on the basis of a specialized computer system. The aim of the invention is to improve reliability by eliminating the influence of impulse noise. The device contains a shift register 1, two registers 8 and 9, two groups of 2 and 3 elements AND, a pulse counter 5, a one-shot 6, a clock generator 26, a counter 25, an element OR 7, an element And 4. 2 Il. to CD SP 4 Figure 1

Description

The invention relates to computing and can be used in computing / v complexes built on the basis of a specialized computing system.

The purpose of the invention is to increase the reliability by eliminating the influence of impulse noise.

Figure 1 shows a block diagram of a device for interfacing two computers; FIG. 2 is a time chart of his work.

The device contains a shift register 1, elements AND 2 of the second group, elements AND 3 of the first group, element AND 4, counter 5 pulses, one-oscillator 6, element OR 7, first 8 and second 9 registers, clock 10, clock signals, bus 11 and 12 information input and output devices, bus

13 output interrupt device bus

14 information input-output devices, a device read input signal bus 15, a start output bus 16, a device write signal input bus 17, a device address input bus 18-20, an output 21 and an interrupt 23 first 23 and second 24 computers 22, counter 25, the clock generator 26, the bus 27 clock pulses and the bus 28 pulses reset,

The digital computer 24 transmits a series of clock pulses when transmitting information via the bus 10, the accompanying information transmitted to the shift register 1 via bus 11, and accompanying information received from the shift register 1 when received on distance 12. The information is an array of more than or equal to one 16-bit word.

The exchange of information between two computers is carried out as follows.

The transmitting computer (23 or 24) inserts the interrupt signal of the receiving digital computer, and after a period of time (previously specified and included in the algorithm), the digital computer 24 starts transmitting clock pulses on bus 10 and information on bus 11, if it is transmitting, or sends clock pulses on the bus 10 and receives information via bus 12 if it is receiving. The series of clock pulses transmitted by the digital computer 24, controls the operation of the counter 25, arriving at its input of the initial installation (figure 2),

The input of the summation of the counter 25 on the bus 27 from the generator 26 receives the clock pulses. The recalculation factor of the counter 25 is set in such a way that, in the pause between the series of syn chro: 1 pulses coming through the bus 10, the counter accumulates the number of pulses sufficient to form the initial setup pulse for the counter 5, driving it to its initial state on the bus 28, Seri sync pulses bus 10, generated during the reception (transmission) of information received at the input of the initial installation of the counter 25, does not allow it to accumulate a number of pulses sufficient to form a pulse of the initial installation of the counter 5. Conversion factor counter 25 is determined from the ratio K i T. T ,, where T, is the pause between the series of pulses, the repetition period of the clock generator pulses.

Thus, if the counter 5 as a result of the interference is not in the initial state, then the counter 25 in the pause between a series of pulses generates a pulse of the initial installation of the counter 5 via the bus 28. The interfering source may be, for example, a short-term failure of the digital computer 24, resulting in a series of sync pulses may occur that is not a multiple of the number of bits of information.

Claims (1)

Invention Formula A device for interfacing two computers, containing a shift register, a pulse counter, two registers, a one-shot, two groups of AND elements, an OR element, an AND element, the recording input of the first register connected to the recording input of the second register, the first input of the AND input is the input of the device for connecting to the recording output of the first computing machine, the information input-output of the first register, the information input of the second register and the second input of the element I form an i, formation input-output of the device. for connecting to the information input-output of the first computer, the enable inputs of the first and second registers and the third input of the element I form a group of address inputs of the device for connecting to the address output group of the first computing machine, the read input the first register is the input of the device for connecting to the readout output of the first computing machine, the output of the one-shot is connected to the first input of the OR element and is the start output of the device for connecting to the start input of the computing machine, the output of the AND element is connected to the second input of the OR element and is the output interrupts for connecting to the interrupt input of the second computer, the information input and the output of the shift register are information input and output of the device for connecting to the information th outputs and inputs of said second computer, respectively, taktovsh input shift register is connected to the counting input of pulse counter and the clock is an apparatus for connection to sinhrovyho dy said second computer, wherein the pulse counter output is connected to the input of the monostable, the output 21 and elShin Compiled by S. Peymal Editor I. Shulla Tehred I. Popovich Corrector N. Korol Order 619/56 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 - 0 OR is connected to the first inputs of the AND elements of the first and second groups, the second inputs of which are connected to the first and second information outputs of the second register, respectively, the information inputs and outputs of the first register are connected to the outputs of the AND elements of the first group and the third inputs of the AND elements of the second group, respectively, third inputs and outputs of which are connected to groups of information outputs and inputs of the shift register, respectively, characterized in that, in order to increase reliability by eliminating the influence and impulse noise, it introduced u clock counter, and the clock output connected to a counting input of a counter whose overflow output is connected to the adjusting input of the pulse counter, the counting input of which is connected to the adjusting input of the counter.