SU1293842A1 - Shaft turn angle-to-digital converter - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to improve the accuracy of the converter. The first generator, the sine-cosine angle sensor, the first and second digital-analog multipliers, the first and second code converters, the adder, the sign determining unit, the voltage-frequency converter, the reversible counter, the second generator, the key, the integrator, the sampler and storage, binary adder and control unit. A series-connected adder, a key, an integrator, a sampling and storage device, a rectifier, a voltage-frequency converter, a reversible counter, and two digital-analog multipliers form a measuring channel, working on the difference between the measured angle and the real one in the conversion cycle. The control unit generates voltages, which are determined by serial conversion of signals at the frequencies of the first and second oscillators, one of which is more than the other two times, by one measuring channel. At the same time, by forming certain intervals of the converter key closure at the corresponding stage of the conversion cycle, one frequency of the output signal of the sine-cosine angle sensor is selected and the other is completely suppressed, thereby eliminating the error caused by the temperature instability of the characteristics of the converter nodes, 1C. . f-ly, 3 ill. i (L N9 CO 00 OO iif IsD

Description

The invention relates to automation and computing, and to the converters of the angle of rotation of the shaft into a code.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a block diagram of a converter; Fig. 2 is a block diagram of an embodiment of the control unit; FIG. 3 shows the operation diagrams of the converter.

The digital angle transducer contains, the first 1 and second 2 generators, the sine-cosine angle sensor 3, the first 4 and second 5 digital-analog multipliers, blocks 6 and 7 convert the angle to the code, adder 85 key 9, integrator 10, block 11 control, device 12 for sampling and storage, binary adder 13, rectifier 14, unit 15 for determining the sign J, voltage-frequency converter (FS) 16, reversible counter 17, Control unit 11 (Fig 2) contains the first 18 and second 19 keys, null comparator 20; the first 21 and second 22 elements are And, the first 23, the second 24 and the third 25 one vibrators, the D-flip-flop 26, the first 27 and the second 28 T-flip-flops. In the diagrams of FIG. 3, positions 29 and 30 denote the output signals of the first 1 and second 2 generators, position 3 indicates the voltage at the direct output of the second T flip-flop 28, position 32 indicates the output signal of the zero comparator 20 and position 33 is the output voltage D-trngger 26, position 34 - output signal of the first element H 21, position 35 - output voltage of the first T-flip-flop 23, positions 36-38 - output signals of the first 23, second 24 and third 25 one-oscillators, respectively. , key integrator and two digital-analog multiply Whose outputs are connected to inputs of the adder constitute a single measuring Ka cash, ie, in the proposed device eliminated the error caused by the inequality of the two transmission channel coefficient measurement. The control unit operates the voltages determining the sequential conversion of signals at the frequencies of the first and second generators by one measuring channel.

U

at the appropriate stage of conversion, one frequency of the output signal of the sine-cosine angle sensor is selected and the other is completely suppressed, thus eliminating the error due to the temperature and time instability of the characteristics of the band-pass filters signals of working frequencies of measuring channels of a prototype device.

The converter works in the following way.

The inputs of the sine-cosine sensor 3 (SKDU) from the first 1 and second 2 generators are supplied with voltage of the same amplitude differing in frequency by two times (Fig, 3, pos. 29 30):

and ,, and „and„

sinto t and sin (2u) fi-4).

U

where arbitrary phase shift.

The signals at the outputs of SKDU 3 can be represented as

and ,, and „cosoi + and, 2 and and ,, sinot - and

1-2

Sin of COSo,

14

where cL is the angle of rotation of the rotor of the SKDU 3. Before the next conversion cycle, all the triggers of the control unit 11 are in the zero cycle (state), and the second input of the second bit 2-bit binary counter 13 receives a logical signal O from the output of the second T- the trigger 28 (Fig. 2), the output code of the 2-rar of the dna binary adder is equal to its input code, and a code equal to the output code N of the converter is fed to the inputs of blocks 6 and 7 of the code conversion, and the voltage at the output of the adder 8 described by the expression

and

E-1

 and., cos N +

U, 2 sin Ы,

Determining the relations for the transformation we get:

siniJ t

22

and ,, sin ((H) sin (ril-N) +

(one)

cos (d.- N),

U

At the beginning of the conversion cycle, the unit key 18 of the control unit 11 opens from the inverted output of the second T-flip-flop 28, and the signal U ,, of the second generator 2 is fed to the input of the comparator 20.

At a positive half-wave of the signal and, 2 (Fig. 3, POS. 30), a single potential will be set at the output of the null comparator 20 (POS. 32). When the comparator 20 is first switched from the zero state to a single, the D-flip-flop 26 is set to state, and at the output of the first element And 21 a unit potential is established (pos 32,34 at tt,). This potential unlocks key 9, and the input of the integrator 10 in

for two positive half cycles of the signal and the second generator 2, the output voltage Uj will flow. adder 8. This key control 9 ensures complete suppression of the harmonic component of the frequency and) iJ of the first generator 1. As at this stage of the conversion, the integration of the output signal of the adder 8 occurs for two equal periods of time shifted one relative to the other by the value of L). therefore, by the time t t. the output voltage of the integrator 10 will be proportional to the amplitude of the frequency signal of the frequency h 2 and the second generator 2 (cm (1):

and"

 To „sin (dl-n).

. (2)

At time tt, j by the negative signal drop at the output of the first element I 21, the first T-flip-flop 27 is set to one (FIG. 3, pos. 35), and at time tt by the second negative drop at the T-input the first The T-flip-flop 27 is set to the zero state and, by a negative signal drop at its output, the second T-flip-flop 28 is set to one state (Fig. 31). At the same time, the first key 1B of the control unit 11 is closed, and the second key 19 of the control unit 11 is opened and the Signal and the first generator - 1 arrive at the input of the null comparator 20. Pa a negative output signal difference of the first T-flip-flop 27 (position 44 at tt) also, the first one-shot 23, a trigger, is launched. the signal of which (pos.36) is set 1293842

It returns to the zero state the D-flip-flop (pos.42 at t t) and keeps it in this state.

A single potential from the output of the second T-flip-flop 28 is fed to the second input of the second bit of the 2-bit binary adder 13. At the same time, the code to the inputs of blocks 6 and 7 of converting the angle code into sine and cosine codes of the angle is increased by Jr / 2 compared to the output code of the converter. The output voltage of the adder B in this case is described by the formula

0

l,

+ and.

 Up, COS sin (N +

(N +

Jl. ) 2

Jl) 2

which after conversion will take the following form:

25

Ur,

and sin sin (ol-N) - U sin (2Jt + If) cos (dL-N). (3)

When the voltage U, the first generator I, passes through a zero value from a region of negative to a region of positive values (Fig. 3, pos. 29 at t t), a single potential is established at the output of the zero comparator 20. In this case, a single potential is also established at the output of the D-flip-flop 26 and at the output of the first element 21, the key 9 is opened, and the output voltage Uj-adder 8 arrives at the input of the integrator 10. At the end of the positive half-period of the signal Ui, the first generator 1 (FIG. 3, pos. 29 at t tj) at the output of the comparator 20 and, therefore, the output of the first element And 21 is set to zero potentials. The key 9 is locked by disconnecting the integrator 10 from the output of the adder 8. At the considered stage of integration of the output signal of the adder 8, the harmonic component of the frequency III3 and 2) of the second generator 2 is completely suppressed, because the integration time (interval & tt - t in Fig. 3) here is equal to the period of change of this signal. B. In accordance with expressions (2) and (3), the output voltage of the integrator 10 by time t t "

.lt- (“- (N).

(four)

The harmonic oscillations of the frequency u) 2u) in expression (1) and frequency u) tO in expression (2), in addition to the useful component, the amplitude of which is proportional to the value of sin (Ы - N), as in the prototype device, the inequality of transformation ratios and non-orthogonality of SCDU windings. 3. The amplitudes of these components are approximately equal, and the phases (relatively useful components) are opposite, therefore, when summing up on integrator 10 (4), they, like the prototype device, will be mutually compensated It will affect the output of the integrator 10.

By a negative differential signal at the output of the first element AND 21, the first T-flip-flop 27 is set to one (FIG. 3, pos.35 at t 5 °) with the output signal through the second element And 22, the second one-shot 24 is triggered. The output signal of the second one-shot 24 sets the the zero state of the first and second T-flip-flops 27 and 28 and triggers the third one-shot 24. Negative voltage drop at the output of the first T-flip-flop 27 triggers the first one-shot 23, which sets the D-flip-flop to zero. 26. The output signal of the second one the vibrator 20 is supplied to the control input of the device 12 for sampling and storage, and the output of the device 12 for sampling and storage is set to a voltage equal to the output voltage of the integrator 10, the output signal of the third one-oscillator 25 is fed to the reset input of the integrator 10, and the output of the integrator 10 is set to zero voltage This completes the next conversion cycle. If NFY, then the output voltage of the integrator 10 and therefore the sampling and storage device 12 by the end of the next conversion cycle is different from This voltage across the rectifier 14 is supplied to voltage converter 16 at a frequency and at its output a sequence of momentum occurs

Sov, change the status of the reversible counter 17, the output code of which is fed to the output of the converter. The direction of change of the output code of the reversible counter 17 is determined by the polarity of the signal at the output of the device 12 for sampling and storage. A change in the output code of the converter occurs until equality N o (., In the steady state, with any combination of the phases of the signals of the first 1 and second 2 generators, one conversion cycle lasts no more than two periods of change of the output signal of the first generator 1. At the same time, the pulse duration of the first and second t and the third 3 one-shot 13-25 should satisfy the following inequality:

, T: / 4cJj.

Thus, in the converter

Along with the compensation of errors caused by the inequality of transmission coefficients and non-orthogonal windings of the SKDU 3 windings, errors due to different coefficients (transmission of measuring channels, as well as temperature and time instability of the frequency characteristics of the bandpass filters assigned to

signals of the working frequencies of the measuring channels of the prototype device. This makes it possible to increase the accuracy of converting the angle of rotation of the shaft to a digital code and, therefore, reduce

for example, the errors of digital automatic angle transmission systems.

Claims (2)

Invention Formula 1 A shaft rotation angle converter into a code containing a sine-cosine sensor, one input of which is connected to the output of the first generator, the outputs of the sine-cosine sensor are connected to analog inputs of the first and second digital-analog multipliers, respectively, whose outputs are connected to the inputs of the sum mator, voltage converter frequency, and a block for determining the sign, the outputs of which are connected respectively to the counting and control inputs of the reversible counter, the outputs of the lower bits of which are connected to the group m inputs of the first and second code converters, input: which are connected to the digital inputs of the first and second digital analog multipliers, the outputs of the reversible counter are the outputs of the converter, characterized in that, in order to improve the accuracy of the converter, a block is entered into it management, key, integrator. arrange The sampling and storage unit, the rectifier binary adder and the second generator whose output is connected to another input of the sine-cosine sensor and one input of the control unit, the other input of which is connected to the output of the first generator, and the first output is connected to the control input of the key, whose information input connected to the output of the adder, and the output is connected to the information input of the integrator, the setup input of which is connected to the second output of the control unit, the third output of which is connected to the control input of the device and samples and storage, the information input of which is connected to the integrator output, and the output is connected to the input of the sign determining unit and through a rectifier - to the input of the voltage converter - frequency, the outputs of the two higher bits of the reversible counter are connected to the same inputs of the corresponding bits of the binary adder , another input of the first digit of the binary adder is connected to the zero potential bus, and another input of the second digit is binary eight connected to the fourth control. 15 2. The converter according to claim 1, 1, and t is characterized in that the control unit contains two keys, a null comparator, two AND elements, three one-oscillators, two T-flip-flops and a D-flip-flop, information inputs of the first and second The keys are respectively one and the other inputs of the control unit 1 and respectively, the outputs of the keys are connected to the input of a null comparator, the output of which is connected to the C input of a D-flip-flop and one input of the first And element, the other input of which is connected to the direct output of a D-flip-flop and the output is connected to the T-input of the first T-flip-flop, direct 20 output which, through the first one-shot, is connected to the R-input of the D-flip-flop, the first input of the second element Nick T-input of the second T-flip-flop, the direct output of which is the fourth output of the control unit and connected to the control input of the second key and to the second input The second element And, whose output over the second one-shot is connected to the R-inputs of the first and second T-flip-flops and the input of the third one-shot, the output of which is the second output of the block, the output of the second one-shot is the third output of the second-triggera connected to the control input of the first switch, the first output member | and is first output. 25 3d J 1 I II I 35 t, | 1g I G t in ff 36 . Editor E. Sligan Compiled by M.Sidorova Tehred V.Kadar Order 396/59 Circulation 902. Subscription VNIISH State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 D Fmg Proofreader M.Samborsk