SU1290470A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides an extension of the range of output frequencies. The digital synthesizer contains a reference oscillator 1, a frequency code generation unit 2, an accumulator adder (NS) 3, a functional converter 4, delay elements 5 and 6, a controlled frequency divider 7 and a D-flip-flop 8. Block 2 generates a frequency control code Kg n the higher bits of the code Kg are fed to the control input of the HC 3, and m younger bits are sent to the control input of the control divider 7. In the HC 3, the phase K code (synthesized oscillation. The limiting clock frequency is determined by the number of bits Dov p. Information from NA 3 is transformed into An analog signal of the desired form is converted by an ion converter 4. The K: f code is smaller than the Kf control code. The Kf code has no more than 8-10 bits, and the Kf code can reach 32. To obtain the required number of synthesized frequencies, The HC 3 transfer input at certain clock moments is supplied with correction single pulses. A control divider 7 performs the formation of a correction sequence. D-flip-flop 8 provides the required duration of correction pulses. 1 il. to (L to with about 4

Description

The invention relates to radio engineering and can be used in radio receiving, radio transmitting and measuring devices.

The aim of the invention is to expand the range of output frequencies.

The drawing shows an electrical structural diagram of a digital frequency synthesizer.

Digital frequency synthesizer contains

shaft tg. The first and second delay elements 5 and 6 compensate for the delays in the controlled frequency divider 7 and D-flip-flop 8, providing the necessary temporal correspondence of the signals.

The code forming unit 2 generates a (m + n) -disc code for the frequency of Cr.

Obviously Kr Kr „+. Uniform sequence with frequency t arrives at the clock input of w-bit

reference oscillator 1, forming unit ° controlled divider 7, which, under dejkod 2 frequency, accumulating adder 3, functional converter 4, first delay element 5, second delay element 6, controlled frequency divider 7, D-flip-flop 8.

Digital frequency synthesizer works as follows.

In the accumulating adder 3, when the synchronization pulses are fed to its clock input, the code of the synthesized oscillation phase is generated. Information from the outputs of the accumulating adder 3 is converted by a functional converter 4 into an analog signal of a desired shape (for example, a sinusoidal). In this case, the function of the control code Kfm transforms it into an uneven sequence with an average frequency

FCP-klKbs

I cf

from

KPT output per each 2 pulses. The output sequence of the controlled divider 7, whose pulses due to internal delays are late in relation to the corresponding pulses of the output sequence of the reference generator 1 by the time tud, goes to the D input of the trigger 8. To the clock input ( The C input) from which the output of the first delay element 5 enters the sequence of the impulse converter 4 can consist of a reference oscillator 1, which is delayed from or in series “ t, td + 1 „, where

control block, delay lines, D-trigger d-preparation 8. Thus

l frequency and low-pass filter, whether-a stable form of the consistently connected constant-output of the output signal of the D-flip-flop 8 is provided.

a digital storage device, a digital-even sequence of the frequency of the logic converter and the lower filter to, delayed by (t, + m) relative to frequencies (not shown in the drawing).

The principle of operation of the digital frequency synthesizer is based on the fact that the number of digits n of the Kf code necessary for the operation of the functional converter 4, fewer and one sequence of the reference oscillator 1, is formed at the output of the second delay element b (the delay T2 introduced by them is equal to the switching delay time of the D-flip-flop 8 ) and arrives at the same output sequence of the reference generator 1, is formed at the output of the second delay element b (the delay T2 introduced by it is equal to the switching delay time of the D-flip-flop 8) and enters t on the taksh number of control code bits 35 is the input input of the n-bit accumulator Krtm +. from the outputs of the co-adder 3 forming unit. In each clock cycle to the contents 2. Usually n does not exceed 8-10 bits, while the value (m + n) determined by the required number of synthesized frequencies can reach 32 and more 8 trigger trigger output. The bit depth of the accumulative sum is 40

Matora 3 is equal to the required bit size of the “transfer” unit. The fullness of the phase K code, .. In this case, the control input of the accumulating adder 3 is fed

The accumulator adder 3 is added with the binary number of the PKK if the unit transfer accumulation sum transfer is one.

of the cumulative adder 3 corresponds to the phase 2SV7Q, where Q is an integer determined by a specific structure by the functionality of the control code Number of possible 5 converters 4. Therefore, on each

OiTOiiQLJTJtJl / i no K-VMgtppgchpch / ishigt

During the cycle, the phase of the synthesized oscillation is increased by pho 2jfKFn / Q-2 or f | 2jr (Kp, + l) / Q-2.

During the synthesizer cycle, i.e. 2 (cycles (TC 2 + Lt) from the output of the pulses. In these cycles, the content of the NAPP-50 O-flip-flop 8 receives X, 2.Kg. "Single-part adder 3 is not added) and Ho

KRP, a (KRP + 1), due to which the average. v tm / i

the rate of accumulation of the phase code and the synthesized frequency increase.

Corrective sequence is formed by controlled divider 7. D-flip-flop 8 serves to provide the Kf / i code formed by the higher bits of the CRL code-2 values. Correcting the required number of synthesized frequencies to the transfer input of accumulating adder 3 single letters (of every T) and lo 2 () “zeros. Then XQ times the phase is increased by ph and X: times by f. Full phase per cycle equals

F

 Foho + f, x, - -2 (2- Kg4 +

nor the duration of the corrective impulse -fK) .2S- v ows, equal to the duration of the clock interval, QL. shaft tg. The first and second delay elements 5 and 6 compensate for the delays in the controlled frequency divider 7 and D-flip-flop 8, providing the necessary temporal correspondence of the signals.

The code forming unit 2 generates a (m + n) -disc code for the frequency of Cr.

Obviously Kr Kr „+. Uniform sequence with frequency t arrives at the clock input of w-bit

controlled divider 7, which under the action of the control code Kfm converts it into an uneven sequence with a medium frequency

FCP-klKbs

I cf

from

KPT output per each 2 pulses. The output sequence of the controlled divider 7, whose pulses due to internal delays are late in relation to the corresponding pulses of the output sequence of the reference generator 1 by the time tud, goes to the D input of the trigger 8. To the clock input ( C-input) from which the output of the first delay element 5 receives a sequence of impulses of the reference generator 1, delayed from the Uniform frequency sequence, delayed by (t, + n) relative to

the output sequence of the reference oscillator 1, is formed at the output of the second delay element b (the delay T2 introduced by it is equal to the switching delay time of the D-flip-flop 8) and is fed to the clock input of the n-bit accumulating adder 3. In each clock cycle the content input of the n-bit accumulating adder 3. In each cycle to the content - the trigger of the trigger 8 is

the accumulator adder 3 is added to the binary number of the PKK if the sum accumulator is input to the transfer input During the synthesizer cycle, i.e. 2 (cycles (TC 2 + b) from the output of the O-flip-flop 8 enters X, 2.Kg. “One-) and Ho

. v tm / i

nits (out of every T) and lo 2 () “zeros. Then XQ times the phase is increased by ph and X: times by f. Full phase per cycle equals

F

 Foho + f, x, - -2 (2- Kg4 +

Such a phase shift in time Ti corresponds to the average frequency

2rK, f. d-2 G2 ° -)

JT-KF

g.2teitn.-)

Based on information from the accumulator adder 3, the functional converter 4 generates an analog signal of a given shape. Depending on the type of functional converter used, this information may consist of the phase code Kf, the frequency code Kfn, and the overflow signal P in any combination.

The correction sequence supplied to the transfer input of the accumulating adder 3 is generated by a controlled divider 7 with some errors. The impulse to the transfer input can come a little earlier or later than is necessary for the exact formation of the code of the phase Kf. These errors lead to the appearance of an error in the calculation of the code for the Kcp phase, which are cyclically repeated. The length of each cycle cycles.

With an appropriate choice of the algorithm of the controlled divider 7, the magnitude of the errors is rather small. If this value does not exceed q junior-bit units, then an exact p-bit output phase code can be obtained by using a (p + H) -discharge accumulating adder 3. The maximum clocking frequency of the accumulating adder decreases with increasing number of bits , which is associated with a decrease in the speed of the combinational adder included in its composition. Therefore, the range of synthesized frequencies expands with decreasing size of the accumulating adder used. Controlled frequency dividers, when implemented appropriately, are operable at higher frequencies than accumulative adders, performed on the same element base, and their fast5

the effect on the synthesized frequency range has virtually no effect.

In the proposed device, by reducing the required size of the accumulating adder, the range of synthesized frequencies is expanded. For example, to get 2 frequencies, you can use not 32, but an 8-bit accumulating adder.

As a controllable divider 7, for example, micro 0 K 155 IE 8 circuit can be used, and the code forming unit 2 can be made in the form of switches and code converters.

Thus, the main advantage of the digital frequency synthesizer lies in expanding the range of synthesized frequencies and its use allows us to solve problems previously solved only by indirect frequency synthesis methods, based on the method of direct synthesis, which causes a high frequency switching frequency.

Claims (1)

Invention Formula A digital frequency synthesizer containing a series-connected reference oscillator and a controlled frequency divider, a series-connected drum-adder and a functional converter, as well as a unit for generating a frequency code, the higher-order bits of which are connected to the control input of the accumulator adder, characterized by that, in order to expand the range of output frequencies, between the output of the reference oscillator and the clock input of the accumulating adder, the first element connected in series delays and a second delay element, as well as a D-flip-flop, the output of which is connected to the transfer accumulator adder input, a clock input and a D-flip-flop input, respectively, are connected to the output of the first delay element and the output of the controlled frequency divider, the control input of which is connected with the release of the lower bits of the frequency code generation unit. 0 five