SU1280424A1 - Device for transmission of data with compression - Google Patents

Abstract

The invention relates to telemetry devices and can be applied in adaptive telemetry systems. The aim of the invention is to increase the accuracy of the device. The device implements a polynomial predictor of zero order with a floating aperture. In this case, not the current one, but the previous one is taken as the next substantial reading. The device contains an analog-digital converter, a counter, registers, adders, a divider, a comparison unit, a memory unit, a key, an AND element, an OR element, and a clock. 3 il.

Description

The invention relates to telemetry and can be applied in adaptive telemetry systems.

The purpose of the invention is to increase the accuracy of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of the device operation algorithm; in fig. 3 - graph of input and output signals.

The device contains (Fig. 1) analog-to-digital converter 1, the first counter 2 clock pulses, the chronometer 3, the first to the fourth registers 4-7, the first to the third adders 8-10, the divider 11, the comparison unit 12, the second counter 13 essential samples, a memory block 14, a key 15, an AND 16 element and an OR 17 element. The timing device is made on a pulse generator 18 and a pulse frequency divider 19.

Register 4 is used to hold the current count, a register. 5 - for storing the previous current reference, register 6 - for storing the previous significant reference, register 7 - for storing the results of intermediate calculations. As these registers, K155IR13 chips can be used, which are recorded by a positive differential pulse applied to their sync input. When the signal O is applied to the first control input of the register 7, it enters the storage mode (its state does not change when the clock pulse is applied to the second control input). When the signal 1 is applied to the first control input of the register 6 with the arrival of a clock pulse, the information sent to the second information input is written to the third control input, and when the signal is sent

a la G on the second control input-information filed on the first information input. I

As a counter of 2 clock pulses and a counter of 13 significant samples, a K155IE7 chip can be used, which has summing and subtracting inputs, as well as outputs indicating overflow and equality of contents to zero. At the second output of counter 2, a signal 1 is set when it is full. The output of the counter 13 sets

five

0

five

five

0

c signal O, if its contents are equal to zero.

Chip K155IPS can be used as adders 8-10. A divider 11, a comparison unit 12, a memory unit 14 can also be implemented on 155 series chips.

When signal 1 is applied to the second control unit, the input of the memory unit 14 is switched to the recording mode, and the information is recorded on the leading edge of the pulse fed to the third control input.

The generator 18, which is included in the chronizer 3, is an asymmetrical multivibrator, which uses two anti-phase outputs. The division factor of the frequency divider 19 is determined by the speed at which information is read from memory block 14.

The selection of significant samples during the operation of the device is based on the ratio

 x (t) (t) -fx (t,) j

(one)

where fn, (t) is the maximum approximation error;

k - factor that takes into account the form of the signal under study;

x (t) is the signal under study. As a set point, when allocating significant samples, the value taken is equal to

§.

k; -

where the approximation error is valid. J

Expression

S

(2)

x (t) dt, the input 5 of formula (1), is the average value of the process x (t) over a period of time from 0 to t. As an estimate of the average value of S, we take the sample mean

S (tn) t,), (3)

0

where N is the number of counts received over a period of time from t to

N

(not

corresponding to t); H (t;) - values of the process under study at time points

31280424

j, i 0,1, ..., N, converted into p l l n p te ix

zovany in 1p1frovy code. We denote by S- equal to

) H (to) + H (t).

(four)

Then the formula (1) in view of (2), (3) and (4) takes the form

liritN)., 2S, (t.) - S (t,) AS (tN). H (five)

With the help of the device, at each step of obtaining the next sample, the absolute value iS (tj,) is calculated, which is compared with the setpoint S. If 6 i {iSCtf,), then the next significant count is recorded, equal to the previous current count H (t,), which is taken as the previous significant count. If 5 -i U S (tj,), then the next current sample is analyzed by the device.

The device works as follows.

The operation of the device starts from: the moment when signal 1 is fed to its control input, and the generator 18, which enters into the chrono 3, is started.

Consider the operation of the device on the N-M cycle of determining the next SU

This value is fed to the input of divider 11, by which the binary number from the adder 10 is divided by the number recorded in counter 2, equal to N + 1. Thus, at the output of the divider l 11, we obtain a value equal to S | (tn), defined by formula (3). The code from the output of divider 11 is shifted by one bit toward the higher bits, i.e. the delimiter output value is multiplied by two, fed to the input of the comparison unit 12.

/five

With the help of the comparison unit 12, the absolute value of the value of uS (tj) is determined according to formula (5) and the obtained value is compared with the setpoint, the value of which is determined by formula (2). If iS (tj () t6, then the second output of block 12 is set to the signal O, and the first to 1. The signal from the second output of block 12 is set through the element

 OR 17 (if counter 2 is not completely filled) passes to the control inputs of register 7 and memory block 14, transfer them to storage mode, as well as to input element AND 16, the passage of pulses from chroniser 3 is forbidden, to input of the installation to its original state the counter 2. At the same time, the signal 1 from the first output of the block 12 is fed to the control input pe30

a real countdown. In this case, in register 35, the entry in it in register 7 is permitted to store the value of the previous essential count HCt), in regaster 5 the value of the previous count H (t) (. (), In register 4 the value of the current H (t), in register 6 - the value of H (tfj), equal to

H (tN) 21 H (t;),

ъ 0

Those. the sum of the previous (N-1) samples.

The value, according to formula (4), is determined using an adder 8, to the inputs of which signals are output from registers 4 and 7.

Output 9 value. equally

formation filed on the second information entry. On the leading edge of the pulse from the second output of the chroniser 3 will be overwritten.

40 information from the output of the adder 9 to the register 6, from the register 4 to the register 5, from the output of the converter 1 to the register 4, and the contents of the counter 2 also increase by one.

45, in the (N + 1) -M step, the value written in the H (to) register does not change,. in register 5, the value equal to H (t | i |) will be recorded; in register 4 - Н (t | g,), in register 6 50. , NI

H (t ,,,) H (tj

N41

H (t;)

H (tj H (tJ + H (t.,.,)

N-1

-uj n. - ti: H (t;).

i 0

and in the counter, 2 is a number equal to N + 2., i.e. 55 initial data for the calculation will be prepared. The impulse from the first output of the chroniser 3 triggers the conversion of H (t) H (tf,) + H (t) H (t). 1 by which the input signal is converted into a digital code.

At the output of the adder 10, a value equal to

m

n

This value is fed to the input of divider 11, by which the binary number from the adder 10 is divided by the number recorded in counter 2, equal to N + 1. Thus, at the output of divider 11, we obtain a value equal to S | (tn), defined by formula (3). The code from the output of divider 11 is shifted by one bit toward the higher bits, i.e. the delimiter output value is multiplied by two, fed to the input of the comparison unit 12.

With the aid of the comparison unit 12, the absolute value of the value of uS (tj) is determined according to formula (5) and the obtained value is compared with the setpoint, the value of which is determined by formula (2). If iS (tj () t6, then the second output of block 12 is set to the signal O, and the first to 1. The signal from the second output of block 12 is set through the element

OR 17 (if counter 2 is not completely filled) passes to the control inputs of register 7 and memory block 14, transfer them to storage mode, as well as to input element AND 16, the passage of pulses from chroniser 3 is forbidden, to input of the installation to its original state the counter 2. At the same time, the signal 1 from the first output of the block 12 is fed to the control input of the

formation filed on the second information entry. On the leading edge of the pulse from the second output of the chroniser 3 will be overwritten.

information from the output of the adder 9 to the register 6, from the register 4 to the register 5, from the output of the converter 1 to the register 4, and the contents of the counter 2 also increase by one.

Thus, at the (N + 1) -M step, the value written in the H (to) register does not change,. in register 5, the value equal to H (t | i |) will be recorded; in register 4 - H (t | g,), in register 6. , NI

H (t ,,,) H (tj

N41

H (t;)

which is used in the (N + 2) device operation cycle.

If on the NM cycle the value of iS (t, |) {exceeds the preset setpoint, then on the second ipoM output of block 12 a signal 1 is set, and on the first output an O signal. In this case, the OR 17 element will work, the register 7 and memory block 14 will be set to recording mode, register 6 will be set to the recording mode of information fed to its first information input. On the leading edge of the pulse, from the second output of the chroniser 3, information will be rewritten: from the output of the register 5 to register 6, memory block 14 and into register 6; from the output of divider 11 to memory block 14; from register 4 to register .5; from the output of converter 1 to register 4. Thus, in register 7, the value of H (t ;,) will be recorded, which is subsequently taken as the previous significant reference H (tg), register 5 is the value of H (t, j), 25 the main input of the device, BS1 is the signal to which will be used as a reference H (t,) in the future. pe 4 is the value of H (t ,,), which is further N + r

The next one will be used as a reference H (tj). The value H (tj,.), (i.e. the reference H (to) for the next generation of the next significant reference) will also be written into the register of memory block 14. The latter will also record the average value of the signal between adjacent significant readings from the output of divider 11 and the number of readings between neighboring significant and readings from

at the second output of the comparison unit 12; P - signal at the second output (overflow output) of counter 2; R1 - R4 - the contents of the registers 4-7; S2 is the signal at the output of the adder 9; BP - memory block 14; Ndc „- output converter code 1 .; SS - the contents of the counter 2 clock pulses.

j Improving the accuracy in registering processes of a pulsed nature when using the proposed device, as compared with the prototype, is illustrated in FIG. 3. Let

j Improving the accuracy in registering processes of a pulsed nature when using the proposed device, as compared with the prototype, is illustrated in FIG. 3. Let

output of counter 2. At the same time, the Era-Q process under study has the form of an element AND 16, the pulse from the output of which will increase the contents of counter 13 by one. Acceptable pulses will occur on the falling front of this pulse (Fig. 3a). When applying the prototype, if the first significant count is taken at point 1. (Fig. 35), since the current countdown is taken as the intruder into the initial state.

ka 2, and a number equal to three is recorded in counter 2, since the average value of the three samples recorded in

(when the setpoint is exceeded), then substantial counts will be taken at points 5, 9 and 13. When the signal is recovered from these essential reference lists 4 - 6. The impulse from the first there using linear interpolation

the output of the clock 3 will start the converter 1, etc.

The procedure for recording the next significant reading in memory block 14

the function h (t) will be obtained. When using the proposed device, substantial readings will be taken at points 4,5,8,9,12,13 (Fig. 3 &),

is also carried out in the case of filling in

counter 2. At this, signal 1 is set at the second output of counter 2, under the influence of which the element OR 17 is triggered.

(when the setpoint is exceeded) previous current counts. When the signal is restored, the function h (t) will be obtained. From FIG. 3 8 and b it follows that

In this case, the signal 1 at the second control input of the register 6 cancels the effect on its first control input of the output signal of the comparison block 12

The filling of the memory block 14 is controlled by the counter 13c. In the case when the contents of the counter 13 are non-zero, a signal 1 is set at its output, which permits the passage of pulses from the third output of the synchronizer 3 through the key 15 to the first control input of the memory block 14,

and the accumulated information is transmitted to the output of the device. One or five temporarily pulses arrive at the subtracting input of the counter 13. After zeroing the counter 13, it generates a signal that shatters the key 15, and the transmission of information ends.

The operation of the device is illustrated by an algorithm, the scheme of which is shown in FIG. 2, where the following symbols are accepted: Y is the signal at the control input of the device, BS1 is the signal at

at the second output of the comparison unit 12; - signal at the second output (overflow output) of counter 2; R1 - R4 -. register contents 4-7; S2 is the signal at the output of adder 9; BP - memory block 14; Ndc „- output converter code 1 .; SS - the contents of the counter 2 clock pulses.

Improving the accuracy in registering processes of a pulsed nature when using the proposed device, as compared with the prototype, is illustrated in FIG. 3. Let

The process under study has the form of np-angle pulses (Fig. 3a). When applying the prototype, if the first significant count is taken at point 1. (Fig. 35), since the current reading is taken as an essential one.

(when the setpoint is exceeded), then substantial samples will be taken at points 5, 9 and 13. When the signal is restored from these essential samples using linear interpolation

the function h (t) will be obtained. When using the proposed device, substantial readings will be taken at points 4,5,8,9,12,13 (Fig. 3 &),

how much is taken

(at excess of setpoint) previous current counts. When the signal is restored, the function h (t) will be obtained. From FIG. 3 8 and b it follows that

one

the function h (t) reproduces the original signal with greater accuracy.

Thus, the proposed device makes it possible to increase the accuracy of recording signals having a pulsed character due to the fact that it takes the current and the preceding current reading as the essential one. It also allows to provide the maximum approximation error of the signal under study, which does not exceed the specified one. To estimate the discrepancy between the process and the approximating process, the value used is determined by the maximum approximation error, which facilitates the choice of setpoint. The device combines the operations of converting an analog signal to a digital using converter 1 and calculating the value of uS (t |) (each subsequent cycle processes the results obtained from converter 1 in the previous cycle), which also improves the speed of the device. In memory block 14, the mean value of counts between the significant ones is also recorded, along with the significant readings. In the prototype, in order to obtain averaged values, at the receiving side it is necessary to perform additional computational operations on the data obtained.

Claims (3)

The invention relates to telemetry and can be applied in adaptive telemetry systems. The purpose of the invention is to increase the accuracy of the device. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of the device operation algorithm; in fig. 3 - graph of input and output signals. The device contains (Fig. 1) analog-to-digital converter 1, the first counter 2 clock pulses, the clock 3, the first to the fourth registers 4-7, the first to the third adders 8-10, the divider 11, the comparison unit 12, the second counter 13 essential samples, a memory block 14, a key 15, an AND 16 element and an OR 17 element. The timing device is made of a pulse generator 18 and a pulse frequency divider 19. Register 4 is used to hold the current count, a register. 5 for the storage of the previous current reference, register 6 for the storage of the previous significant reference, register 7 for the storage of the results of intermediate calculations. As these registers, K155IR13 chips can be used, which are written to by a positive differential pulse applied to their sync input. When the signal O is applied to the first control input of the register 7, it enters the storage mode (its state does not change when the clock pulse is applied to the second control input). When signal 1 is applied to the first control input of register 6, the clock pulse arrives at the third control input, the information fed to the second information input is recorded into it, and when the signal G is fed to the second control input information fed to the first information input. I As a counter of 2 clock pulses and a counter of 13 significant samples, a K155IE7 chip can be used, which has summing and subtracting inputs, as well as outputs that indicate overflow and equality of contents to zero. At the second output of counter 2, a signal 1 is set when it is full. The output of the counter 13 sets the signal O, with the equality of its contents to zero. Chip K155IPS can be used as adders 8-10. A divider 11, a comparison unit 12, a memory unit 14 can also be implemented on 155 series chips. When signal 1 is applied to the second control unit, the input of the memory unit 14 is switched to the recording mode, and the information is recorded on the leading edge of the pulse fed to the third control input. The generator 18, which is included in the chroniser 3, is an asymmetrical multivibrator, which uses two anti-phase outputs. The division factor of the frequency divider 19 is determined by the speed at which information is read from memory block 14. The selection of significant samples during the operation of the device is made on the basis of the ratio x (t) (t) -fx (t,) j where fn, (t) is the maximum approximation error; k - factor that takes into account the form of the signal under study; x (t) is the signal under study. As a setting, when allocating significant samples, the value taken is equal to k; where the approximation error is permissible. J x (t) dt, the input Expression in formula (1), is the average value of the process x (t) over a period of time from O to t. As an estimate of the average value of S, we take the sample mean S (tn) t,), (3) where N is the number of counts obtained over a period of time from t to the corresponding point t); H (t;) is the values of the process under study at the time points of 3 tj, i 0,1, ..., N, converted into a 1-digit code. Denote by S- the value, equal to) H (to) + H (t). Then the formula (1) with regard to (2), (3) and (4) takes the form liritN)., 2S, (t.) - S (t,) AS (tN). H (5) Using the device, at each step of obtaining the next sample, the absolute value of iS (tj,) is calculated, which is compared with the setpoint S. If 6 i {iSCtf,), then the next significant count is recorded, equal to the previous current count H (t,), which is taken as the previous substantial count. If 5 -i U S (tj,), then the next current sample is analyzed by the device. The device works as follows about the first time. The operation of the device starts from: the moment when the signal 1 is fed to its control input, and the generator 18, which enters the chroniser 3, is started. Consider the operation of the device on the N-M cycle of determining the next significant count. In this case, the register 7 stores the value of the previous essential HCt count) in the regaster 5 - the value of the preceding current count H (t) (. (), In register 4 - the value of the current count H (t), in register 6 - the value H ( tfj), equal to H (tN) 21 H (t;), i.e. the sum of the previous (N-1) counting Value), according to the formula (4), is determined using adder 8, to the inputs of which signals are output registers 4 and 7. At the output of the adder 9 value. equal to H (tj H (tJ + H (t.,.,)) -uj n. - ti: H (t At the output of the adder 10, a value equal to H (t) H (tf,) + H (t) H ( t 4 This value is fed to the input of the divider 11, which divides the binary number coming from the adder 10 by the number written in the counter 2, equal to N + 1. Thus, at the output of the divider 11, we get the value equal to S | (tn ), determined by the formula (3). The code from the output of the divider 11, shifted by one bit towards the higher bits, i.e. the value at the output of the divider is multiplied by two, is fed to the input of the comparison unit 12. With the help of the block 12 Wed The absolute value of the value of uS (tj) is determined according to formula (5) and the obtained value is compared with a setpoint, the value of which is determined by formula (2). If iS (tj () t6), the second output of the block 12 sets the signal O, and on the first - 1. The signal O from the second output of block 12 through the OR element 17 (if counter 2 is not completely filled) passes to the control inputs of the register 7 and memory block 14, transferring them to the storage mode, and also to the input of the element And 16, the passage of pulses of the chroniser 3 to the input of the installation to the initial state is prohibited ue counter 2. At the same time, the signal 1 from the first output unit 12 is supplied to a control input of the register 6 to permit the entry of information into it, filed on second information input. On the leading edge of the pulse from the second output of the chronizer 3, information from the output of the adder 9 to the register 6 will be overwritten, from the register 4 to the register 5, from the output of the converter 1 to the register 4, and the counter 2 will also increase by one at the (N + 1) -M step, the value written in the H (to) register does not change,. in register 5, the value equal to H (t | i |) will be pushed; in register 4 - H (t | g,), in register 6. , N-I Н (t ,,,) Н (tj Н (t;) and in counter 2 is a number equal to N + 2., I.e. the initial data will be prepared for the calculation.). A pulse from the first output of the chroniser 3 triggers a converter 1, with which the input signal is converted into a digital code. which is used in the (N + 2) device operation cycle. If on the NM cycle the value iS (t, |) {exceeds the preset setpoint, then on the second ipoM output of block 12 a signal 1 is set, and the first output is signal O. At this, the element OR 17 will be activated, the register 7 and memory block 14 will be set In recording mode, register 6 will be set to the recording mode of information submitted to its first information input. On the leading edge of the pulse from the second output of the chroniser 3, information will be rewritten: from the output of register 5 to register 6, memory block 14 and to register 6; from the output of divider 11 to memory block 14; from register 4 to register .5; from the output of converter 1 to register 4. Thus, in register 7, the value H (t ;,) will be recorded, which is subsequently taken as the previous significant reference H (tg), register 5 is the value H (t, j) will be used as a reference H (t,), in register 4 - the value of H (t ,,), which will later be used as a reference H (tj). The value of H (tj,.,) (i.e. The H (to) readout for the next generation of the next significant readout will also be written to the register of the memory block 14. In the latter, the average value of the signal between adjacent significant readings from the output of divider 11 and the number of readings between neighboring significant and readings from the output of counter 2 will also be recorded. At the same time, the element 16 also operates, the pulse from the output will increase by one the content of the counter 13. On the falling front This pulse will be reset to the initial state of the CH 2 counter, while a counter equal to three will be written to the counter 2, since the average value of three samples recorded in registers 4-6 will be calculated at this clock cycle. The impulse from the first output of the clock 3 will start up the converter 1, etc. The procedure for recording the next significant count in the memory block 14 is also carried out in the case of filling the counter 2. At the same time, signal 1 is set at the second output of counter 2, under the influence of which the element OR 17 is triggered. At the same time, signal 1 at the second control input of register 6 cancels the effect on its first control input of the output signal of comparator unit 12 Filling unit 14 the memory is controlled by the counter 13c. In the case when the contents of the counter 13 are different from zero, a signal 1 is set at its output, which permits the passage of pulses from the third output of the clock 3 through the key 15 to the first control input of the memory block 14, and transfer of the accumulated information to the output of the device comes off. At the same time, the pulses go to the subtracting input of the counter 13. After zeroing the counter 13, it generates a signal that shakes the key 15, and the transmission of information ends. The operation of the device is illustrated by an algorithm, the scheme of which is shown in FIG. 2, where the following symbols are accepted: Y is the signal at the control input of the device, BS1 is the signal at the second output of the comparison unit 12; P - signal at the second output (overflow output) of counter 2; R1 - R4 -. register contents 4-7; S2 is the signal at the output of the adder 9; BP - memory block 14; Ndc „- output converter code 1 .; SS - the contents of the counter 2 clock pulses. Improving the accuracy in registering processes of a pulsed nature when using the proposed device, as compared with the prototype, is illustrated in FIG. 3. Let the process under investigation be in the form of nr-angle pulses (Fig. 3a). When applying the prototype, if the first significant count is taken at point 1. (Fig. 35), since the current count is taken as a significant one (when the setpoint is exceeded), then substantial readings will be taken at points 5, 9 and 13. When the signal is restored from these significant readings using linear interpolation, h (t) function. When using the proposed device, substantial readings will be taken at points 4,5,8,9,12,13 (Fig. 3 &), since previous current readings are taken as essential ones (when the setpoint is exceeded). When the signal is restored, the function h (t) will be obtained. From FIG. 3 8 and b it follows that 11 the function h (t) reproduces the original signal with greater accuracy. Thus, the proposed device allows to increase the accuracy of recording signals of a pulsed nature due to the fact that the current reading and the previous reading are taken as essential. It also allows to provide the maximum approximation error of the signal under study, which does not exceed the specified one. To estimate the discrepancy between the process and the approximating process, the value used is determined by the maximum approximation error, which facilitates the choice of setpoint. The device combines the operations of converting an analog signal to a digital using converter 1 and calculating the value of uS (t |) (each subsequent cycle processes the results obtained from converter 1 in the previous cycle), which also improves the speed of the device. In memory block 14, the mean value of counts between the significant ones is also recorded, along with the significant readings. In the prototype, in order to obtain averaged values, on the receiving side, it is necessary to perform additional computational operations on the obtained data. Claims An apparatus for transmitting data with compression comprising an analog-to-digital converter, the information input of which is the information input of the device, the output of the analog-digital converter is connected to the information input of the first register whose output is connected to the information input of the second register and the first input of the first adder, the first counter, the first output of which is connected to the first information input of the memory block and the first input of the divider, the output of the divider is connected to the first input of the block comparison, the first output of which is connected to the first control input of the third register, the output of which is connected to the first input of the second 24 adder, the chronizer, the input of which is the control input of the device, the first, second and third outputs of the chroniser are connected respectively to the control inputs of the analog the digital converter, the first register and the key information input, the key output is connected to the first control input of the memory unit and the subtractive input of the second counter, the output of the second counter is connected to the control the key input, the output of the memory block is the output of the device, the quarter register and the third adder, which is the fact that, in order to increase the accuracy of the device, the AND element and the OR element are entered into it, the second register output is connected to the first information input of the third register, the second information input of the memory unit, the second input of the second adder and the information input of the fourth register, the output of the fourth register are connected to the second input of the first adder, the output of which is connected to the second input of the comparison unit, The output of which is connected to the first input of the OR element, the output of which is connected to the first control input of the fourth register by the second control inputs of the memory unit and the third register and the first input of the And element, the output of the And element is connected to the summing input of the second counter and the installation input to the initial the state of the first counter, the second output of the first counter is connected to the second input of the OR element, the output of the second adder is connected to the second information input of the third register and the first input of the third adder, the second The third input of the adder is connected to the output of the first register, the output of the third adder is connected to the second input of the divider, the third information input of the memory unit is connected to the output of the divider, the combined counting input of the first counter, the second input of the And element, the control input of the second register, the second control input the fourth register and the third control inputs of the memory unit and the third register are connected to 55 the second output of the chroniser.