SU1278883A1 - Device for generating addresses of truncated fast fourier transform processor - Google Patents

Abstract

The invention relates to radio engineering and computing and can be used in digital signal processing devices. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the device contains two shift registers, two counters, a control unit, two adders, two shift blocks, an AND element, two comparison blocks, a counter block, two AND element blocks, an OR element, and a register block. Moreover, the control unit contains six NOT elements, six AND elements, three RS-flip-flops, ten OR elements, a decoder and a clock generator. The device generates at each step of the algorithm only the addresses that are needed to calculate the desired samples of the discrete signal spectrum. Thanks to this, the processor does not perform unnecessary counts. 7 pe.

Description

one

The invention relates to radio engineering and computing and can be used in digital signal processing devices.

The purpose of the invention is to increase the speed. in and .

To clarify the essence of the invention, we compare the conventional and truncated FFT algorithms. In the case when the number of signal samples is equal to the degree of two, i.e. The discrete spectrum of the signal can be calculated in p steps and with recurrent formulas.

x. ,, (p) -X; (p) + x; ()

X;, (P-L2 -) X; (p) -X; (p + 2 -) W

where i is maraj number

X;, x; + | - input and output data for i i -ro schaga;

P, - numbers of samples in the arrays of input and output data; W - trigonometric coefficient, and

w exp (Z MAFT / N)

in the formulas given. 2 and .2,

Where

oGS-;

1 0.2 -I,

m

Since a periodic discrete function k with period N, it suffices to form an array of trigonometric coefficients and samples, In this case, W corresponds to the k-th sample in the array.

FIG. 1 shows an example of a directed graph diagram of an FFT algorithm for case N 2. In this scheme, the graph vertices (points) correspond to data readings. At each step of the algorithm, lines without arrows correspond to simple data transmission, lines with arrows correspond to transmission with preliminary multiplication by a trigonometric coefficient. The + or - sign near the top of the graph indicates the operation by which the corresponding count was obtained. Below, the graphs of the FFT algorithm are indicated for each step i of the value, which take the variables m and 1. In the example under consideration, 12 complex multiplication operations are required to determine the discrete signal spectrum.

O

five

0

five

0

five

0

five

0

five

In the truncated FFT algorithm, it is required to find M (M "N) samples of the discrete spectrum of the signal with the numbers b ,, bj, ..., b, where bj are integers from the interval (O, Nl). It is enough to determine at each conversion step only those samples that are required in the next step.

FIG. 1 blackened the vertices of the graph of the FFT algorithm corresponding to the data samples that must be determined at each step to calculate the samples of the discrete spectrum of the signal numbered 3 and 7. Thus, the blackened vertices of the graph form a graph-truncated truncated FFT algorithm for the case when M 2 , B, 3, lg 7.

When using the truncated FFT algorithm, the calculation is carried out using the same formulas, but the variable m takes the value m (bj) mod, where j 1, 2. .. I.

In this example, to calculate the desired spectral samples, it is necessary to perform 8 operations of complex multiplication, i.e. one third less than when using the normal FFT algorithm. The win is achieved by the fact that this device for generating the addresses of the truncated FFT processor generates at each step of the algorithm only those addresses that are needed to calculate the desired samples of the discrete signal spectrum. Due to this, the processor does not perform operations with unnecessary readings.

FIG. Figure 1 shows the truncated FFT algorithm; in fig. 2 is a block diagram of the device; in fig. 3 is a block diagram of a block of registers, a block of elements And, a block of counters and a block of fixation zero; in fig. 4 - device operation algorithms; in fig. 5 - time diagrams; Fig. 6 is a control block diagram; in fig. 7 is a logical node diagram.

The device (Fig. 2) contains the registers 1 and 2 of the shift, the counters 3 and 4, the shifters 5 and 6, the element And 7, the adders 8 and 9, the blocks 10 and 11 of the comparison, the block 2 registers, the block 13 elements And, the block 14 account 1 ticks, zero fixing unit 5 and control unit 16, control unit outputs 17-22, control unit inputs 23-26, output 27

fO

15

20

31278883

coefficient addresses, outputs 28 and 29 addresses of the first and second operands, respectively.

FIG. 3 shows the diagrams of a block of 12 registers, a block of 13 elements And, a block of 14 counters and a block I5 of fixing zero. Block 12 of registers contains registers 30, the number of which is not less than the number of sought samples of the discrete spectrum of signal M. Block 14 of counters contains the corresponding number of counters 31. Block 13 of elements And contains M groups of elements AND, the number of elements And 32 in each group being equal to the size of registers 30. Fixing unit zero includes a block of AND elements consisting of AND 33 elements, the number of which is equal to the number of counters 31, and the OR element 34.

The control unit (Fig. 6) contains a decoder 35, triggers 36-38, elements AND 39-46, elements OR 47-52, elements HE 53-55, resistor 56, capacitor 57, logic node 58, generator 59 clock pulses.

The logical node (Fig. 7) contains elements NOT 60-62, elements AND 63-65 with output 66, elements AND 67-71, elements OR 72-75.

To explain the operation of the device in FIG. 4 shows the flowchart of the algorithm of its work. In the flowchart, the following notation is used:

Pr1 - first shift register 1;

Pr2 - second shift register 2;

Sch1 - the first counter 3;

Sch2 - second counter 4;

BLSch - block 14 counters;

CM1 - the first adder 8;

Cm2 - second adder 9; Cksd - the second shifter 6; : - means recording information;

 means the entry bit S S;

I1 (Pr - means the shift of the contents of Pr to the left by one bit;

P1, P2, RZ, P4 - signals at inputs 23-26 of control unit 16 .50

U1, U2, UZ, U4, U5, U6 - signals at the outputs. 17-22 control unit 16.

To clarify the operation of the device to form the addresses of the truncated FFT processor, we also use the time diagrams shown in FIG. 4. Time diagrams are constructed for the case when N 8, M

2 bel. on and his ly Pr Pr ra ra

with that

si and in pi by na and sc re 5 ci by pa but by pa 31

chi 00 in de from et ho 45 so on to pr on da ro adi

sl ta ve cr

thirty

35

40

55

gd

O

five

0

2, 3, 3 b. The diagram shows the signals CC formed inside the control block 1 6 (CU-), the signals P1, P2, RH and P4 at its inputs and the signals U1, U2, OZ, U4. Y5, Y6 at its exits. Signals at the direct outputs of bits Pr1, Pr2, MF, MF2 are also given. B In accordance with the considered example, Pr1 and Pr2 are three-bit, and Sch1 and Sch2 are two-digit.

The device for generating the addresses of the truncated FFT processor works as follows.

After launching the CU, it generates a signal U1, which sets Pr1 and Pr2 to the parallel information recording mode, and a signal U5, which records code 001 at Pr1 and Pr2, and when the next pulse arrives, the CC CU generates signals U2, Ultrasound and U5. The first of them establishes Sch2 and Sch1, as well as counters 31 in the mode of parallel recording of information. 5 The ultrasonic signal has zeroed Sch1 and, in each counter 31, writes a code that is obtained as a result of a bitwise logical multiplication of the code recorded in one of the registers of block 30 by the code recorded in the higher r-1 bits of Pr2. In this case, the codes are recorded in the counters 31.

(bj),

codes recorded in registers 30.

In this example, code 00 is then written to counters 31. Signal V4 zeroed M2. Since O is recorded in the counters 31, a logical unit (P4 1) appears at the output of the zero fixing unit 15. In this case, the algorithm performs the transition from vertex 4 to vertex 7, which 5 corresponds to the formation of V6 upon receipt of the next pulse of signal CC. This signal informs the processor that at the output of Cm2 there is an address L1 (the first operand, at the outputs Cm1 the address A2 of the second operand and at the outputs Cxd the address A3 of the trigonometric coefficient).

In this example, in this case, AI 000, A2 001, and A3 000. Since O is written in M2, and the inverse outputs of all C2 bits, except for the minor, is code 11,

0

five

0

where b; at the output of unit 11, it finds with logic zero (O3). Therefore, the algorithm proceeds from the vertex 8 to the vertex 9. Since the V2 signal is not generated, the V4 signal adds one to the content of C2. After that, the signals U6 at the outputs Sm1, Sm2 and CSCD read the addresses A1 010, and A3 000. In the next cycle, codes 100, 101, 000 and finally, codes 110, 111 and 000 are read. The logical unit is, since code 11 is written with M2. Since the logic unit (P2 1) is also set at the output of the comparison unit 10, the transition to the vertex 10 of the flowchart algorithm is established. The signal U5 generated in this case shifts the contents of Pr1 and Pr2 to the left by one bit. The least significant bit Pr1 is the logical zero, and Pr2 is the logical one. Since the Pr1 recorded not zero, the signal. Therefore, the transition to the top 3 of the algorithm is complete. A new entry is made in the counters 31. In this example, the code O is recorded. At the output of the zero-fixing unit I5, a logical zero (P4 o) appears. Since the output of the comparator unit 10 is also zero (), an ultrasound signal is generated, which adds 1 to the content of Sc1 and subtracts 1 from the contents of the SG counters. As a result, the counters 31 are zeroed out and the signal P4-1 appears. Therefore, the transition to the vertex 7 of the algorithm is performed and the address A1 001, A2 011 and A3 010 is read. In the next cycle, the content of Sc 2 is incremented and the addresses are counted. A1 " 101, A2 1 P and A3 010. Then the next shift of the codes in Pr1 and Pr2 and a new entry into the counter 31 takes place. This time the code I1 is recorded in them. Since there is a call to the top 6 of the algorithm. After three calls, the counter 31 is nullified, and code 11 appears in the Sc1. When the next pulse of the signal appears, the CC BU generates V6, and the codes 101, 111, 011 are read from the CM1, Cm2, and CxCd outputs. code shift in Pr1 and Pr2. Since Pr1 is zeroed in this case, the VU at the signal P4 from the output of the And 7 element stops the operation of the device 278883 6

facilities to form a truncated FFT processor address.

Claims (1)

1 The invention relates to radio engineering and computing and can be used in digital signal processing devices. The object of the invention is to increase the speed of speed. To clarify the essence of the invention, we compare the conventional and truncated FFT algorithms. In the case when the number of signal samples is equal to the degree of two, i.e. The discrete spectrum of the signal can be calculated in p steps and with recurrent formulas. x., (p) -X; (p) + X; () X;, (P-L2-) X; (p) -X; (p + 2-) W where i is the number maraj X ;, x; + | - input and output data for i i-ro schaga; P, - numbers of samples in the arrays of input and output data; W is a trigonometric coefficient, and w exp (ZMAFT / N) in the above formulas .2 and .2, oGS-; 1 0,2 -I, Since a periodic discrete function k with a period N, it is sufficient to form an array of trigonometric coefficients and samples, At the same time, W corresponds to the k-th sample in the array. FIG. 1 shows an example of a directed graph diagram of an FFT algorithm for case N 2. In this scheme, the vertices of the graph (points) correspond to data readings. At each step of the algorithm, lines without arrows correspond to simple data transfer, lines with arrows correspond to transfer with a preliminary multiplication by a trigonometric coefficient. The + or - sign near the top of the graph indicates the operation by which the corresponding count was obtained. The bottom graph of the FFT algorithm is indicated for each step i, the values that take the variables m and 1. In this example, to determine the discrete spectrum of the signal, it requires to perform 12 operations of complex multiplication. 3 In the truncated FFT algorithm, it is required to find M (M N N) samples of the discrete spectrum of the signal with the numbers b ,, bj, ..., b, where bj are integers from the interval (O, Nl). It is enough at each conversion step identify only those samples that are required in the next step. FIG. 1 blackened the vertices of the graph of the FFT algorithm corresponding to the data samples that must be determined at each step to calculate the samples of the discrete spectrum of the signal with numbers 3 and 7. Thus, the blackened vertices of the graph form a graph-diagram of the truncated FFT algorithm for the case where M 2, b , 3, Lg 7. When using the truncated FFT algorithm, the calculation is carried out using the same formulas, but the variable m takes the value m (bj) mod, where j 1, 2. .. I. In the example under consideration, to calculate the desired spectral samples, it is necessary to perform 8 operations of complex multiplication, i.e. one third less than when using the normal FFT algorithm. The gain is achieved by the fact that this device for generating the addresses of the truncated FPF processor forms at each step of the algorithm only those addresses that are needed to calculate the desired samples of the discrete signal spectrum. Due to this, the processor does not perform operations with unnecessary readings. FIG. Figure 1 shows the truncated FFT algorithm; in fig. 2 is a block diagram of the device; in fig. 3 is a block diagram of a block of registers, a block of elements And, a block of counters and a block of fixation zero; in fig. 4 - device operation algorithms; in fig. 5 - time diagrams; Fig. 6 is a control block diagram; in fig. 7 is a logical node diagram. The device (Fig. 2) contains the registers 1 and 2 of the shift, the counters 3 and 4, the shifters 5 and 6, the element And 7, the adders 8 and 9, the blocks 10 and 11 of the comparison, the block 2 registers, the block 13 elements And, the block 14 account 1 ticks, zero fixing unit 5 and control unit 16, control unit outputs 17-22, control unit inputs 23-26, output 27 3 of the coefficient addresses, outputs 28 and 29 of the address of the first and second operands, respectively. FIG. 3 shows the diagrams of a block of 12 registers, a block of 13 elements And, a block of 14 counters and a block I5 of fixing zero. Block 12 of registers contains registers 30, the number of which is not less than the number of sought samples of the discrete spectrum of signal M. Block 14 of counters contains the corresponding number of counters 31. Block 13 of elements And contains M groups of elements AND, the number of elements And 32 in each group being equal to the size of registers 30. The fixing unit zero includes an AND block consisting of AND elements 33, the number of which is equal to the number of counters 31, and the OR element 34. The control block (FIG. 6) contains a decoder 35, triggers 36-38, And elements 39-46, elements OR 47-52 elements HE 53-55, resistor 5 6, the capacitor 57, the logic node 58, the generator 59 clock pulses. The logical node (Fig. 7) contains elements NOT 60-62, elements AND 63-65 with output 66, elements AND 67-71, elements OR 72-75. To explain the operation of the device in FIG. 4 shows the flowchart of the algorithm of its work. The following notation is used in the flowchart: Pr1 is the first shift register 1; Pr2 - second shift register 2; Sch1 - the first counter 3; Sch2 - second counter 4; BLSch - block 14 counters; CM1 - the first adder 8; Cm2 - second adder 9; Cksd - the second shifter 6; : - indicates the recording of information; means the entry bit S S; I1 (Pg - means shifting the contents of Pg to the left by one bit; P1, P2, P3, P4 - signals to inputs 23-26 of control unit 16. U1, U2, UZ, U4, U5, U6 - signals at outputs 17.- 22 control units 16 To clarify the operation of the device for generating the addresses of a truncated FFT processor, we also use the time diagrams shown in Fig. 4. The time diagrams are plotted for the case when N 8, М 83 2, Ь 3, Ь 7. The diagram shows signals CCs formed inside the control block 1 6 (CU-), signals of Р1, Р2, РЗ and Р4 at its inputs and signals У1, У2, УЗ, У4. У5, У6 at its outputs. The signals at the direct outputs of bits P1, Pr2, MF, MF2 are also given. B According to the considered example, Pr1 and Pr2 are three-bit, and MF1 and MF2 are two-digit. A device for forming the addresses of a truncated FFT processor works as follows. it generates a signal V1, which sets Pr1 and Pr2 to the parallel information recording mode, and a signal U5, which records 001 in Pr1 and Pr2. When the next pulse arrives, the CC BU generates signals U2, OZ and U5. The first of them establishes Sch2 and Sch1, as well as counters 31 in the mode of parallel recording of information. The ultrasonic signal has zeroed Sc1 and recorded into each counter 31 a code which is obtained as a result of a bitwise logical multiplication of the code recorded in one of the registers of block 30 by the code recorded in the higher r-1 bits of Pr2. In this case, codes (bj) are written in the counters 31, where b; codes recorded in registers 30. In the considered example, code 00 is written to counters 31. Signal V4 reset C2. Since O is recorded in the counters 31, a logical unit (P4 1) appears at the output of the zero fixing unit 15. In this case, the algorithm performs the transition from vertex 4 to vertex 7, which corresponds to the formation of V6 upon receipt of the next pulse of the signal CC. This signal informs the processor that at the output of Cm2 there is an address L1 (the first operand, at the outputs Cm1 the address A2 of the second operand and at the outputs Cxd the address A3 of a trigonometric coefficient). In this example, in this case, AI 000, A2 001, and A3 000. Since O is recorded in Mid2, and the inverse outputs of all the Midrange bits, except for the younger one, is code 11, at the output of the control unit 11 it finds a logical zero with the output unit 11 ABOUT). Therefore, the algorithm proceeds from the vertex 8 to the vertex 9. Since the V2 signal is not generated, the V4 signal adds one to the content of C2. After that, the signals U6 at the outputs Sm1, Sm2 and CSCD read the addresses A1 010, and A3 000. In the next cycle, codes 100, 101, 000 and finally, codes 110, 111 and 000 are read. The logical unit is, since code 11 is written with M2. Since the logic unit (P2 1) is also set at the output of the comparison unit 10, the transition to the vertex 10 of the flowchart algorithm is established. The signal U5 generated in this case shifts the contents of Pr1 and Pr2 to the left by one bit. The least significant bit Pr1 is the logical zero, and Pr2 is the logical one. Since not zero is recorded in Pr1, the signal therefore makes the transition to the top 3 of the algorithm complete. A new entry is made in the counters 31. In this example, the code O is recorded. At the output of the zero-fixing unit I5, a logical zero (P4 o) appears. Since the output of the comparator unit 10 is also zero (), an ultrasonic signal is generated, which adds 1 to the content of Sc1 and subtracts 1 from the contents of the SG counters. As a result, the counters 31 are zeroed out and the signal P4-1 appears. Therefore, the transition to the vertex 7 of the algorithm is performed and the address A1 001, A2 011 and A3 010 is read. In the next cycle, the content of Sc 2 is incremented and the addresses are counted. A1 " 101, A2 1 P and A3 010. Then the next shift of the codes in Pr1 and Pr2 and a new entry into the counter 31 takes place. This time the code I1 is recorded in them. Since there is a call to the top 6 of the algorithm. After three calls, the counter 31 is nullified, and code 11 appears in the Sc1. When the next pulse of the signal appears, the CC BU generates V6, and codes 101, 111, 011 are read from the CM1, Cm2, and CxCd outputs. Then another code shift occurs in Pr1 and Prg2. Since Pr1 is thus zeroed out, the VU on signal P4 from the output of the And 7 element stops the operation of the device for generating the addresses of the truncated FFT processor. The invention The device for generating addresses of a truncated fast Fourier transform processor, comprising a first shift register, first and second counters, a control unit, the first output of which is connected to the installation inputs of the first and second counters, the counting inputs of which are connected respectively to the second and third outputs of the control unit, The fourth and fifth outputs of which are connected respectively to the clock input and the control input of the shift direction of the first shift register, characterized in that The first and second adders, the second shift register, the first and second shifters, the AND element, the first and second comparison blocks, the block of counters, the first and second blocks of AND elements, the OR element and the register block, the i-th output (, r, r - the width of which is connected to the i-th input of the first block of I elements, the i-th output of which is connected to the i-th, information input of the counter block, the i-th information output of which is connected to the i-th input of the second block elements AND, the i-th output of which is connected to the i-th input of the OR element, the output of which is connected to the first input of the control unit, the first, second, fourth and fifth outputs of which are connected respectively to the installation and counting inputs of the block of counters and the clock and installation inputs of the second shift register, jth (j 2, d) bit direct whose output is connected to the (j + rl) -My input of the first block of elements And and the (J-1) input of the first comparison block, the output of which is connected to the second input of the control unit, the third input of which is connected to the output of the second comparison block (J- 1) th input of which is connected to the discharge the inverse output of the second shift register, the i-th bit of the direct output of the first shift register is connected to the i-th input of the first sum of the math, the i-th input of the shift control of the first shift, the i-th output which is connected to the i-th input of the second adder, the i-th output of which is the iM address output of the first operand of the device and connected to the (1 + g) -th input of the first adder, the i-th output of which is the iM address output of the second operand of the device The output of the address of the coefficient of which is the 1st output of the second shifter (jl) ft whose shift control input is connected to (jl) -My a bit of the direct output of the first shift register, the i-th bit of the inverse output of which is connected to the i-th the input element And, the output of which is connected to the fourth input for the control unit, (Jl) th output of the first counter is connected to (j + r-2) -My the input of the first comparison block, (jl) -My to the information input of the second shifter and (j + rl) -My to the input of the second adder The (jl) th output of the second counter is connected to the (j + r-2) -My input of the second comparator unit and (jl) the information input of the first shifter, the sixth output of the control unit is the device sync output, the control unit contains ten OR elements, six NOT elements, six AND elements, three RS flip-flops, a decoder and a clock pulse generator Bits, the output of which is connected to the first inputs of the elements I from the first to the sixth, to the input of the first element NOT, the output of which is connected to the synchronization inputs of the first, second and third RS flip-flops, whose outputs are connected respectively to the first, second and third inputs of the decoder, the first and the second outputs of which are connected respectively to the first and second inputs of the first element OR, the output of which is connected to the first inputs of the second and third elements OR, the outputs of which are connected respectively to the R input of the first RS flip-flop and the first input of the seventh AND element, the output of which is connected to the S input of the second RS flip-flop, the third output of the decoder is connected to the second input of the first AND element, the first input of the fourth OR element and the first input of the fifth OR element, the output of which is connected to the input of the first RS -t.rigger, the fourth output of the decoder is connected to the second input of the element AND, the first inputs of the sixth and seventh elements OR, the first input of the eighth and tenth elements And the outputs of which are connected - corresponding to the input of the third RS-trngger, the second input the second element OR and the first input of the eighth element OR, the output of which is connected to the first input of the ninth element OR, the output of which is connected to the R input of the second RB flip-flop, the fifth output of the decoder is connected to the second input of the third element And and the first inputs of the eleventh, twelfth and thirteenth elements And, the outputs of which are connected respectively to the second and third inputs of the eighth the OR element and the second input of the fifth OR element, the sixth output of the decoder is connected to the second input of the seventh OR element and the first inputs of the fourteenth and fifteenth AND elements whose outputs are connected respectively to the third input of the second OR element and the fourth input of the eighth OR element, the seventh output of the decoder is connected to the second input of the fourth OR element, the first input of the tenth OR element, and the first input of the sixteenth element AND, the output of which is connected to the second input of the third OR element, the third input which is combined with the second input of the sixth element OR and connected to the eighth output of the decoder, the second inputs of the seventh and eighth elements AND are combined and connected to the output of the second element NOT, the input of which is combined with V The third inputs of the ninth and tenth elements OR are connected to the output of the third element NOT, the input of which is the input setting the logical unit of the device, the outputs of the first, second and third elements I are the fifth, first and sixth outputs of the block, the fourth, the third and the second outputs of which are the outputs of the fourth, fifth and sixth AND elements, respectively, the second inputs of which are connected to the outputs of the fourth, sixth and seventh OR elements, respectively, the second input of the sixteenth element AND to the output of the fourth element NO, the input of the fourth block is input, the second input of which is connected to the second inputs of the eleventh and fifteenth elements And, the second input of the twelfth element And connected to the output of the fifth element NOT, the input of which is combined with the second input of the thirteenth element And and is the third input of the block, the first input of which is connected to the second inputs of the ninth and fourteenth elements And the input of the sixth element is NOT, the output of which is connected to the second input of the tenth and the third input of the fifteenth elements I. 7 1 b Fmg 7