SU1086438A1 - Fast fourier transform processor - Google Patents

Abstract

1. QUICK CONVERSION PROCESSOR. FURIET, containing arithmetic unit, first and second memory locks, Permanent Memory block, control unit, three address formers, two And elements, and two PfflH elements, with the outputs of the first and second And elements connected to the first the inputs of the first and second elements OR, respectively, whose outputs are connected respectively to the first and second-input operands of the arithmetic unit, the inputs of the real and imaginary parts of the coefficients of which are connected respectively to the first and second outputs The direct memory blocks, whose input is connected to the output of the first address generator, the outputs of the second and third address drivers, are connected to the address inputs of the first and second memory blocks, respectively, the first and second outputs of which are respectively combined and are the first and second information outputs, respectively processor, and the first inputs of the first and second elements And are respectively the first and second information inputs of the processor, characterized in that, in order to improve speed processor, it contains the first, second, third and fourth elements 2 AND-OR, the first and second adders modulo 2, the first and second elements are NOT, with the first output of the control unit connected to the first inputs of the first and second elements 2 AND-OR, outputs which are connected to the second inputs of the first and second ICH elements, respectively, the second output of the control unit is connected to the second inputs of the first and second elements 2 AND-OR, the third and the fourth (Lt inputs of which are connected respectively to the first and second outputs of the first memory block, the third output of the control unit is connected to the second inputs of the first and second elements And, the fourth output of the control unit is connected to the input of the first 00 address generator, the fifth output of the control unit is connected to the input 4 of the information reception control of the arithmetic unit, the outputs of the valid part of the first and third 00 operands of which are connected to the first inputs of the third and fourth elements 2 AND-OR, the outputs of which are connected to the first inputs of the first and second modulo 2 adders, respectively. which ports are connected respectively to the first and second information inputs of the first and second memory blocks, the sixth output of the control unit is connected to the control input of the summation

Description

an arithmetic unit whose control input subtraction is connected to the output of the first element NOT, the input 6th is connected to the sixth output of the control unit, the seventh and eighth outputs of which are connected respectively to the second and third inputs of the third and fourth elements 2 OR, the fourth inputs of which are connected to the outputs of imaginary parts the first and second operands of the arithmetic unit respectively, the ninth and tenth outputs of the control unit are connected to the second inputs of the first and BTOpo.ro modulo 2 adders, one The fifteenth output of the control unit is connected to the control input of the first memory block and the input of the second element NOT, the output of which is connected to the control input of the second memory block, the twelfth and thirteenth outputs of the control unit are connected to the address setting inputs of the second and third address formers, outputs overflows of which are connected respectively to the first and second inputs of the control unit, fourteenp output of which is connected to the input of setting the address increment of the first and second address generator ca n fifteenth output control unit is output information issuing litter percent, and the third and fourth inputs of the control unit, are respectively the clock input and the input of receive processor synchronize.

2. The device of claim 1, wherein the control unit contains a stage counter, a stage decoder, an iteration counter, an iterator decoder, a synchronizer, four shift registers, the first and second switches, six flip-flops, thirty And elements, thirteen OR elements and six NOT elements,. the output of the first element is NOT connected to the first input of the first element I, the output of which is connected to the first input of the first element OR, the output of which is connected to the clock stroke of the stage counter, the output of which is connected to the input of the decoder of these stages, the first output of which is connected to the first input of the second element OR The output of which is connected to the input of the second element NOT and the first input of the second element I, the second input of which is combined with the first inputs of the third, fourth, fifth elements AND, the second input of the first element I and counting in the first trigger, the second output of the stage decoder is connected to the first input of the third element OR, the second input of the second element OR, the input of the first element NOT, the second input of the fifth element AND and the second input of the fourth element AND whose output is connected to the clock input of the iteration counter, the first the output of which is connected to the third input of the fifth element AND, the output of which is connected to the second input of the first element OR, the third output of the stage decoder is connected to the first input of the fourth element OR, the second input of the third ele OR and the third input of the second OR element, the fourth output of the stage decoder is connected to the second input of the fourth OR element and the third input of the third OR element, the first output of the first

switch connected to the first input of the fourth element And the synchronizer input, the output of which is connected to the first input of the sixth element AND, the first input of the fifth element OR, and

unit input of the second trigger, the output of which is connected to the first input of the seventh element And, the output of which is connected to the clock input of the first shift register, the output of which is connected to the second input of the fifth element OR, the first inputs of the eighth, ninth, tenth, eleventh, twelfth, the thirteenth,

the fourteenth and fifteenth elements And, the second output of the first commutator. torus is connected to the zero input of the second trigger and the input of the first shift register, the control input of which is connected to the output of the fifth OR element, the output of the synchronizer is connected to the first input of the sixth OR element, the output of which is connected to the input of the second shift register whose output is connected to the first input the seventh OR element, the second input of which is connected to the output of the sixth element And, the second input of which is combined with the first input of the sixteenth element And, the second input of the fourteenth element And, and is connected to the output of the decoder stages, the output of the third element OR is connected to the second inputs of the thirteenth element AND

and the eighth element And, the output of which is connected to the counting input of the third trigger, whose single output is connected to the first inputs of the seventeenth, eighteenth And elements, the second input of the ten, eleventh, fifteenth, sixteenth And elements, and the third input of the fourteenth element And, the second outputs and the third elements And are connected respectively with, single and zero inputs of the third trigger, the zero output of which is connected to the second input of the ninth element and the third input of the thirteenth element And, the output of which It is connected to the first input of the eighth OR element, the second input of which is the fourth input of the control unit, the second output of the stage decoder is connected to the second input of the eighteenth AND element and the third input of the ninth AND element, the output of which is connected to the first input of the ninth OR element, the second the input of which is connected to the output of the tenth element AND, the third input of which is connected to the second input of the seventeenth element AND, the first input of the first switch and is connected to the output of the fourth element OR, the fifth output of the decoder The tapes are connected to the second input of the twelfth element AND, the output of which is connected to the third input of the ninth element OR and is the fifteenth output of the control unit, the outputs of the seventeenth, eighteenth element AND of the ninth element OR are connected respectively to the first, second and third inputs of the second switch The first and second outputs of which are respectively the twelfth and thirteenth outputs of the control unit, the first output of the stage decoder is the third output of the control unit and is connected to the input of the third el NOT, the output of which is connected to the first input of the nineteenth element AND, the second input of which is connected to the output of the fourth element NO, whose input is connected to the output of the sixteenth element AND, the output of which is the second output of the control unit, and the output of the nineteenth element AND the first output of the control unit; the third output of the first switch is connected to the single input of the fourth trigger, the single output of which is connected to the third input of the fifteenth element I, the output of which is connected to the zero input of the fourth trigger and the second input of the sixth OR element, the third input of which is connected to the output of the fourteenth element AND, the control inputs of the synchronizer, the second shift register and the second input of the seventh element AND are connected and the third input of the control unit, the output of the eighth element OR is connected to the second input the first switch and the input of the third shift register, the output of which is connected to the first input of the tenth element of the IL and the single input of the fifth trigger, the unit output of which is connected to the first input d vadtsati element And, the output of which is connected to the clock input of the fourth shift register, the output of which is connected to the third input of the first switch and the first input of the twenty-first, twenty-second, twenty-third and twenty fourth fourth elements And, the first output of the first switch is connected to the zero input of the fifth trigger and controlling the input of the fourth shift register, the input of which is connected to the output of the tenth element OR, the second input of which is combined with the first inputs of the twenty-fifth, twenty-sixth, and twenty The seventh, twenty-eighth, twenty-nine elements AND, the second input of the twenty-third element AND, and is connected to the unit of the sixth trigger and represents the eighth output of the control unit, the zero output of the sixth trigger is connected to the first input of the thirtieth element And, matched the twenty-second element AND is the seventh output of the control unit, the output of the third element OR is connected to the second input of the twenty-fourth element AND, the output of which is connected to the counting input of the sixth trigger, single and zero inputs The outputs of the second and third elements And, the second output of the stage decoder are connected to the second inputs of the twenty fifth, thirtieth and twenty sixth elements And, the first output of the iterator decoder is connected to the third input of the twenty fifth and thirtieth elements And, p the element NO, the output of which is connected to the third input of the twenty-sixth element AND, the output of which is connected to the first input of the eleventh element OR, the second input of which is combined with the first input of the twelfth element IL And and connected to the output of the twenty fifth element And, the output of the thirtieth element And, connected to the second input of the twelfth element OR, the output of the fourth element OR connected to the second input of the twenty-seventh element And, the third input of the twenty third element And the sixth element NOT, output which is connected to the third input of the twenty-second element And, the output of which is connected to the first input of the thirteen element OR, the second input of which is connected to the output of the twenty-third element And, the third output of the decoder iterations in The sixth output of the control unit and connected to the second input of the twenty-eighth element AND, the output of which is the ninth output of the control unit, the fourth output of the stage decoder is connected to the second input of the twenty-ninth element And, the output of which is the tenth output of the control unit, outputs eleventh, twelfth

and the thirteenth elements OR and the output of the twenty-seventh element AND are connected respectively to the fourth, fifth, sixth and seventh input of the second switch, the second output of the twentieth element AND and the clock input of the third shift register are combined and form the third input of the control unit, first, second, third and the fourth outputs of the iteration decoder are the fourteenth output of the control unit, the output of the first flip-flop is connected to the fourth input of the first switch and the eighth input of the second switch and is the eleventh output the house of the control unit, the first output of the stage decoder is the third output, the home of the scanner unit, the output of the fourth and seventh OR elements; the output of the control unit The fifth and sixth inputs of the first switch are respectively the first and second inputs of the control unit.

The invention relates to the field of computing and can be used for solving problems of digital signal processing.

A device for calculating Fourier coefficients is known, in which the speed is increased by combining computations. The device contains multiplication blocks, summing blocks, registers of the real and imaginary parts of the weight coefficient C11.

Despite the use of four multipliers and the simultaneous execution of multiplication, addition, and subtraction operations, the device has a relatively low speed since the results of the calculations are recorded in the same registers where the source data is recorded. Therefore, the computing device cannot start processing the following operands until 4

previously calculated results will not be rewritten into RAM.

The closest technical solution to the invention is a device for calculating Fourier coefficients comprising multiplication blocks, summing blocks, registers of the real and imaginary parts of the input operands, registers of the real and imaginary parts of the weighting factor, registers of the real and imaginary parts of the output operands, as well as intermediate registers, providing an increase in the speed of computations by combining the operation of multiplication blocks and summing blocks C2.

The disadvantages of this device include a relatively small speed when calculating the Fourier coefficients from the actual sequence of input data; in addition, the organization of computations of the Fourier coefficients from a real sequence in it is realizable and requires significant amounts of operative memory. The purpose of the invention is to increase the speed and simplify the device. The goal is achieved by the fact that in the processor containing the arithmetic unit, the first and second memory blocks, the permanent memory block, the control block, three address generators, two AND elements and two OR elements, the outputs of the first and second AND elements are connected to the first the inputs of the first and second OR elements, respectively, whose outputs are connected respectively to the first and second inputs of the operands of the arithmetic unit, the inputs of the real and imaginary parts of the coefficients of which are connected respectively to the first and second The outputs of the fixed memory block whose input is connected to the output of the first address driver, the outputs of the second and third address drivers are connected to the address inputs of the first one, and; the second memory blocks, the first and second outputs of which are respectively combined and the first and the second information outputs of the processor, and the first ones entered the first and second elements And are respectively the first and second information inputs of the processor, containing the first, second, third and fourth elements s 2 AND-OR, the first and second adders modulo 2, the first and second elements are NOT, the first output of the control unit connected to the first inputs of the first and second elements 2 AND-OR, the outputs of which are connected to the second inputs of the first and second elements OR The second output of the control unit is connected to the second inputs of the first and second elements 2 of I-ШШ, the third and fourth inputs of which are connected respectively to the first and second outputs of the first memory block, the third output of the control unit is connected to the second inputs of the first and second And, the fourth output of the control unit is connected to the input of the first address generator, the five output of the control unit is connected to the control input of receiving information of the arithmetic unit, the outputs of the real part of the first and third operands of which are connected to the first inputs of the third and fourth elements 2, respectively. OR, the outputs of which are connected to the first inputs of the corresponding. first and second modulo-2 adders, the outputs of which are connected to the first and second information inputs of the first and second memory blocks, respectively, the sixth output of the control unit is connected to the control input of the summation of the arithmetic unit whose subtraction control input is connected to the output of the first element HE, the input which is connected to the sixth output of the control unit, the seventh and eighth outputs of which are connected respectively to the second and third inputs of the third and fourth elements 2 AND-OR, the fourth inputs which are connected to the outputs of imaginary parts of the first and second operands of the arithmetic unit, respectively; the ninth and tenth outputs of the control unit are connected to the second inputs of the first and second modulo 2 adders, respectively; the eleventh output of the control unit is connected to the control input the second element NOT, the output of which is connected to the control input of the second memory block, the twelfth and thirteenth outputs of the control unit are connected to the inputs for setting the address of the second and third, respectively its address drivers, the overflow outputs of which are connected respectively to the first and second inputs of the control unit, the fourteenth output of which is connected to the input of the address increment jobs of the first and second address drivers, the fifteen output of the control unit is the output of the processor output information, and the third and fourth inputs of the block the controls are a clock input and a clock reception input of the processor, respectively. The control unit contains a stage counter, stage decoder, iteration counter, iterator decoder, synchronizer, four shift registers, first and second switches, six triggers, thirty AND elements, thirteen OR elements and six NOT elements, and the output of the first element is NOT connected to the first input the first element And, the output of which is connected to the first input of the first element OR, the output of which is connected to the clock input of the stage counter, the output of which is connected to the input of the stage decoder, the first output of which n to the first input of the second element OR, the output of which is connected to the input of the second element NOT and the first and the input of the second element AND the second input of which is combined with the first inputs of the third, fourth, fifth And elements, the second input of the first element AND and the counting input of the first trigger, the second output of the stage decoder is connected to the first input of the third element OR, the second input of the second element SHI, the input of the first element NOT, the second input of the fifth element AND and the second input of the fourth element AND whose output is connected to the clock input m iteration counter, the output of which is connected to the third input of the fifth element AND, the output of which is connected to the second input of the first OR element, the third output of the stage decoder is connected to the first input of the fourth OR element, the third input of the third OR element, and the third input of the ROR element OR, the fourth output of the stage decoder is connected to the second input of the fourth OR element and the third input of the third OR element, the first output of the first switch is connected to the first input of the fourth AND element and the synchronizer input, output which is connected to the first 1m input of the sixth element AND the first input of the fifth OR element and the single input of the second trigger, whose output is connected to the first input of the seventh AND element, the output of which is connected to the clock input of the first shift register, the output of which is connected to the second input of the fifth of the RShI element, the first inputs of the eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth and fifteenth elements. The second output of the first switch is connected to the zero input of the second trigger and the input The first shift register, the control input of which is connected to the output of the first OR element, the synchronizer output is connected to the first input of the sixth OR element, the output of which is connected to the input of the second shift register, the output of which is connected to the first input of the seventh OR element, the second input of which is connected to way out

the sixth element And the second input of which is combined with the first input of the sixteenth element And, the second input of the fourteenth element And and connected to the fourth output of the decoder stages, the output of the third element OR connected to the second inputs of the thirteenth element And the eighth element And, the output of which is connected to the counting input the third trigger, a single output of which is connected to the first inputs of the seventeenth, eighteenth elements AND, the second input of the tenth, eleventh, fifteenth, sixteenth elements AND and the third input h And the outputs of the second and third elements And are connected respectively to the single and zero inputs of the third trigger, the zero output of which is connected to the second input of the ninth element And, and to the third input of the thirteenth element And, the output of which is connected to the first input of the eighth element OR, the second the input of which is the fourth input of the control unit, the second output of the stage decoder is connected to the second input of the eighteenth element AND and the third input of the ninth element AND, the output of which is connected to the first one nine OR element, the second input of which is connected to the output of the tenth element AND, the third input of which is combined with the second input of the seventeenth element AND, the first input of the first switch and connected to the output of the fourth element I1Sh, the fifth stage of the stage decoder is connected to the second input of the twelfth element AND, the output of which is connected to the third input of the ninth OR element and is the fifteenth output of the control unit, the outputs of the seventeenth, eighteenth AND elements and the ninth NIII element are connected respectively to the first m, the second and third inputs of the second switch, the first and second outputs of which are the twelfth and thirteenth outputs of the control unit, respectively; the first output of the stage decoder is the third output of the control unit and connected to the input of the third HE element, the output of which is connected to the first input of the nineteenth element And, the second input of which is connected to the output of the fourth element And, the second input of which is connected to the output of the fourth element NOT, the input of which is connected to the output of the sixteenth element And, the output to The first is the second output of the control unit, and the output of the nineteenth element I is the first output of the control unit, the third output of the first switch is connected to the single input of the fourth flip-flop, whose single output is connected to the third input of the fifteenth element And whose output is connected to the zero input the fourth trigger and the second input of the sixth OR element, the third input of which is connected to the output of the fourteenth element AND, the control inputs of the synchronizer, the second shift register and the second input of the seventh element AND are combined and are the third input of the control unit, the output of the eighth element OR is connected to the second input of the first switch and the input of the third shift register, the output of which is connected to the first input of the tenth OR element and the single input of the fifth trigger, the single output of which is connected to the first input of the twentieth element And, the output of which is connected to the clock input of the fourth shift register, the output of which is connected to the third input of the first switch and the first input of the twenty-first, twenty second o, the twenty-third and twenty-fourth elements And, the first output of the first switch is connected to the zero input of the fifth trigger and the control input of the fourth shift register, the input of which is connected to the output of the tenth OR element, the second input of which is connected to the first BJto twenty the twenty-sixth, twenty-seventh, twenty-eighth, twenty-nine elements AND, the second input of the twenty-third element AND, and is connected to the unit output of the sixth trigger and forms the eighth output of the control unit, zero

The sixth trigger is connected to the first input of the thirtieth element AND, the second input of the twenty-second element And is the seventh output of the control unit, the output of the third element OR is connected to the second input of the twenty-fourth element AND, the output of which is connected to the counting input of the sixth trigger, the zero inputs of which are connected to the outputs of the second and third elements And, respectively, the second output of the decoder stages connected with 10

These iterations are the fourteenth output of the control unit, the output of the first trigger is connected to the fourth.  the input of the first switch and the eighth input of the second switch and is the eleventh output of the control unit; the first output of the stage decoder is the third output of the control unit; the outputs of the fourth and seventh OR elements are the fourth output of the control unit; the output of the eleventh And output, the second and third outputs 388 MI inputs of the twenty-fifth, thirtieth and twenty-sixth elements And, the first output of the decoder iterations connected to the third input of the twenty-fifth and thirtieth elements And and the input The fifth element is NOT, the output of which is connected to the third input of the twenty-sixth element, the output of which is connected to the first input of the eleventh element OR, the second input of which is combined with the first input of the twelfth element OR, and the output of the thirtieth element And connected with the second input of the twelfth element OR, the output of the fourth element OR is connected to the second input of the twenty-seventh element AND, the third input of the twenty-third element AND and the input of the sixth element NOT, the output of which is Connected to the third input of the twenty-second element AND, the output of which is connected to the first input of the thirteenth element OR, the second input of which is connected to the output of the twenty-third element AND, the third output of the iterator decoder is six & 1 output of the control unit and connected to the second input of the twenty-eighth element And, the output of which is the ninth output of the control unit, the fourth output of the stage decoder is connected to the second input of the twenty-ninth AND element, the height of which is the tenth output of the control unit, the outputs the eleventh, twelfth and thirteenth elements OR and the output of the twenty-seventh element And are connected respectively to the fourth, fifth, sixth and seventh input of the second switch, the second output of the twentieth element AND and the clock input of the third shift register are combined and the third input of the control unit, the first, second.  the third and fourth outputs of the decoders and the output of the EIGHT element OR form the fifth output of the control unit, and the fifth and sixth inputs of the first switch are the first and second inputs of the control unit, respectively.  Fig, 1 shows the processor circuit; FIGS. 2 to 10 respectively, an arithmetic unit, a constant memory address generator, an address (memory controller) driver, a control unit, a stage unit, a read control node, a control and record node, input and output switches.  The Fast Fourier Transform Processor contains an arithmetic block (2,3) of memory blocks 2,3, block. fixed memory 4, address driver (fixed memory) 5, address drivers (random access memory) 6, 7, control unit 8, four elements 2 AND-OR 9-12, two elements 13 and 14, two elements OR 15 and 16, two adders modulo 2 17 and 18, elements NOT 19 and 20, informational codes 21, 22, clock input 23.  the input synchronization input numbers 24, the information outputs of the processor 25, 26, the output synchronization issue of the numbers 27, the outputs 28-41 of block 8, the output 42 of the element HE 19, the outputs 43-44 of drivers 6 and 7, respectively.  FIG.  2 shows a functional diagram of the arithmetic unit 1, which corresponds to the computing device of the prototype and contains the registers 45 of the real and 46 imaginary parts of the first number of the pair of processing complex numbers, registers 47 and 48 of the real and imaginary parts of the complex weighting factor, matrix multipliers 49-52, adders 53 , 54, registers 55 of the real and 56 imaginary parts of the second number of a pair of processed complex numbers, adders 57-60, registers 61, 62 of the storage of the real part of the first and second complex real as a result of the calculations, and the storage registers 63 64 of the imaginary part, respectively, of the first and second complex results of the calculations.  FIG. .  Fig. 3 shows the functional diagram of the address memory generator 5, which contains the address counter 65, our bits 10 10, the element NOT 66, the group of elements 2, OR 67t-67.  FIG.  4 is a functional diagram of an address mapper (RAM) 6 (7), which contains A, an address register for m bits, consisting of flip-flops 68, an AND element at (in-1) input 69, an OR element at (t-1 ) input 70, two-input elements And 71, 72, two-input elements OR 73 - 73, elements NOT 74 - 74, two-input element And 75, two groups of three-input elements And 76 - 76,, And 77 -77, two-input elements OR 78, 79 . . , - 79j, adders modulo 2 80 - 80, multiplexers 8 C - 81 for increasing the address code.  FIG.  5 shows a structural control circuit 8, which comprises a node of steps 82, the opening of FIG.  6, read control node 83 disclosed in FIG.  7, recording control node 84, disclosed in FIG.  8, the input switch 85 disclosed in FIG.  9, and the output switch 86 disclosed in FIG.  ten.  FIG.  6 shows a functional diagram of the node of steps 82.  The location of the entrance and exits of the node corresponds to their location in FIG.  five.  The node contains a stage counter 87, a stage decoder for five outputs 88, an iteration counter 89, a decoder for iterations per m outputs 90, a trigger 91, elements HE 92 and 93, elements AND 94 97 (three-input) element AND 98, (two-input) elements OR 99 and 100 and (three-input) elements OR 101 and 102.  FIG.  7 is a functional diagram of the read control node 83.  The location of the inputs and outputs of the node corresponds to their location in FIG.  five.  The node contains a synchronizer 103, triggers 104 - 106, shift registers (4 bits) 107 and 108, acting as delay elements, (two-input) elements AND 109-117, (two-input) elements OR 118 - 120, (three-input) elements And 121 - 125, (three-input) elements OR 126 and 127 and elements NOT 128 and 129.  FIG.  8 is a functional diagram of the control node 84.  The location of the inputs and outputs of the node corresponds to their location in FIG.  5, the Node contains shift registers 130 and 131 (by 4 bits), which act as delay elements triggers 132 and 133, (two-input) elements AND 134 - 139, (two-input) elements OR 140-143, elements NOT 14 and 145 , (three-way) elements And 146 150.  FIG.  9 is a functional diagram of an input switch that contains elements 2 ORI 151-155, (three-input) elements AND 156 and 157, (two-input) elements OR 158 and 159, and element HE 160 The location of the outputs corresponds to their location in FIG.  five.  FIG.  10 is a functional diagram of the output switch 86, which contains (two-input elements AND 161 and 162, elements 2ILI 163-168 and element NOT 169.  The arrangement of the inputs of the switch 86 corresponds to their location in FIG.  five.  In order to explain the operation of the processor, we consider the implementation of the Fast Fourier Transform (FFT) algorithm in it.  The input sequence is S:, where, 1, 2,. . . , N-1 is converted to a complex sequence. {(j) j, where, 1, 2 ,. . . , N / 2-1, by representing each pair of neighboring samples as a complex number, with even numbers (5, 57 54i considered real, and odd (5, 5,, Sg.  , . .  , Sj) are the imaginary parts of the complex numbers.  The calculation of the Fourier coefficients of the transformed sequence consists in the calculation of intermediate coefficients using the basic formulas of the FFT algorithm: Ai (j) A ,.  (j) + A (K) wi; i, (O A {(K) A. (J) -A. . (K) W (2) where is the current iteration number,. , 2, 3 ,. . .  m , Wf is the value of the complex weight coefficient.  The value of n is equal to the binary inversion of the code for the number of the computation zone in the iteration.  So, for binary code “- ,, 012, Ld. .  . , ". , O binary-inverse code will be, and. . . , c, 3, the zone number is represented by the m-digit: binary code.  The zone numbers on the iterations will be: for the first iteration; , 1 for the second iteration; 108 12 i 0,1,2,3 for the third iteration; 0,1,2,3 ,.  . . , N / 4-1 for the last iteration.  Since the transformed sequence was two times shorter than the original one, the number of iterations for the calculation will be one less, and the capacity of the RAM will be halved.  Accordingly, the computation time at each iteration is halved.  After calculating the intermediate coefficients, a calculation is performed. Fourier coefficients by the formulas: A tA. . ,, A, -A where t to 1, 2,. . . , (); A and - intermediate coefficients calculated by formulas (1) and (2).  The calculation using formulas (3) is performed in two steps.  The first is the evaluation of the expressions. . . . .  After calculating expressions (5), the second stage is performed, which consists in calculating the Fourier coefficients by formulas (3) and (4), the hardware implementation of which is the same as the basic formulas (1) and (2).  The difference lies in the formation of the addresses of the weights w and the operands.  It should be noted that calculations using formulas (1) - (4) allow only the N / 2 Fourier coefficients to be determined. However, for spectral analysis this is quite sufficient, since the second half of the spectrum is symmetric with respect to the first.  The time for calculating the coefficients according to formulas (3) and (4) is equal to the time for calculating according to the basic formulas (1) and (2) at any two iterations.  The processor works in the following way.  Before calculating the Fourier coefficients, the sequence of input samples S is entered into the RAM 3; I.  Each pair of adjacent samples is fed to the information inputs of the processor 21 and 22 at the same time, accompanied by a synchronization signal for receiving the number on the input 24.  Even counts (Sjj, $ 21. . .  iS (sj-2 arrive at the information inputs of the register 55 of the arithmetic unit 1 through the first inputs of the elements And 13 and the elements OR 15, and odd (5, 5, -5uJ to the information inputs of the register 56 of the arithmetic unit 1 through the first inputs of the elements And 14 and elements OR 16.  At the time of the sort, the counter of steps 87 (FIG.  6) the control unit 8 is in the zero state, while from the first output of the decoder of steps 88 of the control unit 8 to the second inputs of the groups of elements 13 and 14, the output potential is fed through the bus (output) 30.  The synchronization signal for receiving numbers through the first input of the element OR 120 (FIG. 7) of the control unit 8 is transmitted to the serial input of the shift register 130 (FIG.  8) control unit 8 and the inputs for writing registers 55 and 56 nj to input 32-3 (FIG.  2).  The clock pulses at input 23 are fed to the shift input of register 130 and provide a consistent advance of the synchronization signal over its discharge.  The signal from the output of the shift register 130 writes to the registers 61-64 of the arithmetic unit 1 of the second counts, which are sent to their information inputs from the outputs of the registers 55 and 56 through the adders 57-60 of the arithmetic unit 1, to the second inputs of which comes zero information given when setting the initial state of the processor.  At the same time, the same signal is set to the trigger state 132 and, via the OR 140 element, is fed to the serial input of the shift register 131 (FIG.  8) control unit 8.  The shift registers 130 and 131 serve as delay circuits.  Shift register 130 provides a delay for the write signal to registers 6164 relative to the write signal to registers 56 and 55 for the duration of the calculation in adders 57-60.  The shift register 131 provides for a delay in changing the address code and information at the inputs of the RAM blocks during their write cycle.  The trigger 133 (FIG.  8) during input the control unit is in the zero state and the resolving potential from its zero arm at input 34 enters the second inputs of elements 2 AND-OR 12 and 11, thereby the outputs of registers 61 and 63.  The change of the signs of the input samples on elements 17 and 18 is not performed, since zero potentials from the outputs of elements And 138 and 139 arrive at their second inputs (Fig.  6) control unit 8.  Trigger 91 (FIG.  6) control unit 8 is in the zero state.  The zero potential from the single output of this trigger via input 38 is fed to the third inputs (write and read control inputs) of the first and through the NOT element 20 of the second RAM blocks 2 and 3.  The high level at the third input of the RAM block sets the write mode, and the low level sets the read mode.  Therefore, the input samples are recorded in the RAM 3.  In addition, the zero potential of the trigger 91 is supplied to the elements of the output switch 86 (FIG.  10) control unit 8 and provides for connection of outputs of elements SHSh 141-143 and element 137 137 (FIG.  8) control unit 8 via busses 40 to the inputs of the address maker and the RAM 7 (FIG.  four).  During the input of the entire sequence of input samples at the outputs of elements SHSh 141-143 there is a low potential.  Low potentials from the outputs of the elements OR 141-143, respectively, flow through the elements AND 162, 2 AND-OR 166 and 167 of the output switch 86 (FIG.  10) on the control, the inputs of the multiplexers 81 - 81j and the second inputs of the elements of the adders modulo 2 80- - 80 through the inputs 40-4, 40-3 and 40-2, thereby ensuring the transfer of the address register code 68 - 68 through the multiplexers 81 - 81 (FIG.  4) to the (address) input of the RAM block 3.  During the input, iterations 89 in the counter (FIG.  6) the control unit 8 has a zero code, while all outputs of the decoder 90 have a low potential.  The low potentials from the outputs of the decoder 90 to the outputs 41 are fed to the inputs of the elements of the memory driver 6 and 7, and in the increment code generator of the address code a natural counting mode is set.  At the first input of the element are And 135, at the second input of the element And 136, at the first and third outputs of the element And 149 are low potentials, and at the first and third inputs of the element 150 And there are high potentials (Fig.  8), therefore, signals from the output of the shift register 131 are passed only to the output of the And 150 element (Fig.  eight).  From the output of the element AND 150 through the element OR 143, these signals as counting signals are received through the first input of element 2 AND-OR 168 (at the second input of this element high potential) of the output switch 86 (FIG.  10) bus 40-1 to the first inputs of the elements And 71, and 72 (counting input) of the address memory generator 7 (FIG.  41).  With the arrival of each counting signal, the contents of the address register 68; - 68 is increased by one unit. -,, I. The counting signal with the number N / 2 during writing to the RAM 7 of the sample pair with the number M / D of the passage through the chain of elements 71, 73 - 73. , switches the triggers 68 - 68 of the address register from one to the zero state and through the first inputs of the element AND 75, the second input of the element OR 78 as a signal; overflow on the third exit 44 (FIG.  4) arriving at the third input of element 2 AND-OR 153 and the first input of element 2 AND-OR 155 (FIG.  9).  This completes the input of the array of input samples.  In each cell of the RAM unit, two adjacent readings are recorded.  The second stage of the processor is to calculate the intermediate Fourier coefficients using the formulas (1) and (2).  At all but the last iterations, the write addresses of the computed operands A- (j) and A; j (1) are the same as the read addresses of the input operands Aj (j) and A- (k).  Denote the addresses for the operands A-. (j) and A,. (k via XI and X2, addresses of operands A (j) and A; (k) on all iterations, except the last one, via Y1 and Y2, and for the last iteration - Y1 and Y2.  . The addresses XI and U1 are formed on the address register by the increment shaper of address formers 6 and 7 in the natural order of counting with the prohibition of setting the address register triggers in the unit state, the numbers of which coincide with the posterior number of the iteration being performed, and the first number has the highest trigger 68p address register (FIG.  four).  Specifically, the first iteration prohibits the installation of trigger unit 68, on, the second iteration of trigger 68, and so on. d.  The formation of addresses X2 and Y2 is carried out by logical summation on the elements OR 79–79 of the register code for addresses 68 and –68 with the positional number of the iteration being performed.  The formation of addresses U1 and U2 is performed by binary inversion of addresses U1 and U2 through the second and fourth inputs of multiplexers 81 - 81 |.  Recording the results of the calculations at addresses U1 and U2 provides a natural order of their location in the RAM 6 or 7.    The values of the complex weighting coefficients.  2G (i pfitsy J (and stored in the cells of the constant memory block sequentially, and n unambiguously corresponds to the cell number) The reading of the weighting codes in the arithmetic unit 1 is performed at the beginning of each iteration and by the signal of the end of the zone, coming from the output of the AND 70 (FIG.  4) at the second exit 43 D. G1Y block 6 and the second input 44 for block 7.  Addresses for reading weight coefficients are generated by binary inversion on address code 65, elements 67 - 67 of the counter code 65.  Consider the work of the processor to calculate the intermediate coefficients by the formulas (1) and- (2) for example, processing the first pair of operands of the first iteration.  The signal is filled at the end of the input from the output of the element OR 78 of block 7 (FIG.  4) at the third output 44 through the first input of element 2 AND-OR 155 (high potential at the second input), through the second input of element OR 159 (firm.  9) the input switch, as a signal of the write end of the array, is fed to the input of the read control node 83 and to the third input of the write control node 84.  In the control unit 8, the signal of the end of the array recording produces the following: through the second input of the element AND 94 (at the first input high potential) and the second input of the element OR 99 adds one to.  a step counter 87, thereby providing a high level at the second output of the descrambler of steps 88 (FIG.  6) and low on all other outlets; switching trigger 91 (FIG.  6) from zero to one state, thereby setting the RAM block 2 to the write mode, and the RAM block 3 to the read mode; through the first input of the element 96 (at the second output a high potential) sets in one state the trigger 106 (Fig.  7) read control node 83 and trigger 133 (FIG.  8) recording control unit 84; via synchronizer 103 (FIG.  7) establishes the trigger 104 in one state and, through the elements OR 118 and 126, the first bits: shift registers 107 and 108; confirms the zero state of the trigger 132V of the register 131 (FIG.  8) recording control unit 94.  A high potential from a single trigger trigger 91 (FIG.  6) at the twelfth output of the node of the stages is fed to the input element HE 169, to the second inputs of the elements AND 161 and. 162 and the fourth entrances of elements 2 of the I-STI 163 168 (FIG.  10), thereby ensuring the transmission of signals from the read control node 83 via the outputs 40 to the address driver 7 and the transmission of signals from the write control node 84 to the outputs 39 to the address driver 6.  The high level at the second output of the decoder of steps 88 and the single state of the trigger 106 ensures the formation of a high potential at the output of the element. And 116 and low - at the output of the element And 117 (FIG.  7) reading control unit 83, with ETL at the outputs of the AND 162 and 2 IHSH 167 elements, low potential, and at the output of the 2 AND-OR 166 element - high potential (Fig.  10) output switch 86.  These potentials, arriving at the outputs 40-3, 40-2, 40-4 in the address driver 7, provide for the formation and loading of the address X2 into the memory unit 3, while at 10,818 outputs it sets the value of the operand A- ( ).  Similarly, the high level at the second output of the decoder of steps 88 n is the single state of the trigger 133 (Fig.  8) the recording control unit 84 provides in the address maker 6 the formation and output from it to the operational memory 2 of the address U2.  The addresses X2 and Y2 are formed on the OR elements 79 -, - 79, whereupon the control inputs A and B are, respectively, the unit and zero potentials and the outputs of the second inputs (inputs 1) are transferred to the outputs of the multiplexers.  At the output of the element 113, the high potential is maintained during the implementation of the second stage.  Progress on exit 28 (FIG.  1) to the second input of elements 2 of I-ШШ 9 and 10, this potential allows the direct transfer of operands from blocks of RAM 3 or 2 to the arithmetic unit 1, t. e.  The imaginary part of the operand arrives at the first input, and is valid at the second input of the arithmetic unit 1.  A high level of a single arm of the trigger 104 (FIG.  7) it permits the passage of 109 clock pulses to the shift input of register 107, which produces a consecutive advancement of the unit by perticTpa.  The output signal (high bit) of the shift register 107 at a single state of the trigger 106 produces the following: through the first input of the element 115 and the output enters the second inputs of the registers 45 and 46 of the arithmetic unit 1 and writes to them, respectively, the real and imaginary parts of the operand BUT. (to); through the first input of the element OR 118 sets to one the first bit of the shift register.  107; through the first input element And 110 switches the trigger 106 (Fig.  7).  Clock pulses arrive at the shift: the input of the register 108 (Fig, 7), produced by the advancement of the unit on the bit of the register.  The signal from the output of the shift register 108 produces the following: output 32-2 goes to the second inputs of registers 47 and 48 of the arithmetic unit 1, recording in them, respectively, the real and imaginary part of the complex weighting factor.  In the zero state of the trigger 106 (FIG. 7), the output potentials of the And 116 and 117 elements are low potentials, which through the first inputs of the I-IZH 16 and 167 elements 2 through the outputs 40-4 and 40-2 enter the address shaper 7 and together with low. The potential from the output of the AND 162 element, arriving at the output 40-3, also in the address driver 7, ensures that the address code XI is inserted into the operational memory 3, while the information output of this block is set to the value of the operand A. , -. (/), which is similar to the operand Аj (к) goes to the first and second inputs of apH (J of the logical unit 1.  In the zero state of the trigger 106 (FIG.  7) the signal from the output of the shift register 107 produces the following: through the third input of the element And 121 and watts. The element input element OR 120 sets to the first digit of the register 130 (FIG.  8) and output 32-3 goes to the second (control) inputs of registers 55 and 56, writing them to the real and imaginary parts of operand A (j), respectively; through the third input of the element AND 124, the second input of the element OR 127 of the control unit with coupling 83 (Fig.  7) and the third input of the element 2 AND-OR 168 of the output switch 86 (FIG.  10) on the output 40-1 enters the first inputs of the elements And 71 and 72 (counting input) of the address driver 7, increasing the contents of the address register 68 -) - 68, ".  During all processing steps, adders 53 and 57 perform the operation of adding input operands, adders 54 and 58 perform a subtraction, and the operands received at the second inputs of these adders are subtracted.  Low potential from the third-party decoder of steps 88 (FIG.  6) the output 33 is fed to the control input of the adder 59 (FIG.  2) and through the element NOT 19 on exit 42 (FIG.  1) to control the input of the adder 60, thereby ensuring the operation of the layer. marriage on summa-; re 59 and the subtraction operation on the adder 60.  The information inputs of registers 61 and 63 are real and imaginary parts of the result A, - (j), and the information inputs of registers 62 and 64 are received respectively real and imaginary parts of the result (k).  The signal from the output of the shift register 130 (FIG.  8), delayed in relation to the input signal by the delay time of adders 57-60, produces the following trace: output 32-4 records the results of A. (j) and A- (k) to registers 61-64 of arithmetic unit 1; sets the first bit of the shift register 131 through the second input of the element OR 140 (FIG. 8) to a single state; establishes the trigger state 132 in one state, allowing the passage of clock pulses through AND 134 to the shift input of register 131.  The unit state of the trigger 133 (FIG.  8) connects the outputs of registers 62 and 64 to the info1 operational inputs of the RAM 2 and 3, while the address generator U2 comes from the address generator 6 to the RAM 2.  By the time the signal appears at the output of the register 131 in the RAM 2, the result A (k) is recorded.  The signal from the output of the register 131 produces the following: through the second input of the input I 136 (the first input of this element allows the potential formed by assembling the second, third and fourth outputs of the decoder of steps 88 through OR, FIG.  6, on the OR element 101), the trigger 133 switches to the zero state (FIG.  8), while at the output of the address driver 6 an address U1 is formed; through the second input of the element AND 135 and the first input of the element OR 140 records the unit in the first register bit 131.  In the zero state of the trigger 133, registers 61 and 62 are connected to the memory blocks 2 and 3.  By the time the signal at the output of the register 131 appears in the memory unit 2, the result A (j) is written to the address U1.  In the zero state of the trigger 133, the signal from the output of the register 131 through the second input of the element is And 150, the second input of the element OR 143, the third input of the element 2 I-IPI 165 of the output switch 86 (Fig.  10) the output 39-1 enters the counting input of the address generator 6 and increases the code of the address register 68 - 68.  211 The processing mechanism of subsequent pairs of operands is similar to the processing of the first pair of operands.  All operands in the first iteration are processed with the same weighting factor.  After reading the entire array of operands from the operational block, memory 2 at the output of the element And the address resolver 7, an overflow signal is generated, which through the first input of the element OR 78 (Fig.  4), the third input of the element 2 is AND-OR 153 and the second input of the element OR 158 (FIG.  9, the input switch 85, as a signal to read the end of the array, sets the trigger 104 and the register 107 to the zero state (FIG.  7), thereby stopping the process of reading the array of operands.  After recording all pairs of results, an overflow signal is generated at the output of the AND 77 element address body 6, which through the first input of the OR element 78 (FIG.  4), a third of the input element 2 AND-OR 155, the second input element OR 159 (Fig.  9), as a signal to write the end of the array, enters, the read control node 83, the write control node 84 and the node of steps 82 and perform the same actions as after the end of the input of the data array, except for the node of steps 82.  In the latter, the unit is added to the iteration counter 89 via the element AND 95, thereby setting the second iteration (high potential at the second output) at the output of the decoder for iterations 9.  The trigger 91 is switched on each signal at the end of the array recording, thereby changing the operation mode of the RAM blocks 2 and 3.  Starting from the second iteration, the reading of the complex weights is performed not only at the beginning of the iteration, but also after the arrival of each signal at the end of the zone produced by the OR 70 element of the address generator included in the read mode.  When performing the last iteration with a single state, three heras 133 at the outputs of the elements OR 14 and 142 (Fig.  8) the write control unit generates high potentials that provide address generator (6 or 7), which is in write mode, and form address Y2 8 through the fourth inputs of multiplexers 81 - 81 (Fig.  four).  In the zero state of the trigger 133, at the output of the element OR 141, a high potential is maintained, and at the output of the element OR 142, a low potential is established.  Under the influence of these potentials in the address maker (6 or 7), which is in recording mode, the second inputs of the multiplexers 81 81 form and are output, the addresses U1 through the second inputs of the multiplexers 8C are 81 addresses Y.  At the last iteration, adding a unit to the counter of steps 87 at the last iteration is done by signaling the end of the array recording through the first input of the element E 98 (the second and third inputs have high potentials and the second input of the IL 99 element (FIG.  6), while at the third output of the decoder of steps 88 a high potential is established.  In the third and fourth stages of the processor, the Fourier coefficients are calculated using the formulas (3) and (4) from the results obtained in the second stage.  Consider the work of the processor, calculating a pair of Fourier coefficients.  Let, and c + d ,. .  (6), (7) V%, g. / q-c.  .   . .  V j g In the third stage, the operands L, 2, 6 ,, are computed and on the adders 57-60 of the arithmetic unit 1 and the partial multiplication 6 + by the factor (-1), which consists in changing the sign of the operand 6 on the adder group modulo 2 17 with high potential at their second entrances.  The swapping of operands 6 and is performed on. elements 2 AND-OR 9 and 10 (FIG.  1) when performing the fourth stage.  To calculate the operands I and 6 from the third output of the decoder of steps 88, the output 33 leads to a high potential at the control input of the adder 59 and through the element NOT 19 for control of the input of the adder 60 of the arithmetic unit 1.  .  The organization of reading operands A and the registers 55, 56 and 45, 46 is the same as for operand Aj (j), A (k) when performing the second stage.  To ensure the supply of the real part from register 45 to the second inputs of adders 57, 58 and the imaginary part d from register 46 to the second inputs of adders 59, 60 to registers 47 and 48 at the beginning of the stage read the zero address from the fixed memory block cobalt weighting, WHICH the real part is equal to one, and imaginary zero.  As a result of reading in register 47, all bits are set to one, and in register 48, the zero state throughout the entire execution step. The address to read operand A is the direct code, and operand A 2 is the return code of address register 68 | -68fr, address resolver (6 or 7) included in read mode.  The addresses for recording the results are the same as the read addresses of the input operands, and the D + 1D record is written with the direct address code, with the return code of the address generator of the addresses included in the write mode.  The return code of the address is generated at a high potential / le pa second inputs of adders modulo 2 80 ;, - Spj, a high potential is formed on: And 117 element with a single state of readout control node trigger 106 83 (FIG.  7) and at the output of the element 137 at the single state of the trigger 133 of the control unit recording 84 (Fig.  eight).  Addresses for reading and writing operands are transmitted to blocks of operative memory 2 and 3 via the first inputs of multiplexers 81 - 81 ' (FIG.  4) by supplying low potentials to the control inputs A and B from the outputs of the elements AND 161, 2 AND-RSHI 163 for block 6, AND 162, 2 AND-OR 166 (Fig.  10) for block 7.  Adding a unit to with S kept register 68 - 68,. The address bar (6 or 7) included in the gateway mode is made through the first input of the AND 125 element and the third input of the OR element 127 (FIG.  7 Adding a unit to the content of the 10 1024 gist of the address address 68 - 68 of the address maker (6 or 7) included in the recording mode is done through the second input of the AND 149 element and the first input of the OR 143 element (Fig.  eight).  The end-of-count signals and array records in the third and fourth stages are formed with a single state of the flip-flops 68 - 68j, with. This output element And 69 (FIG.  4) a high potential is established.  For definiteness, let the trigger 91 be in a single state.  Then a high potential from a single output of this trigger goes to the input of the element NOT 160 and to the fourth inputs of the elements 2 AND-OR 151155.  The address driver 7 is in read mode, and the address driver 6 is in write mode.  A high potential from the output of the element AND 69 address formers 7 to exit 44 through the third input of the element 2 AND-OR 151 enters the second input of the element AND 156 (high potential at the third input).  Upon receipt of a pulse signal from the output of the element OR 120 (FIG.  7) at the first input element And 156 (FIG.  9) at its output, an array reading end signal is generated, which sets the trigger 132 to the zero state, stopping the reading process.  A high potential from the output of the element AND 69 of the address setting device 6 to the output 43 through the third input of the element 2 I-ШШ 154 is fed to the first input of the element I 157 (high potential at the second input).  When a pulse signal comes from the output of element 131 (FIG.  B) at the third input of the AND element 157, at its output, a signal is generated at the end of the array recording, which performs actions similar to those in the previous stages.  A unit is added to the counter of steps 87, and a high potential is set at the fourth output on the decoder of the stages. .  In the fourth step, the calculation of the Fourier coefficients is made according to formulas (2) (I. (Vl)),. . . , (g-i); wjj-. e 1, 2, 3 The calculation of the Fourier coefficients by formulas (9) and (10) is similar to performing any iteration with the exception of three differences.  The first difference is in the first-order transmission of the complex operand () to registers 45 and 46 of the arithmetic unit 1 from the random-access memory unit 2 or 3.  This is both baked by applying a high potential from an And 112 element output (FIG.  7) on output 29 to the fourth inputs of elements 2 AND-OR 9 and 10 for the duration of the operand (the operand code 62 itself is recorded in register 45 and the operand code (-i (;)) in register 46.  The second difference is the direct transfer to the block of permanent memory -4 of the codes of the addresses of the address counter 65 (Fig.  3), while a high potential is supplied to the second inputs of elements 2 AND-OR 67 - 67 from the fourth output of the decoder of steps 88 via bus 31-1.  Weighting coefficients are read from the constant memory block 4 to the arithmetic unit 1 and the addition of one to the address counter 65 is performed for each pair of operands processed, the first pair of operands being processed with the weighting factor at address 00. . . 0 This is achieved by adding a unit to the counter of the address 65 of the signal with the output of the register through the first input of the AND 111 element and the second input of the OR element 119 (FIG.  7) read control unit 83.  The third difference is the change in the sign of the imaginary part of the §N / 2-1 result.  to get the result. This is provided by feeding you a low potential Nfil-V from the output of the AND element 139 (FIG.  8) on the output 37 to the second inputs of the adders modulo 2 (FIG.  1) at the time of recording the result В | Ц (memory block (2 or 3).  The formation of addresses by blocks 6 and 7 for reading and writing operands, as well as the formation of signals for the read end and the end of the array write is similar to the third stage.  Signal The end of the array recording at the end of the fourth stage increases the code of the counter of steps 87, while a high potential is set at the fifth output of the decoder 88 (the step of outputting the results).  When the calculation results are output, the write control node 84 does not work, i. e.  trigger 132 (FIG.  8) is in the zero state.  Each Fourier coefficient given by the outputs 25 and 26 of the RAM 2 and 3 is accompanied by a timing signal issuing a number from the output of the AND 114 to the output 27; In the process of withdrawal, the external subscriber is issued in the natural order of § Iz.  Fourier coefficients.  At the conclusion of the output, an array reading end signal is generated, which sets the trigger state 104 to the zero state (FIG.  7).  At this point, the processor operation for calculating the Fourier coefficients ends.  It should be noted that the calculation of the Fourier coefficient with the ME number in the third and fourth stages of the processor operation is not performed: this would require the introduction of significant hardware into the processor.  An intermediate coefficient with this number, calculated at the second stage of the processor and different from the true coefficient by the sign in front of the imaginary part, is used as the Fourier coefficient with the K / 4 number.  This inaccuracy is of no fundamental importance, since at subsequent stages the sum of the squares of the modules of the real and imaginary parts is mainly used. of these coefficients.  This p-processor has a number of technical advantages over similar processors.  The main one is high speed when executing the processing of input information, high speed is achieved by presenting the actual sequence of input samples of dimension N with the complex input sequence N / 2 and introducing two stages of calculations using formulas (7) (10), which reduces time computing almost doubled; introduction and proper organization of the work of the address memory forwarders and the RAM memory itself, which eliminates downtime in the operation of the arithmetic unit and RAM blocks, t. e.  reached conveyor information processing.  Another advantage of the processor is to halve the capacity of the RAM blocks while maintaining the functionality by packing each pair of adjacent samples into each memory cell.  In addition, the output of the generated (calculated) coefficients of 10 2 Fourier in the natural order due to the implementation in the processor of the corresponding work of the address memory makers eliminates the need for rearranging the Fourier coefficients at the subsequent stages of information processing.

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Claims (2)

1. FOURIER FAST TRANSFORMING PROCESSOR, comprising an arithmetic unit, first and second memory units, a read-only memory unit, a control unit, three address drivers, two AND elements and two OR elements, the outputs of the first and second AND elements being connected to the first inputs of the first and of the second OR element, the outputs of which are connected respectively to the first and second input of the operands of the arithmetic block, the inputs of the real and imaginary part of the coefficients of which are connected respectively to the first and second outputs of the block Single po-, constant memory having an input connected to the output of the first address generator, the outputs of the second and third address generators are connected with address inputs, respectively, per-, first- and second-memory blocks, the first A and second outputs which respectively; but combined and are respectively the first and second information outputs of the processor, and the first inputs of the first and second elements And are respectively the first and second information inputs of the processor, characterized * in that, in order to increase the speed of the processor, it contains the first, second, third and fourth AND-OR elements 2, the first and second adders modulo 2, the first and second NOT elements, the first output of the control unit being connected to the first inputs of the first and second AND-OR elements 2, the outputs of which are connected to the second inputs of the first and second OR elements, respectively, the second output of the control unit is connected to the second inputs of the first and second Elements 2 AND-OR, the third and fourth inputs of which are connected respectively to the first and second outputs of the first memory unit, the third output of the control unit is connected to the second inputs the first and second elements And, the fourth output of the unit yn-. The control unit is connected to the input of the first address generator, the fifth output of the control unit is connected to the input control input of the arithmetic unit information, the outputs of the real part of the first and third operands of which are connected to the first inputs of the third and fourth elements 2 AND-OR, respectively, the outputs of which are connected to the first inputs respectively, the first and second • adders modulo 2, the outputs of which are connected respectively to the first and second information inputs; of the first and second memory units, the sixth output of the control unit is connected to the control input of summing oo oo arithmetic unit, the control input of the subtraction of which is connected * to the output of the first element NOT, the input of which is connected to the sixth output of the control unit, the seventh and eighth outputs of which are connected respectively to the second and the third inputs of the third and fourth elements 2 OR, the fourth inputs of which are connected to the outputs of the imaginary parts of the first and second operands of the arithmetic block, respectively, the ninth and ten the outputs of the control unit are connected to the second inputs of the first and second adders, respectively, modulo 2, the eleventh output of the control unit is connected to the control input of the first memory unit and the input of the second element NOT, the output of which is connected to the control input of the second memory unit, the twelfth and thirteenth outputs of the control unit connected to the inputs of the job address, respectively, of the second and third address formers, the overflow outputs of which are connected respectively to the first and second inputs of the control unit, the fourteen output of which is connected to the input of the job incrementing the addresses of the first and second address formers, the fifteenth output of the control unit is the output of the processor output information, and the third and fourth inputs of the control unit are, respectively. · The clock input and the processor synchronization input. 2. The device according to p. ^ Characterized in that the control unit comprises a step counter, a step decoder, an iteration counter, an iteration decoder, a synchronizer, four shift registers, the first and second switch, six triggers, thirty AND elements, thirteen OR elements and six elements NOT,. moreover, the output of the first element is NOT connected to the first input of the first AND element, the output of which is connected to the first input of the first OR element, the output of which is connected to the clock input of the stage counter, the output of which is connected to the input of the stage decoder, the first output of which is connected to the first input of the second element OR, the output of which is connected to the input of the second element NOT and the first input of the second element AND, the second input of which is combined with the first inputs of the third, fourth, fifth elements And, the second input of the first element And the first trigger input, the second output of the stages decoder is connected to the first input of the third OR element, the second input of the second OR element, the input of the first element NOT, the second input of the fifth AND element and the second input of the fourth AND element, the output of which is connected to the clock input of the iteration counter, the first whose output is connected to the third input of the fifth AND element, the output of which is connected to the second input of the first OR element, the third output of the stages decoder is connected to the first input of the fourth OR element, the second input of the third ele ent or the third input of the second element OR, the fourth output of the stage decoder is connected to the second input of the fourth element and the third input of the third element OR, the first output of the first switch is connected to the first input of the fourth element AND and the input of the synchronizer, the output of which is connected to the first input of the sixth element And, the first input of the fifth element OR, and I, the single input of the second trigger, the output of which is connected to the first input of the seventh element And, the output of which is connected to the clock input of the first shift register, stroke koto'-cerned is connected to the second input of the fifth OR gate, the first inputs vommogo, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth and fifteenth element and the second output of the first commutation. the torus is connected to the zero input of the second trigger and the input of the first shift register, the control input of which is connected to the output of the fifth element OR, the output of the synchronizer is connected to the first input of the sixth element OR, the output of which is connected to the input of the second shift register, the output of which is connected to the first input of the seventh element OR, the second input of which is connected to the output of the sixth element AND, the second input of which is combined with the first input of the sixteenth element And, the second input of the fourteenth element And and connected to the fourth th output of the decoder stages, the output of the third OR gate connected to the secondary ring * thirteenth inputs of the AND / and the eighth element AND, whose output is connected to the counting input of the third trigger, the single output of which is connected to the first inputs of the seventeenth, eighteenth elements And, the second input of the tenth, eleventh, fifteenth, sixteenth elements And and the third input of the fourteenth element And, the outputs of the second and third And elements are connected respectively to the e, single and zero inputs of the third trigger, the zero output of which is connected to the second input of the ninth element / AND and the third input of the thirteenth element And, the output of which connected to the first input of the eighth OR element, the second input of which is the fourth input of the control unit, the second output of the stage decoder is connected to the second input of the eighteenth AND element and the third input of the ninth AND element, the output of which is connected to the first input of the ninth OR element, the second input of which connected to the output of the tenth element And, the third input of which is connected to the second input of the seventeenth element And, the first input of the first switch and connected to the output of the fourth element OR, the fifth output of the decoder stage s connected to the second input of the twelfth AND element, the output of which is connected to the third input of the ninth OR element and is the fifteenth output of the control unit, the outputs of the seventeenth, eighteenth AND elements and the ninth OR element are connected respectively to the first, second and third inputs of the second switch, the first and second the outputs of which are the twelfth and thirteenth outputs of the control unit, respectively, the first output of the stages decoder is the third output of the control unit and is connected to the input of the third element NOT, the output of which is connected to the first input of the nineteenth AND element, the second input of which is connected to the output of the fourth element NOT, the input of which is connected to the output of the sixteenth AND element, the output of which is the second output of the control unit, and the output of the nineteenth AND element is the first output of the control unit, the third output of the first switch is connected to a single input of the fourth trigger, the single output of which is connected to the third input of the fifteenth AND element, the output of which is connected to the zero input of the fourth the trigger and the second input of the sixth OR element, the third input of which is connected to the output of the fourteenth AND element, the control inputs of the synchronizer, the second shift register and the second input of the seventh AND element are combined and are the third input of the control unit, the output of the eighth OR element is connected to the second input of the first switch and the input of the third shift register, the output of which is connected to the first input of the tenth OR element and the single input of the fifth trigger, the single output of which is connected to the first input of the twentieth ment And, whose output is connected to the clock input of the fourth shift register, the output of which is connected to the third input of the first switch and the first input of the twenty-first, twenty-second, twenty-third and twenty-fourth elements And, the first output of the first switch is connected to the zero input of the fifth trigger and the control the input of the fourth shift register, the input of which is connected to the output of the tenth OR element, the second input of which is combined with the first inputs of the twenty-fifth, twenty-sixth, twenty-seventh, d the seventy-eighth, twenty-ninth element And, the second input of the twenty-third element And is connected to the single output of the sixth trigger and forms the eighth output of the control unit, the zero output of the sixth trigger is connected to the first input of the thirtieth element Y, the second input of the twenty-second element And is the seventh output control unit, the output of the third element OR is connected to the second input of the twenty-fourth element AND, the output of which is connected to the counting input of the sixth trigger, the unit and zero inputs of which are connected with the outputs of the second and third elements AND, respectively, the second output of the stages decoder is connected to the second inputs of the twenty-fifth, thirty and twenty-sixth elements And, the first output of the iterations decoder is connected to the third input of the twenty-fifth and thirty elements AND, the input of the fifth element is NOT, the output of which is connected to the third input of the twenty-sixth element,, the output of which is connected to the first input 1086438 the house of the eleventh element OR, the second input of which is combined with the first input of the twelfth element OR and connected to the output at the twenty-fifth AND element, the output of the thirty element AND is connected to the second input of the twelfth OR element, the output of the fourth OR element is connected to the second input of the twenty-seventh AND element, the third input of the twenty-third AND element and the input of the sixth element · NOT, the output of which is connected to the third the input of the twenty second AND element, whose output is connected to the first input of the thirteenth OR element, the second input of which is connected to the output of the twenty third AND element, the third output of the iteration decoder is the sixth output of the control and is connected to the second input of the twenty-eighth AND element, the output of which is the ninth output of the control unit, the fourth output of the stage decoder is connected to the second input of the twenty-ninth AND element, the output of which is the tenth output of the control unit, the outputs of the eleventh, twelfth, and thirteenth OR elements and the output of the twenty-seventh element And connected respectively to the fourth, fifth, sixth and seventh input of the second switch, the second output of the twentieth element And and the clock input of the third shift of the register are combined and form the third input of the control unit, the first, second, third and fourth outputs of the iteration decoder are the fourteenth output of the control unit, the output of the first trigger is connected to the fourth input of the first switch and the eighth input of the second switch and is the eleventh output of the control unit, the first output the stage decoder is the third output, · the house of the control unit, the output of the fourth and seventh elements OR are the fourth output of the control unit, the output of the eleventh element AND, the output the second and third shift registers and the output of the eighth element IIII form the fifth output of the control unit, and the fifth and sixth inputs of the first switch are respectively the first and second inputs of the control unit.