SU1101835A1 - Arithmetic unit for executing fast fourier transform - Google Patents

Abstract

1. ARITHMETIC DEVICE FOR QUICK FURIER CONVERSION, containing two input registers of numbers, an input register of a weighting factor, a multiplying block, two registers of addends, an adder, a switch, four result registers and a control unit, which, in order to simplify device, the control unit contains a clock generator, a clock counter, a decoder, an OR element, and a memory block, the information inputs of the input number registers are combined, and are the first input of the device, the output of the first input A single register of numbers is connected to the first input of the multiplier. unit, the second input of which is connected to the output of the register of the weighting factor, whose information input is the second input of the device, the output of the multiplying unit is connected to the information input of the first register of the addends, the output of which is connected to the information input of the second register, the output of which is connected to the first information input of the adder, the output of which is connected to the information inputs of the result registers, the outputs of which are interconnected and connected to the first information input switch, the second information input of which is connected to the output of the second input register of numbers, the switch output is connected to the second information input of the adder, the output of the clock generator of the control unit is connected to the counting input of the clock counter, the outputs of which are connected to the address inputs of the memory block, in addition, the outputs of the lower ones The bits of the clock counter are connected to the inputs of the decoder, the first, second, third and fourth outputs of which are connected to the inputs of the input and the input. S issuing the first, second, third. SL and the fourth result registers, respectively, the second and fourth outputs of the decoder are connected to the input inputs of the first and second, input number registers, respectively, as well as the inputs of the OR element, the output of which is connected to, the input inputs of the first and second registers and the weight coefficient register, the first the output of the memory block is connected to the control input of the sumeomator, the second output of the memory block is connected to the control input of the comzc mutator. 2. The device according to claim 1, characterized in that, for the purpose of ensuring uniform results, it additionally contains four output registers, the information inputs of which are combined and, connected to the output of the adder, the input input of the first output register and the input output of the fourth the output register is connected to the third output of the memory block, the output input of the first output register and the input input of the fourth output register are connected to the fourth output of the block

Description

the memory, the input inputs of the second and fourth output registers are connected respectively to the fifth and BocbivHM outputs of the memory block, the output inputs of the second and third output registers are connected to the sixth and seventh outputs of the memory block, respectively.

The invention relates to computing and can be used in the construction of devices that re-enable the Fast Fourier Transform (FFT) algorithm.

A device that performs operations with complex numbers is known. The device contains registers of the real and imaginary parts of factors, shapers of bit products, combinationally-accumulating adders, a block of translation into the additional code l.

However, this device requires a large amount of equipment.

The closest to the invention of the technical entity is a device for fast Fourier transform, containing four input registers of numbers and two input registers of weight coefficient, whose inputs are device inputs, multiplier unit, adder, cog / addend components, commutator of factors, two registers of adjectives , four work registers and a control unit, the first output of which is connected to the control input, the commutator of the addends, the second output - to the control input of the commutator commutator, the outputs of the registrar The weighting factor is connected to the first two information inputs of the commutator commutator, the outputs of which are connected to the inputs of the multiplying unit, the outputs of which are connected to the inputs of the registers of the works, the outputs of which are connected to the first four information inputs of the commutator of the summands, the other four information inputs of which are connected to the outputs of the input number registers, the outputs of the commutator switch are connected to the inputs of the adder, the output of which is connected to the output of the device and to the inputs of the registers aemyh, the outputs of which are connected to the third and fourth data inputs of the register 2 factors.

A disadvantage of the known device is the high cost of the equipment and the multitude of inputs, which requires memory opening, and this, in turn, leads to an increase in external connections and complication of addressing or the need to install a data distributor.

at the input of the device.

The aim of the invention is to simplify the device.

The goal is achieved by the fact that in an arithmetic unit for fast Fourier transform,

containing two input registers

numbers, input weight register, multiplying block, two summand registers, adder, switch, control block and four result registers, the control block contains a clock generator, a three-bit clock counter, a decoder, an OR element, and a firmware memory block, and the information inputs of the the number registers are combined and are the first input of the device, the output of the first input number register is connected to the first input of the multiplying unit, the second input of which is connected to the output of the weight register wow

coefficient, information input

which is the second entrance

devices output multiplier

block is connected to the information

the input of the first registrar register, the output of which is connected to the information input of the second register of the addends, the output of which is connected to the first information input of the adder, the output of which is connected to the information inputs of the result registers, the outputs of which are interconnected and connected to the first information input of the switch; the information input of which is connected to the output of the second input register of numbers, the output of the switch is connected to the second information input of the adder, the output of the generator is pulsed the control unit

connected to the counting input of the clock counter, the outputs of which are connected to the address inputs of the memory block; in addition, the low-level bits of the clock counter are connected to

the inputs of the decoder, the first, second, third and fourth outputs of which are connected to the input input and the input issuance of the first, second, third and fourth result registers

respectively, the second and fourth outputs of the decoder are connected to the input inputs of the first and second input number registers, respectively, as well as the inputs of the OR element, the output of which is connected to the input inputs of the first and second registers of the weighting factor and-register, the first output of the memory unit The adder's input, the second output of the memory unit is connected to the control input of the switch. In addition, in order to ensure uniform results, the device additionally contains four output registers, informational inputs of which are combined and connected to the output of the adder, the input input of the first output register and the output input of the fourth output register are connected to the third output of the memory unit, the output output of the first output the register and the input of the fourth output register are connected to the fourth output of the memory block, the receive inputs of the second and fourth output registers are connected respectively to the fifth and Eighth outputs the memory block, the inputs of the second issue and the third output registers connected respectively to the outputs of the sixth and seventh memory block. Figure 1 shows the structural diagram of the device; in fig. 2 is a block diagram of a device that provides a uniform output of the TOBJ result in FIG. 3 is a block diagram of the control unit; in fig. 4 is a timing diagram illustrating the operation of the device; in fig. 5 is a block diagram of the operation of the control unit. An arithmetic unit for fast Fourier transform contains two input registers 1 and 2 numbers, the information inputs of which are combined and are the first input of the device, input register 3, the weight coefficient, the information input of which is the device's input. The outputs of the input register 1 of the numbers and the input register 3 of the weighting factor are connected respectively to the first and second inputs of the multiplying unit 4, the output of which is connected to the information input of the first register 5 terms The output register 5 terms the connection information input of the second register 6 terms. The output of the addendum register is connected to the first information input of the adder 7, the output information of the switch 8 is connected to the second information input, the information inputs of the result registers 9t12 are interconnected and connected to the output of the adder 7. The outputs of the result registers 9fl2 are interconnected and are the output of all the device, in addition, the outputs of the registers 9412 results connected to the first information input of the switch 8, Voo-a swarm whose information input is connected to the output of the input register 2 numbers. The outputs of the control unit 13 are connected to the control inputs of all the registers, the adder 7 and the switch 8. The arithmetic unit for fast Fourier transform, providing uniform results, contains four additional output registers 14t17, whose information inputs are interconnected and connected to the output of the adder 7, and the outputs of the output registers 14-117, also interconnected, are output 18 of the entire device. The control inputs for receiving and outputting the output registers 14 -: - 17 are connected to the corresponding outputs of the control unit 13. Adder 7 is a adder that has a control input for the operation to be performed. Directly combining the outputs of the result registers is permissible if registers with three output states are used as these registers. The control unit 13 of FIG. 3 contains a generator of 19 clock pulses, the output of which is connected to the counting input of a three-bit counter of 20 cycles. The first (minor) and second outputs of the counter 20 are connected to the corresponding inputs of the decoder 21, in addition, the first, second and third outputs of the counter 20 are connected to the corresponding inputs of the microprogram memory unit 22. The second and fourth outputs of the decoder 21 are connected to two inputs of the OR element 23, the output of which is the output 24 of the 13-control unit. The first, second, third and fourth outputs of the decoder 21 are. . respectively, the outputs 25 through 28 of the control unit 13, and the first and second outputs of the memory unit 22 are outputs 29 and 30. The output 2 5 is connected to the receive synchronous input and to the control input of the output of the register 11, the output 26 is connected to. synchronization inputs of reception of registers 1 and 12 and with the control input of the output of register 12, output 27 is connected to the synchronization input and to the control input of the register 9, output 28 is connected to the synchronization of reception of registers 2 and 10, the output 29 is connected to the control input of the adder 7, the output 20 to the control input to the mutator 8. With the introduction of four output registers 14r17 in the control block 13, the memory block 22 contains six outputs more, and the output of the memory block is connected to the synchronous receiving register 14 and with the register control input 17, the output is connected to the register receive 16 clock and the register 14 control input, output 33 is connected to the register 15 clock input, output 3.4 is connected to the register output control input 15, output 35 is connected to the control input output of register 16, and output 36 — with a synchronous input of reception I of register 17. In FIG. 5, the following conventional designations are accepted: ij-i-th-cycle, j-th-palutakt} s - result at the output of adder 7; FFT - the moment of issuing the results of the transformation, indicating which one, namely, the result gives s; Pr1 2 - input registers of the numbers 1 and Prz - the register of the weighting factor 3; Prg5 - the first register of the terms 5 Pgb - the second register of the terms of 6 Pr9tl2 - registers of results of 9г12 МО - the result at the output of multiplying block 4; Pr14-r17 - output registers 14r17 The device performs the basic operation of the fast Fourier transform algorithm at the base 2 A; B; tC; W; AI ,, B, -C.VJ ReA; ReB; + ReC, ReW-I C ;. ImA; - l B, + (eCi-i, .ReW ReA; t, ReBrReC; -ReW t C. .r4B; -ReC;.,. ReW, where Bj, -C; are the original samples; A ;, A ;,, - converted samples W - weighting factor, s-iT-, w.eJ, j 4Tj Ы - number of samples in the original array; s - real part of the h and eat a; Itn - imaginary part of the number. We assume that the information is received in the registers at the moment when the trailing edge of the sync pulse arrives. At the end of the first clock cycle, the output from control unit 13 of the control unit 13 in the input number register 1 takes the real part ReC; The weight register 3 of the signal from output 24 is valid, the ReW part of the weight coefficient W. In the second cycle, multiplication is performed in duplication unit 4 and the product Re C; -Raw from the signal from output 24 is received in register 5. By the same signal In register 3, the imaginary part 01 W of the weight coefficient W- is received, and by the signal from output 28 in the register of 2 numbers the real part Re B of the original count B is received ;. In the third cycle, multiplication is performed and the product of ReC | L, W is taken from output 24 to register 5 by the signal from output 24; according to the same signal, register 6 accepts the product Rec. RE W. and register 3 - the imaginary part 3n, W of the weight coefficient W; in the input register 1 of the numbers, the output from the signal 26 receives the imaginary part of the original count C ;. In the fourth cycle in multiplication block 4, multiply and produce 3mC-1rn no, the signal from output 24 is received in register of 5 terms, and the product Ret is received in register b by the same signal; .W, and in input register 3, the ReW part of the weight coefficient W is valid. The signal from output 28 to input register 2 receives the imaginary part 3t S, the original reference B, -. The switch 8 to the signal from output 30 connects to the input of the adder 7, the output of the input register 2 numbers. The adder 7, based on the signals from output 29, performs the addition operation in the first half of the fourth cycle, and the subtraction operation in the second half. Accordingly, Kev; + (ec - rew on the signal from output 27 is received in register 9 in the middle of the fourth cycle, and the difference ReB, -ReCReW ° from output 28 at the end of the fourth cycle. And is taken in register 10. In the fifth cycle in multiplication block 4, the multiplication and the product l | T | C; -Rewno are performed; the signal from output 24 is received in register 5, the product ReW from this signal is received in register 6, and in input

register 3 is the real part of RP. In input register 1, the output part of the next reference point C, is taken from output.26. Switch 8 by the signal from output 30 connects

to the input of the adder 7, the output of the input register 2. The adder 7, according to the signals from the output 29, performs the operation of a half- and second-half clock and the subtraction operation — in the second

half. In the middle of the fifth cycle, the sum I Sj ReC, on the signal from the output 25, is taken into register 11, and at the end of the fifth cycle the difference is 1 8; -RsC. the signal from output 26 is received in register 12. In the sixth cycle in the duplication block 4 multiplication is performed and the product of € ReC from the signal from output 24 is received in register 5, the product ReW is received in register b by the same signal; and in register 3 - imaginary part of the weighting factor. In input register 2, the actual part YeV of the initial sample Bj, is taken from the output 28 signal. Switch 8, based on the output 30, connects the combined output of the result registers 9fl2 to the input of the adder 7. The adder 7, based on the signals from output 29, performs the subtraction operation in the first half of the sixth clock cycle and the addition operation in the second half. In the first half of the sixth clock cycle, the signal from output 27 of register 9 gives the sum of ReB; + ReC; and in the middle of a clock cycle by the same signal (on the falling edge) in register 9 the difference ReAi Jaeb is received ;; - ReC; -ReVj-I C -l W. In the second half of the numbered clock cycle the signal from output 28 of register 10 yields the difference ReVi / and, at the end of the clock cycle, the sum ReA ;, ReB; -ReC; ReW + is received at the same signal into register 10.

In the seventh cycle in multiplication block 4, multiplication and the product ReC; I, are performed; the signal from output 24 is received in register 5, and in register B by the same signal. the product Rec-REW is received, and in the input register 3, the imaginary part of the weighting factor W. In the input register 1, the output signal 26 is taken from the imaginary part of the original reference C,. The switch 8 on the signal from output 30 connects to the input of the adder 7 the combined output of registers 94-12 results. The adder 7, according to the signals of the c-output 29, performs the addition operation and the subtraction operation in the first and second halves of the seventh cycle, respectively. In the first half of the seventh clock cycle, the signal from output 25 from register 11 yields the sum ReC I, v, and in the middle of the clock, the sum I ft is received into the register 11; l "B; t Rec ;. UC-ReWV In the second half of the seventh cycle, a difference from the output signal from register 12 is outputted to the signal from output 26; - ReC; tn, W, and at the end of the clock cycle, the difference | 1 "1 lm vB; -ReC; -l C; -ReVKV

In the eighth cycle, the multiplication unit 4 performs the multiplication and the product In, takes the signal from output 24 to register 5, and to register 6 uses the same signal to accept the product g and in register 3 the actual weight is calculated. in input register 2, the output from 28 is assumed to be the imaginary part 1 9, h, of the initial reference b. The switch 8 on the signal from the output 30 connects to the input of the cooler 7 the output of the input register 2 numbers. The adder 7 performs addition and subtraction operations in the first and second halves of a clock, respectively. In the first half of the eighth clock cycle from register 9, the real part of He A is output from the device; transformed by A, by the signal from output 27 and by the same signal (by the falling edge) in register 9 the sum Re 8 is received; , + fReC, -. In the second half of the eighth clock cycle from register 10, the real part Re D; is output to the device's slab by the signal from output 28, and the difference ReB;, - ReCi ,, is received at the same signal in register 10

In the first half of the tenth cycle, the signal from output 25 of register 11 outputs the imaginary part In, A; converted reference L; and on the same signal, the sum 11 ,, 4 ReC ,, - UW is accepted into register 11. In the second half of the ninth clock cycle, a signal from output 26 of register 12 sends the imaginary part 1 "A ;," of the converted reference A to the device output, and the difference, - ReCi, is received into the register 12 by the same signal. The operation of the elements of the device is similar to that described for the fifth cycle.

Further operation of the entire device is similar.

With the introduction of the four output registers 14717, the operation of the device differs only in cycles 6-9, related to recording the converted samples and outputting them to the output of the device. Namely, in the middle of the sixth cycle, the real part of Re A is valid;

the converted reference A, is not accepted into register 9, but into register 14, respectively Re A i., / lyriA; flmAUi is accepted into registers 15-17. Then, the output of the transformed samples can be performed independently of intermediate calculations, and evenly, i.e. one result for one measure. For example, in the seventh clock cycle, the output of the device is given by ReA t in the eighth -ReA r in the ninth -1 t L in the tenth - + 1 and in the middle of the tenth clock cycle in the register 14 is taken ReA and then .ReA, 4, / T, l;, uh, respectively, in the tenth and odnadtsa t'm tkktah registers 15-17, and in

ig. i

the eleventh cycle can already be issued the twelfth Re A ,, etc.

Thus, in comparison with the known device, the proposed

with the same performance, there are three registers and one switch less, and the known device includes complex multi-input switches, and the proposed one is simple

two-way. In addition, the known device has six inputs, whereas the proposed device has only two, which significantly reduces the number of external connections and allows

work with linearly organized; memory

20

FIG. year

2it

23

g

S

2 27

J b

.J /

-D ± w

S tjff

Claims (2)

1. Arithmetic device for fast Fourier transform, containing two input register of numbers, input register of weighting factor, multiplier 'block, two register of terms, adder, switch, four register of results and control unit, which differs in that, for the purpose to simplify the device, the control unit contains a clock generator, a clock counter, a decoder, an OR element and a memory unit, the information inputs of the input number registers being combined. and are the first input of the device, the output of the first input p A number register is connected to the first input of the multiplier. block, the second input of which is connected to the output of the register of the weight coefficient, the information input of which is the second input of the device, the output of the multiplier block is connected to the information input of the first register of terms, the output of which is connected to the information input of the second register of terms, the output of which is connected to the first information the adder input, the output of which is connected to the information inputs of the result registers, the outputs of which are interconnected and connected to the first information input 'lutator, the second information input of which is connected to the output of the second input register of numbers, the output of the switch is connected to the second information input of the adder, the output of the clock generator of the control unit is connected to the counting input of the clock counter, the outputs of which are connected to the address inputs of the memory block, in addition, the outputs the least significant bits of the clock counter are connected to the inputs of the decoder, the first, second, third and fourth outputs of which are connected to the inputs of the reception and input, issuing the first, second, third. and the fourth registers of results, respectively, the second and fourth outputs of the decoder are connected to the inputs of the reception of the first and second, input registers of numbers, respectively, as well as to the inputs of the OR element, the output of which is connected to the inputs of the reception of the first and second registers of terms and register of the weight coefficient, the first output the memory block is connected to the control input of the adder, the second output of the memory block is connected to the control input of the switch. 2. The device pop. 1, characterized in that, in order to ensure uniform output of the results, it further comprises four output registers, the information inputs of which are combined and connected to the output of the adder, the input input of the first output register and the output input of the fourth output register are connected to the third output of the block memory, the input output of the first output register and the input input of the fourth output register are connected to the fourth output of the block SU ..1101835 memory, the input inputs of the second and fourth output registers are connected respectively to the fifth and eighth outputs of the memory unit, the outputs of the second and third output registers are connected respectively to the sixth and seventh outputs of the memory unit.