SU1272492A1

SU1272492A1 - Pulse-duration discriminator

Info

Publication number: SU1272492A1
Application number: SU853868394A
Authority: SU
Inventors: Галина Николаевна Верещагина; Владимир Юрьевич Демьяненко; Юрий Петрович Канищев
Original assignee: Войсковая часть 45807-Р/П
Priority date: 1985-03-18
Filing date: 1985-03-18
Publication date: 1986-11-23

Abstract

Изобретение может быть использовано в аппаратуре обработки потоков импульсных сигналов пр моугольной формы. Целью изобретени вл етс расширение функциональных возможностей устройства. Цель достигаетс введением триггера I1, элемента ИЛИ 10, запоминающих устройств 8 и 9. Устройство содержит, кроме того, генератор 1 тактовых импульсов, инвертор 3, элементы И 2 и 13, счетчики 4 и 6 импульсов, триггеры 5 и 7, выходные шины 13 и 14. Устройство обес9 печивает выделение из потока импульсов , длительность которых меньше за (Л данного порога селекции в широком диапазоне значений. 3 ил.The invention can be used in the apparatus for processing streams of pulsed signals of a rectangular shape. The aim of the invention is to expand the functionality of the device. The goal is achieved by introducing trigger I1, element OR 10, memory devices 8 and 9. The device also contains 1 clock pulse generator, inverter 3, AND 2 and 13 elements, pulse counters 4 and 6, triggers 5 and 7, output buses 13 and 14. The device ensures separation of pulses from the stream, the duration of which is less than (L of a given selection threshold in a wide range of values. 3 Il.

Description

Изобретение относится к импульсной технике и радиотехнике и может быть использовано в аппаратуре обработки потоком импульсных сигналов прямоугольной формы.The invention relates to a pulse technique and radio engineering and can be used in apparatus for processing a rectangular pulse waveform.

Цель изобретения - расширение функциональных возможностей устройства путем выделения из потока импульсов, длительность которых меньше заданного порога, и оперативного изменения порога селекции в широком диапазоне значений за счет продления первым счетчиком импульсов паузы между входными импульсами и задержки потока входных импульсов вторым счетчиком импульсов и оперативными запоминающими устройствами на время, равное порогу селекции и установки значения этого порога в счетчиках импульсов непосредственно перед обработкой каждого входного импульса.The purpose of the invention is to expand the functionality of the device by isolating pulses from the stream, the duration of which is less than a predetermined threshold, and quickly changing the selection threshold in a wide range of values by extending the pause between the input pulses by the first pulse counter and delaying the input pulse stream by the second pulse counter and random access memory for a time equal to the threshold of selection and setting the value of this threshold in pulse counters immediately before each Khodnev pulse.

На фиг. I представлена функциональная схема устройства; на фиг. 2вариант включения двух селекторов импульсов по длительности для полного разделения потока входных импульсных сигналов; на фиг. 3 - временные диаграммы, поясняющие работу устройства.In FIG. I is a functional diagram of the device; in FIG. 2 option to turn on two pulse selectors in duration to completely separate the input pulse signal stream; in FIG. 3 is a timing diagram explaining the operation of the device.

Устройство содержит генератор 1 , тактовых импульсов, первый выход которого соединен с одним входом элемента И 2, другой вход которого является входом устройства и соединен с входом элемента НЕ 3, выход которого соединен с входом разрешения записи счетчика 4 импульсов, тактовый вход которого соединен с выходом элемента И 2, выход переполнения с входом установки единицы триггера 5, а информационные входа счетчика 4 импульсов являются информационными входами устройства и соединены с информационными входами счетчика 6 импульсов, выход переполнения которо-го соединен со счетным входом триггера 7, прямой и инверсный выходы которого соединены с входами разрешения записи-считывания соответственно первого 8 и второго 9 оперативных запоминающих устройств (ОЗУ), входы стробирования которых соединены с первым выходом генератора 1 тактовых импульсов и тактовым входом счетчика 6 импульсов, выходы разрядов которого соединены с адресными входами ОЗУ 8 и 9, выхода которых соединены соответственно с первым и вторым вхо272492 * дами элемента ИЛИ 10, выход которого соединен с информационным входом триггера 1I, тактовый вход которого соединен с вторым выходом генерато5 pa 1 тактовых импульсов, а инверсный выход - с входом установки нуля триггера 5, прямой выход которого соединен с первой выходной шиной 12 устройства, а инверсный выход соединен 10 с первым входом элемента И 13, второй выход которого соединен с прямым выходом триггера 11, а выход соединен с второй выходной шиной 14 устройства.The device contains a clock generator 1, the first output of which is connected to one input of the AND 2 element, the other input of which is the input of the device and connected to the input of the HE 3 element, the output of which is connected to the write permission of the 4 pulse counter, whose clock input is connected to the output element And 2, the overflow output with the installation input of the trigger unit 5, and the information inputs of the counter 4 pulses are information inputs of the device and are connected to the information inputs of the counter 6 pulses, the output is overflow of which is connected to the counting input of trigger 7, the direct and inverse outputs of which are connected to the write-read enable inputs of the first 8 and second 9 random access memory (RAM), respectively, the gating inputs of which are connected to the first output of the clock generator 1 and the clock input counter 6 pulses, the outputs of the discharges of which are connected to the address inputs of RAM 8 and 9, the outputs of which are connected respectively to the first and second inputs 272792 * of the element OR 10, the output of which is connected to the information input trigger 1I, the clock input of which is connected to the second output of the generator 5 pa 1 clock pulses, and the inverse output is connected to the zero-setting input of trigger 5, the direct output of which is connected to the first output bus 12 of the device, and the inverse output is connected 10 to the first input of the And 13 element, the second output of which is connected to the direct output of the trigger 11, and the output is connected to the second output bus 14 of the device.

Селектор импульсов по длительности работает следующим образом.The pulse selector in duration works as follows.

На вход устройства поступают сигналы в виде импульсов прямоугольной 2Q формы. Импульсу соответствует напряжение логической единицы, паузе логического нуля (фиг. За). В момент времени, соответствующий паузе входного импульса, через элемент НЕ 3 25 происходит начальная установка в счетчике 4 импульсов кода, при котором обеспечивается время заполнения счетчика 4 импульсов, равное порогу селекции . Во время действия на эд входе устройства импульса через элемент И 2, происходит передача тактов с первого выхода генератора 1 тактовых импульсов на тактовый вход счетчика 4 импульсов. Через время Т на выходе переноса образуется сигнал, ³⁵ устанавливающий триггер 5 в единичное состояние. Импульсами с первого выхода генератора тактовых импульсов постоянно тактируется счетчик 6 импульсов с устанавливаемым с информа⁴⁰ ционных входов модулем пересчета, соответствующим времени порога селекции Tj . Выходы разрядов этого счетчика импульсов формируют адресный код, поступающий параллельно на 45 ОЗУ 8 и 9. С периодом Т₁ на выходе переноса счетчика 6 импульсов формируются сигналы, поступающие на счетный вход, триггера 7. Прямой выход триггера 7 управляет попеременно эа5° писью-считыванием в ОЗУ 8. Инверсный выход триггера 7 соединен с входом разрешения записи-считывания ОЗУ 9. Тем самым осуществляется противофазная работа ОЗУ 8 и 9. В качестве стробирующего сигнала для обоих ОЗУ используется пауза между тактовыми импульсами, поступающими с первого выхода генератора 1 .The input of the device receives signals in the form of pulses of a rectangular 2Q shape. The pulse corresponds to the voltage of a logical unit, a pause of logical zero (Fig. Over). At the moment of time corresponding to the pause of the input pulse, through the element HE 3 25, the code is initially set in the counter 4 pulses, at which the filling time of the counter 4 pulses is equal to the selection threshold. During the action on the ed input of the pulse device through the And 2 element, the clocks are transferred from the first output of the clock pulse generator 1 to the clock input of the 4 pulse counter. After a time T at the output of transference is formed signal ³⁵ sets the flip-flop 5 in one state. The pulses from the first output of the clock generator are constantly clocked counter 6 pulses with installed from ⁴⁰ information inputs conversion module corresponding to the selection threshold time Tj. The outputs of the bits of this pulse counter form an address code that arrives in parallel to 45 RAMs 8 and 9. With a period of T ₁ , signals are transferred to the counting input of trigger 7 at the transfer output of the pulse counter 6. The direct output of trigger 7 controls alternately ea5 ° read-write in RAM 8. The inverse output of flip-flop 7 is connected to the write-read enable input of RAM 9. In this way, out-of-phase operation of RAM 8 and 9 is performed. A pause between clock pulses from the first one is used as a gate signal for both RAM generator output 1.

С выходов ОЗУ 8 и 9 считываемые сигналы через элемент ИЛИ 10, поступают на информационный вход триггера II. Ввод информации в этот триггер осуществляется по тактовому импульсу, поступающему на вход синхронизации с второго выхода генератора 1 тактовых импульсов. Периоды следования импульсов на обоих выходах генератора 1 равны, последовательности импульсов имеют повышенную скважность и сдвинуты между собой, напри4 и Т_? (фиг. Зе). Измеподаваемых на информасчетчиков 4 и 6 имоперативно изменять и Т₂.From the outputs of RAM 8 and 9, the read signals through the element OR 10 are fed to the information input of trigger II. Information is entered into this trigger by a clock pulse supplied to the synchronization input from the second output of the clock generator 1. The pulse repetition periods at both outputs of generator 1 are equal, the pulse sequences have increased duty cycle and are shifted between each other, for example, 4 and T _? (Fig. Ze). Measured by information counters 4 and 6 and change T ₂ .

значений градесятки - ты10degradic values - you are 10

1272492 вале между Т нением кодов, ционные входы пульсов, можно величины порогов селекции Т,1272492 valleys between T nenie codes, ional inputs of pulses, you can select thresholds T selection,

Использование типовых ОЗУ в интегральном исполнении позволяет работать устройству при разнице ниц порогов сячи раз.The use of typical RAM in an integrated design allows the device to work with a difference in the thresholds ssyach times.

Claims

The invention relates to a pulse technique and radio engineering and can be used in the equipment for processing a stream of pulse signals of a rectangular shape. The purpose of the invention is to expand the functionality of the device by extracting pulses from a stream that are less than a predetermined threshold and quickly changing the selection threshold in a wide range of values by extending the pause between the input pulses by the first counter of pulses and delaying the stream of input pulses by the second pulse counter and operative memory devices for a time equal to the threshold of selection and setting the value of this threshold in the pulse counters immediately before processing each th input pulse. FIG. 1 shows a functional diagram of the device; in fig. 2 option for switching on two pulse selectors by duration to completely separate the stream of input pulse signals; in fig. 3 - timing diagrams for the device operation. The device contains a generator of I clock pulses, the first output of which is connected to one input of the element AND 2, the other input of which is the input of the device and connected to the input of the element HE 3, the output of which is connected to the recording enable input of the counter of 4 pulses, the clock input of which is connected to the output element 2, the overflow output with the installation input of the trigger unit 5, and the information inputs of the pulse counter 4 are information inputs of the device and connected to the information inputs of the pulse counter 6, the output pe The length of which is connected to the counting input of the trigger 7, the direct and inverse outputs of which are connected to the write / read enable inputs of the first 8 and second 9 random access memories (RAM), respectively, the gating inputs of which are connected to the first output of the clock generator 1 and the clock input of the counter 6 pulses, the outputs of the bits of which are connected to the address inputs of RAM 8 and 9, the outputs of which are connected respectively to the first and second inputs of the 22 or 10 element, the output of which is connected to the information input Trigger 11, the clock input of which is connected to the second output of the clock generator 1, and the inverse output to the input of the zero setting of the trigger 5, the direct output of which is connected to the first output bus 12 of the device, and the inverse output is connected to the first element of the I 13, the second output of which is connected to the direct output of the trigger 11, and the output is connected to the second output bus 14 of the device. The pulse selector in duration works as follows. Signals in the form of rectangular pulses are input to the device. The impulse corresponds to the voltage of a logical unit, the pause of a logical zero (Fig. 3a). At the moment of time corresponding to the input pulse pause, the initial setting in the counter 4 pulses of the code takes place through the element NO 3, which ensures the filling time of the counter 4 pulses equal to the selection threshold T. During the action at the input of the device impulse through the element 2, cycles from the first output of the generator 1 clock pulses to the clock input of the counter 4 pulses. After time T, a signal is generated at the transfer output, setting trigger button 5 into one state. The pulses counter from the first output of the clock generator continuously counts the pulse counter 6 with the recalculation module installed from the information V54ODV corresponding to the time of the selection threshold T. The outputs of the bits of this pulse counter form an address code that arrives in parallel on RAM 8 and 9. With a period T at the transfer output of the pulse counter 6, signals are input to the counting input of trigger 7. The forward output of trigger 7 controls alternately writing-reading RAM 8. The inverse output of the trigger 7 is connected to the write / read enable input of the RAM 9. Thus, the antiphase operation of the RAM 8 and 9 is performed. A pause between the clock pulses from the first one is used as a strobe signal for both RAM. the output of the generator 1. from the outputs of the RAM 8 and 9 read signals through the element OR 10, are received at the information input of the trigger II. The input of information into this trigger is carried out by a clock pulse, which enters the synchronization input from the second output of the clock generator. The periods of the pulses at both outputs of the generator 1 are equal, the sequences of pulses have an increased duty cycle and are shifted among themselves, for example, by half the follow-up period. This ensures the necessary dp for the normal operation of the device, the timing of the clock pulses. At the direct output of flip-flop 11 (Fig. Sv), the input stream of pulses, delayed by time T, is reproduced. The signals from the inverse output of the trigger 11 provide for the translation of the trigger 5 to the zero state at the moments of pauses at the delayed input stream. Thus, the nose is provided with a product at the direct output of the trigger 5 pulses, the duration of which is longer than the selection threshold T, (Fig. 3b). The signals from the inverse output of the trigger 5 prohibit the passage through the E-JQ ment And 13. pulses from the direct output of the trigger 11, in which the duration is greater than T ,. As a result, at the output of the element I 13 only a stream of pulses is reproduced, the duration of which is less than T (Fig. 3g). Using a series connection of two similar selection blocks, consisting of a set of elements included in it and clocked by one clock generator 1, a complete separation of the input pulse stream can be obtained (Fig. 2). The counters 4 and 6 of the pulses of the first selection block are tuned to a selection threshold equal to T ,, and the counters of pulses 4 and 6 of the second selection block depend on the selection threshold equal to T Tj greater than T where At the output of the first selection block, the pulses are reproduced the duration of which is greater than T, at the second exit - with a duration of less than T ,. At the first output of the selection unit, pulses are reproduced, the capacity of which is greater than 1 (fig., Rear), and at the second output - the duration of which is in inter1 92 and T (fig. Ze). By changing the codes applied to the information inputs of the counters 4 and 6 pulses, you can quickly change the values of selection thresholds 11; ai T and T .. Using typical RAM in an integrated design allows the device to operate when the difference of threshold values of selection thresholds is in tens - thousand chi times The invention selector pulses in duration, containing an input bus connected to the input of the inverter and the first input of the first element, the second input of which is connected to the first output of the clock generator, and the output is connected to the clock input of the first pulse counter, the recording enable input of which is connected to the output the inverter and the overflow output to the installation input of the unit of the first trigger, the direct output of which is connected to the first output bus, and also contains the second pulse counter, the trigger and the AND element, distinguishing with the fact that, in order to expand the functionality by selecting pulses, the duration of which is less than a predetermined threshold, and promptly changing the selection threshold in a wide range of values, a third trigger, an OR element and the first and second random-access memory are introduced into it, the inputs of which are connected to the input bus and the gating inputs to the first output of the clock generator and the clock input of the second pulse counter, the information inputs of which are information the device’s input inputs are connected to the information inputs of the first pulse counter, and the overflow output is connected to the clock input of the second trigger, the direct output of which is connected to the write / read enable input of the first random access memory, and the inverse output to the write enable access input of the second operational memory devices whose address inputs are connected to the outputs of the bits of the second pulse counter and the address inputs of the first random access memory, output one to $ 12724924

the second is connected to the first input of the elec- tric output — to the input of the zero perment OR installation, the second input of which is a soy trigger, the inverse output is kotodinen with the output of the second operatively connected to the first input of the second storage device, and you of the second And, the second input which stroke is connected to the third-j information input to the direct output of the third trigger, the clock input of the trigger, and the output to the second output is connected to the second output by the generator-output bus, the clock pulse section, and the inverse