SU1270893A1 - Phase-lock loop - Google Patents

Abstract

The invention relates to radio engineering, false settings are eliminated. The device contains a phase detector 1, a phase shifter 2, a reference frequency source 3, a low-pass filter 4, a search unit 5, a controlled oscillator 6, a frequency conversion path 7, 8-8p frequency adders, auxiliary frequency source 9, pulse spreaders 10, 12, setting indicator 11, synchronization indicator 13, elements AND 14, 15-15p, frequency discriminators 16-1bp, element OR 17. Setting the device to the mirror frequency corresponds to the coincidence of three input signals: a potential corresponding to logical 1, a pulse reference follow elnosti, short pulses supplied from the feedback circuit, and a synchronism signal indicating equality with which potential € logich.1 corresponds to the sync apparatus. With the coincidence of all 3 signals in the indicator 11, a reset signal is generated from block 5, at which the frequency of the output oscillator 6 changes in the right direction. 2 Il.

Description

The invention relates to radio engineering and can be used in frequency synthesizers containing phase-locked loop devices.

The purpose of the invention is the elimination of false settings.

Na -Fig, 1 presents structural electrical ^! scheme of a phase locked loop; Fig.2 diagrams explaining the work.

The phase locked loop contains a phase detector (PD) 1, a phase shifter 2, a reference frequency source 3, a low pass filter 4, a search unit 5, a controlled 6 generator, a frequency conversion path 7, frequency combiners 8-8i, a source of auxiliary frequencies 9, the first a pulse shaper 10 and a tuning indicator 11, a second pulse shaper 12 and a synchronism indicator 13, as well as an And 14 element, additional And 15-15r elements, frequency sign discriminators 16-16I, an OR element 17 forming a synchronism indicator 13.

The phase-locked loop (PLL) operates as follows: the mirror frequency of the adder 8 _t path frequency 7. The principle of operation of the device is illustrated using diagrams (figure 2).

The case with the cosine characteristic of the PD is considered (Fig. 2). When constructing the characteristics along the abscissa axis, the phase shift of the input signals (Λψ) is delayed.

The reference and output oscillations of the path 7 are converted into pulse sequences (f ' _o ) and (f _Df ) (Fig. 26 and c). Shapers 10 and 12 pulses provide a coincidence in time of the edges of the pulses with the passage of sinusoidal signals through a phase equal to 180.k, where k -> 0 is an integer.

A phase shift of 90 ° between the characteristic of the PD 1 and the input reference signal is provided by the phase shifter 2. At the same time, two different potentials of the reference oscillations correspond to sections of the characteristic of the PD 1 with different steepness. The first driver 10 generates short pulses, coinciding. giving in time with the passage of the signal through a phase equal to ZbO'k!

way ..

In the case when the frequency of the working oscillation takes the value f'rvn “^ 8sp 1 ⁺ - ffccn 2 ⁺ ” '° ” ⁺ ffecr) Π ⁺ 5' where ff. _VH - the output frequency of the oscillator 6, controlled

1 “ffttn j.

D, voltage;

the frequency of the input auxiliary oscillations supplied to the inputs of the frequency adders 8-8r;

frequencies of the reference oscillation, the conditions must be fulfilled: b _VSN1 ^p tuc ^_ fftcnl ^{? f} Bcn2 f g / n - f bcc * * · (a) (b)

The fulfillment of condition (a) is ensured by the choice of the sign of the slope of the phase detector (PD) 1. Non-compliance with condition (a) is equivalent to a change in the sign of the conversion of the first frequency adder 8 and, therefore, a change in the sign of the slope of the PD 1. That is, when, the PLL device operates on another branch of the characteristic

PD 1. This property is used to indicate a false setting on

Thus, the coincidence in time of short pulses with the positive or negative potential of the reference pulse sequence corresponds to the positive and negative steepness of PD 1 and, therefore, the PLL device is set to working (/ уц ~ f Aux 1) or mirror (f _{6l! Ni} - f _{ry (1)} the frequency of the frequency _f of the adder 8. Feeding direct or inverted sequence of reference pulses to the coincidence circuit, it is possible to select the conversion conditions in the adder 8 • _{{frequencies.} Configuring PLL frequency devices for mirror 45 correspond ^J coincidentally on time three input signals: a potential corresponding to a logic one, a reference pulse sequence (fo) (2b), short pulses fed to the feedback circuit (f _ot ') (fig.2g) and a synchronism signal indicating which equation logical unit potential corresponds to synchronization mode

5S PLL devices. If all three signals coincide, a reset signal is generated in the setting indicator 11 for the search unit 5, at which the frequency

1270893 4 of the output oscillation of the generator 6 is changing in the right direction.

The fulfillment of conditions (b) is monitored by discriminators 16 of the frequency sign, the inputs of which receive input-5 oscillations of all adders, starting from the second, the frequency of the path 7, except the first, and the output generates a signal equal to the potential of a logical unit, if condition (b) is not performed. This means that in the false synchronization mode of the device, when the output of at least one frequency adder 8 produces a mirror frequency, the search unit 5 will fail.

From the principle of operation it follows that if there is only one frequency adder 8 in the path 7, the tuning indicator 11 should be made in the form of one AND element, the output of which is connected to the search unit 5.

Thus, in the proposed device provides reliable 25 protection from false settings of the PLL to mirror frequencies by introducing a tuning indicator and pulse shapers.

Claims (1)

The invention relates to radio engineering and can be used in frequency synthesizers containing phase locked loops. The purpose of the invention is to eliminate false settings. Fig. 1 shows a structural electrical circuit of a phase locked loop device; 2, diagrams illustrating the work. The phase locked loop contains a phase detector (PD) 1, a phase shifter 2, a reference frequency source 3, a low-pass filter A, a search block 5, control 6 generator 6 frequency conversion path 7, frequency accumulators 8-8ii, auxiliary source 9, frequency the second shaper has 10 pulses and a setting indicator 11, a second shaper of 12 pulses and a synchronism indicator 13, as well as an AND 14 element 15 AND 15-15, frequency differences 16-16P, the OR 17 element forming the synchronism indicator 13. A phase locked loop (PLL) works as follows. In the case where the frequency of the operating oscillation is 8Cni.- fecn2 fecri n and where f is the frequency of the output oscillator of the voltage-controlled oscillator 6; frequency auxiliary oscillations5 supplied to the inputs of the adders frequency 8-8p; fy are the frequencies of the reference oscillation; therefore, a change in the sign of the slope of the PD 1. That is, with ffyy fecni, the PLL operates on a different branch of the PD characteristic 1. This property is used to indicate a false setting on the mirror frequency of the frequency 8 8 adder. 7 The principle of operation of the device is explained using diagrams (Fig. 2). The case with the cosinusoidal characteristic of PD (figure 2) is considered. When plotting the characteristic along the abscissa axis, the phase shift of the input signals (DF) is postponed. The reference and output vibrations of the path 7 are converted into pulse sequences (fo) and (fpf) (Fig. 26 and c). The shapers of 10 and 12 pulses ensure the coincidence of the pulse fronts with the passage of sinusoidal signals through a phase equal to 180.k, where is an integer. A phase shift of 90 between the PD 1 characteristic and the input reference signal is provided by the phase shifter 2. In this case, two different potential of the reference oscillation correspond to the sections of the PD 1 characteristic with a different slope. The first driver 10 generates short pulses, the same. giving in time with a signal passing through a phase equal Thus, the coincidence in time of short pulses with a positive or negative potential of the reference pulse sequence corresponds to the positive and negative slope of PD 1 and, therefore, to setting the PLL device to working (f - fgjp) or mirror ( fgjp - fry) the frequency of the adder 8 frequency. By applying a direct or inverse sequence of reference pulses to a coincidence circuit, it is possible to select conversion conditions in frequency adder 8. Setting the PLL to the mirror frequency corresponds to the coincidence of the three input signals: the potential corresponding to the logical unit, the reference pulse sequence (fft) (fig.2b), short pulses from the feedback circuit (fot (fig.2g) and signal synchronization indication, the equality of which to the potential of the logical unit corresponds to the synchronization mode of the PLL device. When all three signals coincide in the setting indicator 11, the Reset signal of the search block 5 is generated, at which the output frequency oscillator 6 and changes in the right direction. The fulfillment of conditions (b) is controlled by the discriminators of the 16th sign of the part whose inputs receive the oscillations of all adders, beginning with the second, the frequency of the path 7, except the first, and at the output A signal equal to the potential of the logical unit is generated if condition (b) is not fulfilled, which means that in the false synchronization mode of the device, when the output of at least one frequency adder 8 is mirrored, the search unit 5 will fail. From the principle of operation it follows that if there is only one adder 8 of frequency in the path 7, the indicator 11 of the setting must be made as a single element AND, the output of which is connected to the search block 5. Thus, the proposed device provides reliable protection against false settings of the PLL ring on the mirror frequencies by introducing the tuning indicator and pulse formers. % Formula isb, retenta Phase-locked loop device containing a source connected in series :, a frequency reference, a phase shifter, a phase detector, a low pass filter, a search unit, a controlled oscillator and a frequency converters connected in steps + 1 of frequency adders the output of which is connected to the second input of the phase detector, and the second inputs of the frequency adders are connected to a source of auxiliary frequencies, characterized in that, in order to eliminate false settings, it is entered setting knob made as a series-connected AND element and an OR element, as well as n frequency sign discriminators, the inputs of each of which are connected to the inputs of each of Cn + 1) -th frequency adders, starting from the second, and between the output of each frequency sign discriminator and the corresponding input of the OR element is an additional AND element, the first pulse shaper connected between the output of the frequency conversion path and the first input of the AND element, and the second pulse shaper connected between the output the reference frequency source and the second input of the AND element, while the third input of the AND element and other inputs of the additional AND elements are connected to the output of the synchronism indicator, and the output of the OR element is connected to the control input of the posk block. “,  1-I GP