SU1265776A1 - Device for checking programs - Google Patents

Abstract

The invention relates to computing and can be used in hardware and hybrid monitors to count the frequency of occurrences of events belonging to several classes, in particular, to obtain statistical characteristics of the operation of programs. The purpose of the invention is to reduce the hardware cost of the implementation of the memory block. The device contains two memory blocks, a register, a mode, a data register, three multiplexers, three OR elements, a command usage counter, a base address counter, a NOT element, three AND elements, and a trigger trigger. , microinstructions counter, descrambler, two triggers of the switches, register of the base, overflow trigger, record trigger, adder. 1 il. (L with

Description

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about ate

One I1 The invention relates to computing and can be used in hardware and hybrid monitors to count the frequency of occurrence of events belonging to several KIM classes, in particular, to obtain statistical characteristics of the programs. The aim of the invention is to reduce the hardware cost of implementing a memory block. The drawing shows a diagram of a device for controlling program control. The device contains blocks 1 and 2 of memory, register 3 modes, data register 4, first 5, third 6 and second 7 multiplexers, third 8, second 9 and first 10 elements OR, command use counter 11 , the base address counter 12, the element is NOT 13, the first one is 14, the second 15 and the third 16 are And, the trigger 17 is started, the counter is 18 microinstructions, the decoder 19, the trigger 20 and 21 are read, the register 22 is base, the overflow trigger 23, the trigger ger 24 records, adder 25, group of information inputs 26, group of inputs 27 event tags, input 28 entries, an input 29 of the event slump attribute, a clock input 30 and a group of information outputs 31, Memory block 1 is designed to store the results of counting the frequency of command use, It has a capacity of 2-bit words, where k is the number of bits in the code operations; 2 - the number of zones into which the memory block 1 is divided, and that p. To store the result of the counting of commands with the operation code UK, i 2 i 1, in block 1 of the memory, cells are allocated that have addresses b - ,, , B2 s OL.K,., O. 2a1 (btr ,,,, b2b1-sd address of the zone; jk to ... a 2a1 to the discharge opcode that is used to address the cells of memory block 1 within each zone), and the lower-order bits of the result are stored in the cell having the address О ,,, ОО-к ... а 2а1, the following and bits are the B cell, having the address 0 ... 01 dK, ,, and 2а1, and so on to the older and bit who stored in a cell with the address 1 ,,, 11 o..k., cx 2a1. This block allows you to store 2 {-digit counting results, the maximum size of the result determined from the ratio of 1 to 2. Block 2 memory ti pre Classifi- cation for storing bi -bit addresses and additional zones odnorazr dnyh features. It has a capacity of 2 (t + 1) -digit words. The zone address and the sign for a command that has an operation code a to ... a 2a1 are stored in the cell of the 2pam ty block at the address ak ... a2x1. Stored in the memory block 2, the information is of the form bt ... b2b-1 s (C-sign), moreover, if С 0, then bt-n, .. b.2 b 1 is used to address the zone of the memory block 1 if 1, then in block 1 of memory the zero zone is addressed, and the code is br-n,. The 2 bl is added to the contents of the selected cell of the first zone of the G memory block. Register 3 modes sets the device operation mode. The device can operate in two modes: operating mode, with all bits of the register 3 modes must be O, and the Read mode is set to initial setting, the initial setting, while register 3 modes contains information Q.K ... x.2a. I b.t-n.b. 2 1, where QK .. a2a1 is the cell address of memory block 2; Ltn ... b2blQ.KQ2a.l is the cell address of memory block 1. In the operating mode, the device calculates the frequency of use of commands in the program under study. In the read mode with the initial installation, the device reads to the data register 4 the contents of the cells of the 1. And 2 memory cells, whose addresses are determined by the contents of the register 3 modes. This mode is necessary for the initial installation of the device before the beginning of the measurement session and for the output of the results of the counting of the use of commands at the end of the measurement session. The device works as follows. Before starting a measurement session, it is necessary to carry out the initial installation of the device. To do this, the code o, ", ... o. 2, and 1,, bm. ,, Ь 2, b 1; By the signal from input 28 of the record, this code records to register 3 of the mode. This sets the scan mode to initial setup. At that, 1 from the output of the first register register 3 modes enters the control input of the multiplexer 5 and opens it via the second group of inputs, code passes ;, ,, Oi2, Ql from the register 3 modes to the address input groups of the memory block 2 and to the group of lower address inputs of the 1pam unit, to the control input of the multiplexer 6, the signal from the output of the element OR 8 opens multiplexer 6 through the second group of inputs and passes the code а.к.а2а-1 from the register 3 modes to the group of higher address inputs Dov of memory block 1; to the input of counter 11 and through the element OR 9 to the reset input of the counter 12, keeping the counters 11 and 12 in the zero state on the element NOT 13, the zero signal from the output of which closes the element 14. And simultaneously with the recording on the register 3, the positive potential, The input to the first bit of register 3 of the mode enters the first input of the AND 15 element. Under the influence of the signal from the input 28 of the record at the output of the AND 15 element, a positive potential appears, which, having passed through the OR 10 element, establishes the trigger 17. At the inverse code of trigger 17, a zero signal appears that goes to the reset inputs of microcommand counter 18 and decoder 19, unlocking decoder 19 and allowing microcontrol counter 18 to read clock pulses received at its counting input from the clock input 30 of the device. Under the influence of clock pulses at the counting input, the microproject counter 18 forms at its outputs a sequence of eight combinations from 000 to 111. These combinations are decrypted by the decoder 19, the eight outputs of which sequentially appear 1, the signal from the first output of the decoder 19 sets the trigger 20 Squit, from the output of which 1 is fed to the input of the schits of the block of 2pam tees, at the outputs of which information appears, read from the cell having the address ..cx2aJ. The signal from the second output of the decoder 19 is fed to the recording inputs of the register 22 of the base and the counter 12. Information from the outputs of the memory block 2 is recorded at the base register 22 of the base. The contents of counter 12 do not change, as it is maintained in the zero state by a single signal from the output of the element OR 9. The signal from the third output of the decoder 19 sets the overflow trigger 23 and the trigger 21, which is fed to the interface of memory 1 ti. On the output of the memory block 1 information appears, read from a cell having an address ... b 2Y ck. .O.2a1. The signal from the fourth output of the decoder 19 resets the first read trigger 20, enters the write input of data register 4 and writes information from the outputs of memory block 1 and the outputs of base register 22 to it. The outputs of data register 4 are information outputs 31 of the device. In addition, this signal arrives at the input of the record of the counter 11, the contents of which do not change, since it is maintained in the zero state by a single signal from the output of the first register bit 3 of the mode. The signal from the second output of the decoder 19 resets the second trigger 21 to read out and goes to the counting input of the counter 11 without changing its state, since the counter input of this counter is 1. The signal from the sixth output of the decoder 19 sets the trigger 24 for the record, from the output of which 1 is fed to the inputs of the recording of blocks 1 and 2 of memory. In the cell of the memory block 1 having the address b-m., B2b1ac. .a2al, the I-bit code 0 ... 00 is entered, which arrives at the information inputs of memory block 1 from the information outputs of the 1G counter. In the cell of memory block 2, which has the address a.k.a 2a1. the (t + 1) -digit code O ... 01 is written to the information inputs of memory block 2 from the outputs of the counter 12 and the overflow trigger 23. The signal from the seventh output of the decoder 19 is triggered. Trigger 24 records. The signal from the eighth output of the decoder 19 is fed to the reset input of the trigger 17 start. In this case, on the inverse output of the trigger 17 of start-up, 1 appears, which resets the counter of 18 commands and the decoder I9 and podderivaet them in the zero state.

For the initial installation of the device, it is necessary to repeat the described procedure 2 times, changing the information recorded on the register 3 mode from 0 ... 01 to 1 ... 1 1.

To transfer the device to the operating mode, the register 3 modes by a signal from the recording input 28 records the code 0 ... 0, coming from the groups of information inputs 26 of the device. At the same time, O from the output of the first bit of the register of 3 modes is fed to the control input of multiplexer 5, allowing through it to pass the K-bit operation code ac ... from the group of inputs 27 event tags to the group of address inputs of the block, 2 memories and per group of lower address entries block

1 m tee; to the second inputs of the elements OR 8 and 9, allowing passage to

their outputs of signals arriving at the first inputs of these elements; to the reset input of counter 1I, allowing it to react to signals arriving at the recording input and the counting input; on the input element is NOT 13, a single signal from the output of which opens the element And 14.

To the second input of the element 14 from the input 29 of the feature of the device, a signal arrives indicating that an operation code is on the group of inputs 27 of the device. At the output of the element AND 14, 1 appears, which through the element OR 10 sets the trigger 17. A decoder 19 generates a series of eight signals that appear sequentially at its eight outputs.

The signal from the first output of the decoder 19 sets the trigger 20 sch tgeani. At the same time at the outputs of the block

2pam, information of the form b1-g, .. b.2 b 1 sec, read from the cell whose address is the opcode coming from the device group 27 of the device is displayed. with. . a.2al.

The signal from the second output of the descrambler 19 writes the code B.bl.b2b.1 onto the counter 12, and the code 22 of the base register - the code b t.b.2blc. In this case, the sign C from the output of the first bit of the register 22 of the base enters the control input of the multiplexer 7 and through the element OR 8 to the control input of the multiplexer 6. If, then the multiplexers 6 and 7 pass

information on their first groups of inputs. Hence, the group of higher address inputs of memory 1 comes from base register 22, code t, .. 2, which in this case is used to address the memory area, and the output groups of memory 1 are connected to the input groups of counter 11. If then the group of higher address bits of memory 1 comes from mode register code 0 ... 00, the group of inputs of counter 11 is connected to the group of outputs of adder 25.

The signal from the third output of the decoder 19 sets the overflow trigger 23 and the read trigger 2 and enters the second input of the AND element 16, the first input of which receives the sign C from the first output of the memory block 2. If c 1, then at the output of AND 16 appears 1, which passes through the OR 9 element and resets the base counter 12. At the outputs of memory block 1, information appears, either read from the cell with the address 0., .00 Q.K. . Q..2 a. (at C or from the cell with the address L.ch.f. 2Ba .. and 2a1 (with c 0).

The signal from the fourth output of the decoder 19 clears the trigger 20 and writes down to counter 1 or information from the outputs of memory block 1 at с 0, or information from the outputs of adder 25 at), which is the sum of the cb.t .. b2 from the register 22 databases with information read from memory block 1.

The signal from the fifth output of the decoder 19 resets the read trigger 21, and entering the counting input of the counter 11, adds 1 to its contents. If the code 11 on the counter 11 ... P, then adding to it causes the counter to overflow. In this case, the counter 11 is nullified. A signal appears at its output overflow, which resets the overflow trigger 23 and adds 1 to the contents of the counter 12.

Claims (1)

The signal from the sixth output of the decoder 19 sets the trigger 24 record. At the same time, a record is inserted into the previously selected cell of memory block 1. information from the outputs of the counter 1I frequency, and to the previously selected cell of the memory block 2 - information from the outputs of the counter 12 of the base and the trigger 23 overflow. The signal from the seventh output of the decoder 19 resets the trigger 24 records, the Signal from the eighth output of the decoder 19 resets the trigger 17 start. For the device from the measurement results device, it is transferred to the Read with blanking mode. At the same time, the final result of measuring the frequency of occurrence of a command with the operation code Q q., A is 2 o. 1 is programmed as follows. The minor bits of the result are obtained by summing up the contents of the cell of the memory block 1, having the address O,., O, and K,. and 2 Q. 1, with the code bt-n, ,, ь. 2 are read from the memory block 2 at address a. 1c., And 2aL. The following bits of the result are read out and the cells of the memory block 1 at the address O ,, 01 а.к,. a.2 a.1 and so on. Moreover, if the sign is, then to the contents of the cell of memory block 1 having the address b.m.,, Ь. 2 b IQ. to, ,, Q 2 a 1, add 1, 7 Thus, the invention allows to reduce the capacity of the memory necessary for storing f-digit results of counting the frequency of use of commands, since the final result is not obtained by summing the contents of the cells allocated for of this command, and the contents of the cell (1 +) stand - the zones to the left of the contents of the cell of the i -th zone (,,,, 2), Formula of the Invention A device for monitoring programs containing the first memory block, the base register and the command usage counter, group of information outputs The command utilization network is connected to a group of information inputs of the first memory block, characterized in that, in order to reduce hardware costs, a second memory block, a mode register, three multiplexers, three AND elements, a NOT element, three OR elements, and a base counter are entered into the device. addresses, overflow trigger, adder, data register, start trigger, microinstruction counter, descrambler, two read trigger and record trigger with the device’s event tag inputs connected to the first group of information inputs of the first cartoon plekso- Dr. input group setting mode the PA. The device bots are connected to the group of information inputs of the mode register, the device's clock input and the device event sign input are connected to the micro-command counter input and the first input of the first element AND, the device record sign input is connected to the first input of the second element and the record input of the mode register, the input of the attribute of the group of inputs of the device mode setting is connected to the second input of the second element AND, the output of which is connected to the first input of the first element OR, the output The mode of the mode register is connected to the control "input of the first multiplexer, to the first inputs of the second and third OR elements, to the input of the initial installation of the command use counter, and through the element to the second input of the first AND element, whose input is connected to the second input of the first OR element, output which is connected to a single trigger trigger input, the inverse output of which is connected to the microcommand counting counter input and to the decoder decryption enable input, information outputs of the counter m of the crocs are connected to the information inputs of the decoder, the first output of which is connected to the single input of the first read trigger, the direct output of which is connected to the read input of the second memory block, the second output of the decoder is connected to the inputs of the register and counter of the base address, the third output of the decoder is connected to the single the input of the second read trigger, the first input of the third element X are the unit inputs of the overflow trigger, the fourth output of the decoder is connected to the zero input of the first trigger, shani, with inputs data register and using the program counter, a fifth vghod decoder connected to the zero input of the second flip-flop schitshani, with the counting input of using the counter commands, sixth, seventh and eighth vkody depshfratora connected respectively to edinichny input triggb-ra recording zero the recording trigger input and the start trigger trigger input, n 5 my recording trigger output is connected to the recording inputs of the first and second memory blocks, the direct output of the second T of the truncher of the schichshan is connected to the input of the schishshan the first memory block, the group of information outputs of the second memory block is connected to the group of information inputs of the counter of the base address and the base register, the group of information outputs of the counter of the base address is connected to the group of information inputs of the second memory block, the group of information outputs of the first multiplexer is connected to the group of address inputs the second memory block, with the second group address-. The first bits of the base register are connected to the second input of the third element OR, to the control input of the second multiplexer and information input of the data register, whose information outputs are information outputs of the device, the group of information outputs of the first memory block is connected to a group of inputs of the first operand days of the matrix, with the first group of information inputs of the data register and with the first group of information inputs of the second multiplexer, a group of information outputs p the base hub is connected to the first group of information inputs of the third multiplexer, the second group of information inputs of the data register and the group of inputs of the second operand of the adder, the result output group of which is connected to the second group of information inputs of the second switch, the information output group of which is connected to the group of information inputs of the command usage counter the overflow output of which is connected to the zero input of the overflow trigger and the counting input of the base address counter, perv the group of information outputs of the mode register is connected to the second group of information inputs of the first multiplexer, the second group of information outputs of the mode register is connected to the second group of information inputs of the third multiplexer, the group of information outputs of which is connected to the first group of address inputs of the first information block the outputs of the first memory block are connected to the second input of the third element I, the output of which is connected to the second input of the second element And, the output of which is connected to the initial setup input of the base address counter, the direct output of the overflow trigger is connected to the information input of the second memory block, the output of the third OR element is connected to the control input of the third multiplexer.