SU1262507A1 - Device for generating test sequence - Google Patents

Abstract

The invention relates to computing technology, in particular, to automatic test synthesis devices for monitoring performance and troubleshooting digital objects based on microprocessors. The aim of the invention is to improve the speed of the device. The goal is achieved by introducing into the device a pulse generator, a divider, a trigger, an AND element, a gating pulse shaper, an OR OR NOT element, an OR element, a NOT element, n memory blocks, two groups of n shift registers, a group of n multiplexers. The issuance of information on the output bus begins with the registers of the first group, and ends with the issuance of information from the registers of the second group. 2 Il.

Description

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The invention relates to computing and, in particular, to automatic test synthesis devices for monitoring performance and troubleshooting complex digital objects based on microprocessors.

The aim of the invention is to increase the str of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagram of the device.

The device contains an address counter 1, n memory blocks, the first Sj. -3ts and second 4i -4l groups of shift registers, multiplexers group 5j-5p, clock generator b, divider 7, shaper pulse generator 8, HE element 9, two elements OR NOT HE, 11, element AND 12, element OR 13 , trigger 14, input 15, set device mode, outputs 16 | -IGri and test sequence, input 17 set initial conditions.

The device works as follows .30

The signals from the input 17 setting the initial conditions are fed to the inputs of the address 1 counter and the memory blocks 2 of the group.

The data written to the address counter 1 is gated with the leading edge of the strobe signal, and the data written to the memory blocks is gated with the AM / CT signals and, where ... n. The first of these signals, the zero value, determines the recording mode; the second one, the procedure itself is written to one of the selected i memory blocks. The clock pulse generator 6 generates signals with a frequency twice as high as the frequency of changing information on the output word bus, since the shift of information in registers 3 and 4 of shift and the change of output information are carried out on the leading edge of the synchronous pulses. The signals of the clock pulses from the output of the generator 6 are fed to the input of the divider 7 and to the inputs of the elements OR-NOT 10 and 11, which form the shift signal, respectively, of the first 4 and second 5 shift registers. The signal of the divider 7 (Fig. 2) gates the clock shift signals on the OR-NOT 10 and 11 elements, and in the first half of the period of the signal at the output of the divider 7, the sync signals are allowed to be generated on the output of the ILINE 10 element, and the second on the output of the OR-NOT 11 element. This corresponds to the alternate operation of the first and second registers 3 and 4 of the shift.

The shaper 8 gates 1, their pulses are formed by recording gates in shift registers 3 and 4 (Fig. 2), with the strobe writing to the shift registers 4 of the second group on the secondary front of the input signal, and strobe writing to the shift registers of the first group on back. Thus, writing parallel information

from memory blocks to that shift register, which in this half-period of the signal (from the output of divider 7) does not shift. Multiplexers 5j (-5p groups are controlled by an inverse signal from the output of divider 7, and by themselves passing to outputs 16 first the information of the shift registers of the first group, and then of the shift registers of the second group.

At the initial moment, the value of the signal at the input 15 of the device is zero, the trigger 14 is set to zero, thereby prohibiting the passage of the generalized signal from the driver 8 through the elements OR 13 and AND 12 to the counting input of the address counter. The signal from the output of the trigger 14 also prohibits the operation of the registers 3 and 4 of the shift mode shift. When a signal of the logical unit arrives at the input of the device 15, the trigger 14 at the leading edge of the signal coming from the output of the divider 7 is set to a high level, allowing

alternating shift registers and adding one to the address 1 counter after each entry: either in shift registers 3j-3, or in shift registers 4-4 by shift. The output of information to the output 16 begins with the issuance of information from the registers 3-Zn, and ends with the issuance of information from the registers 4j: -4 shift, since the trigger 14 is clocked by the leading edge from the divider 7.

Claims (1)

Invention Formula A device for generating a test sequence containing an address counter, the information input of which is the input of setting the initial conditions of the device, characterized in that, in order to improve speed, the gating pulse former, divider, trigger, oscillator of commercial pulses are entered into the device, two an OR-NOT element, an OR element, an NOT element, an AND element, a group of n memory blocks, two groups of n register-in shift, a group of n multiplexers, with the output of the clock generator connected to the clock the deluxe input and with the first inputs of the ILINE, the output of the divider is connected to the input of the gate stator gates, the second input of the first OR-NOT element, the trigger synchronous input and through the element NOT with the control, the multiplexer inputs group and the second input of the second element OR NOT, the first and second information inputs of the multiplexers of the group are connected respectively to the outputs of the shift registers of the first and second groups, the shift resolution inputs of which are connected respectively to the outputs of the first and second elements OR NOT, the first and second outputs of the gating pulse generator are connected respectively to the inputs enable the recording of the shift registers of the first and second groups and the first and second inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is combined with the inputs recording prohibition of shift registers of the first and second groups and connected to a direct output of flip-flop having an information input coupled to an input specifying device mode. the information inputs of the group memory units are connected to the input of setting the initial conditions of the device, the outputs of the group memory blocks are connected to the information inputs of the shift registers of the first and second groups, the counting input of the address counter is connected to the output of the And element, the output of the address counter is connected to the address inputs of the memory blocks the groups, the outputs of the group multiplexers are the outputs of the device test sequence. / 7 With 5 l 6 S5 l.7 with 5 l. Yugigschlgggitgish lJlllLJlJlJglJlLJggLGLLJlLJJJJJ Jl gpJlJlJlJlJlJirLTLTLrL LLLR