SU1261082A1 - Ternary bridge-type flip-flop - Google Patents

Abstract

The invention relates to a pulse technique, in particular to devices with three stable states. The purpose of the invention — an increase in the efficiency and speed of a three-way bridge trigger — is achieved by decreasing; neither the voltage drop in the output circuits of the trigger and the possibility of switching its states in any order. To achieve this goal, two two-collector transistors of the first conductivity type were additionally introduced into it: pos. 22 and 23. In addition, the trigger contains transistors 7, 8, 9, 15 and 16, three inputs 1, 2 and 3, outputs 4 and 5, resistors. By applying positive pulses to the inputs, the trigger switches to one of three stable states, regardless of the previous state. 1 tt. f

Description

The invention relates to a pulse technique, namely to devices with three stable states.

The purpose of the invention is to increase the efficiency and speed of a ternary bridge trigger by reducing the voltage drop in the output circuit of the trigger and making it possible to switch its states in an arbitrary order.

The drawing shows the electrical circuit of the proposed three-way bridge trigger

The ternary bridge trigger contains three inputs 1,2,3 and two outputs 4, 5, between which load 6 includes three transistors 7, 8, 9 of the first conductivity type, the emitters of which are connected; , 12 are connected to the bases of the first, second, third transistors 7, 8, 9, the base of the first transistor 7 is connected to the first input 1, and the first and second collectors are connected to the bases of the second and third transistors B, 9, respectively, the collectors of which are connected respectively - | Twisted and fifth resistors 13, 14 with b the fourth and fifth transistors 15, 16 of the second conductivity type, which respectively through the sixth and seventh resistors 17, 18 are connected to the power bus 19 and the emitters of the fourth and fifth transistors 15, 16, the collectors of which are connected respectively through the eighth and nine The second resistors 20, 21 with the bases of the second and third transistors 8, 9, the emitters of the sixth and seventh transistors 22, 23 are connected to a common bus and through the tenth and eleventh resistors 24, 25 are connected respectively to the bases of the sixth and seventh transistors 22 23, first calls The quads of which are connected respectively to the first and second collectors of the first transistor 7, and the second collectors are connected respectively to the collectors of the third and second transistors 9, 8, the additional collectors of which are connected respectively to the additional collectors of the fourth and fifth transistors 15, 16 respectively to the second and first outlets out 5.4.

The ternary bridge trigger works as follows.

five

0 5 0 5 0 5

0

When the power is turned on, all the transistors of the bridge ternary trigger are closed, at the outputs 4, 5 equal potentials and current in the load 6 is absent. The trigger is in the first steady state, with the power source being powered from the power source, no energy is consumed.

If a positive pulse arrives at the second input 2, the sixth transistor 22 opens and enters us (the current of the second collector of the sixth, transistor 22 through the fifth resistor 14 opens the fifth transistor 16. The potential at the first output 4 increases due to the additional current collector of the fifth transistor 16. The collector current of the fifth transistor 16 through the ninth resistor 21 opens and pushes the third transistor 9, and the potential at the second output decreases. There will be current through the load 6 in the direction from the first output to the second. The end of the pulse at the second output 2 of the sixth transistor 17 is closed, but the potential at its second collector does not increase, since the third transistor 9 is open and current flows through its collector. The three-way bridge trigger is in the second steady state, in which the fifth and third transistors 16 and 9 are open, while the second and fourth transistors 8 and 15 are closed. At the first output they are high and at the second low potentials.

If at this moment a positive pulse arrives at the third input 3, the seventh transistor 23 opens and enters the saturation. The first collector current of the seventh transistor 23 shunts the base current of the third transistor 9 and the latter closes. This leads to a decrease in the collector current to the third transistor 9 and the closing of the fifth transistor 16. At the same time, due to the current of the second collector of the seventh transistor 23, which flows through the quad resistor 13, the fourth transistor 15 opens and enters, which increases potential at the second exit. The collector current of the fourth transistor 15, flowed through the eighth resistor 20, opens and saturates the second transistor 8. Potential

on the first exit decreases. The current through the load 6 reverses direction. After the end of the pulse at the third input 3, the seventh transistor 23 closes, however the low potential at its second collector does not change, since the second transistor 8 is open and saturated and current flows through its collector. The trigger is in the third stable state, in which the second and fourth transistors 8 and 15 are open, the third and fifth transistors 9 and 16 are closed. At the first exit low, at the second exit high potentials.

If a positive pulse arrives at the first input, then the first transistor 7 opens and enters its current. The currents of its collectors shunt the currents of the bases of the second and third transistors 8 and 9, which causes both of them to close regardless of the previous trigger state. Reduce the formula of the invention

ten

t5

20

A triple bridge trigger containing three inputs and two outputs, the load of which is connected, three transistors of the first conductivity type, the emitters of which are connected to the secondary bus and through the corresponding three resistors connected to the bases of the first, second and third transistors, the base of the first transistor the first and second collectors are connected to the bases of the second and third transistors, respectively, whose collectors are connected through the fourth and fifth resistors with the bases of the fourth and fifth transistors the second of type conductivity, respectively, through which the sixth and seventh resistors connected to the power bus and the emitters of the fourth and fifth tran ican, whose collectors are respectively connected through the eighth and

shuffled to zero collector currents of the second 25 ninth resistors with bases of the second

and the third transistors 8 and 9, which leads to the closing of the fifth and fourth transistors 16 and 15 and the switching of the ternary bridge trigger to the first stable state independently of the previous one. After the end of the pulse at the first input, the first transistor 7 is closed.

If the trigger is in the third steady state and a positive pulse arrives at the second input 2, the trigger switches to the second steady state similarly to the described switching from the second steady state to third due to the symmetry of the device.

Thus, by applying positive pulses to the inputs 1,2,3

the trigger switches to one of the three 5 first w outputs, the bases of the sixth and seventh stable states, regardless of the previous state.

Our transistors are connected to the second and third inputs respectively.

Editor N.Shvydka

Compiled by A. Yanov Tehred M. Khodanych

Order 5243/56 Circulation 816 Subscription

VNIZhSH State Committee of the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

Formula of the invention

A triple bridge trigger containing three inputs and two outputs, between which the load is connected, three transistors of the first conductivity type, the emitters of which are connected to the common bus and through the corresponding three resistors are connected to the bases of the first, second and third transistors, the base of the first transistor is connected to the first input and the first and second collectors are connected to the bases of the second and third transistors, respectively, whose collectors are connected via the fourth and fifth resistors respectively to the bases of the fourth and fifth ranzistorov second conductivity type, respectively, through which the sixth and seventh rezis. tori are connected to the power bus and emitters of the fourth and fifth transistors, the collectors of which are connected respectively via the eighth and

ninth resistors with second bases

and the third transistor, characterized in that, in order to improve efficiency and speed, the sixth and seventh transistors of the first conductivity type are introduced into it, the emitters of which are connected to a common bus and through the tenth and eleventh resistors are connected respectively to the bases of the sixth and seventh transistors, The first collectors of which are connected respectively to the first and second collectors of the first transistor, and the second collectors are connected respectively to the collectors of the third and second transistors, additional collectors cat ryh connected respectively with additional collectors Chegbertogo and fifth transistors respectively and a second and

first exit w, base sixth and seventh

Our transistors are connected to the second and third inputs respectively.

Proofreader A.Zimokosov

Claims (1)

A trinity bridge holding three inputs and with which a transistor of the first type of conductivity is connected, emitters of which are connected to a common bus and connected to the bases of the first, second and third transistors through the corresponding three resistors, the base of the first transistor is connected to the first input, and the first and second collectors are connected to bases of the second and third transistors, respectively, the collectors of which are connected respectively through the fourth and fifth resistors to the bases of the fourth and fifth transistors of the second type of conductivity, which respectively, through the sixth and seventh resistors, they are connected to the power bus and emitters of the fourth and fifth transistors, the collectors of which are connected respectively through the eighth and ninth resistors to the bases of the second and third transistors, characterized in that, in order to increase the efficiency and speed, it introduced the sixth and seventh transistors of the first type of conductivity, the emitters of which are connected to a common bus and through the tenth and eleventh resistors are connected respectively to the bases of the sixth and seventh transistors, the first the lecturers of which are connected respectively to the first and second collectors of the first transistor, and the second collectors are connected respectively to the collectors of the third and second transistors, the additional collectors of which are connected respectively to the additional collectors of the fourth and fifth transistors and, respectively, with the second first outputs, the bases of the sixth and seventh transistors are connected respectively with second and third entrances.