SU1672526A1 - Address decoder - Google Patents

Abstract

The invention relates to high-speed logic circuits, namely, decoders, and can be used in computing devices and automation. The aim of the invention is to improve the speed of the decoder. This goal is achieved by introducing the address of diodes 6 with corresponding connections into the decoder. Diodes 6 together with resistors 5 form the elements And, and the current switches on transistors 2, 4 and resistors 5 - elements OR NOT. The signals to the inputs of the elements can be fed without inversion. This avoids the delay of the input signal when inverting. 1 il.

Description

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The invention relates to high-speed logic circuits and semiconductor technology and can be used in computing devices and automation devices.

The aim of the invention is to improve the speed of the decoder.

The drawing shows an electrical circuit of the decoder on four outputs.

The decoder contains cells 1, consisting of reference transistors 2, current sources 3, key transistors 4, resistors 5, diodes 6, zero potential bus 7, outputs 8. power bus 9, reference bus 10, inputs 11.

1 the address decoder works as follows.

When one of the combinations of address word bits is applied to the outputs 11 at the bases of the key transistors A and the cathodes of the diodes 6, the corresponding potential levels of the logic signals are set. This leads to the fact that there is one of the cells 1, in which all the key transistors 4 will be locked with a low potential at the bases of these transistors 4 and all the diodes 6 will be locked with a high potential at the cathodes of these diodes 6. For example, with a combination code of 000. ..00 the key transistors 4 will be locked in all the cells 1. Accordingly, the currents of the current sources through the reference transistors 2 are closed in the power line 9. This leads to the fact that all diodes 6 in cells 1 are open, starting from the second, through them the current of the input signal sources will flow into the output nodes, ensuring the potential drop across the resistors. This leads to the fact that at the first exit 8, which corresponds to the first cell 1, a high potential is established, and at all other outlets - a low potential.

With a Kodopa, combinations 111 ... 111 will open: key transistors 4, respectively, the current of current sources 3, flow through them, will ensure the potential drop across resistors 5, and all are locked

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Claims (1)

diodes 6 which lead to the establishment of a high potential at the last output 8 of the address decoder. In the case of intermediate values of the address word bit combinations, there is one cell 1 in which the key transistors 4 are locked, respectively, the current source 3 through the reference transistor 2 is closed , and the diodes 6 will be locked, which will lead to a high potential at this output 8 and to low potential levels at all other outputs 8. Claims of the invention Address decoder containing cells each of which e the latter consists of a current source, a load resistor, a reference transistor, key transistors, the emigres of which are connected to the first output of the current source and the emitter of the reference transistor, and the collectors to the first output of the load resistor, the last cell contains a load resistor, the second terminals of the load resistors of all cells and the collectors of the reference transistors and is connected to the power bus of the decoder, the second terminals of the source are connected to the zero potential bus Forces of the current and, to the reference bus, the bases of the reference transistors, the outputs of the decoder are the first terminals of the load resistors of the cells of the decoder, the bases of the corresponding key transistors of the cells of the decoder 5 from 20-1) + 2m (2 | -1) are combined m input of the decoder, where 1 j 2P; 1 I n: n is the width of the input of the decoder, characterized in that, p. in order to improve the performance of the address decoder, each cell, besides the first, contains diodes, the anodes of which are connected to the first output of the load resistor, the cathodes of the corresponding diodes five 0 0 1-1 ,one Decoder cells with (2J-1) -2 + 1} th to 2 5 j-th are connected to the 1st input of the decoder.