SU1260974A1 - Device for checking electric parameters of digital units - Google Patents

Abstract

The invention relates to a control and measuring technique and can be used to monitor electrical parameters and diagnose malfunctions of digital nodes. The purpose of the invention is to expand the functionality of the device by providing monitoring and diagnostics of digital nodes at a real clock frequency, in real time, and by conducting two-threshold level monitoring at any of the outputs of the digital node being monitored. The device contains a calculator, interface unit, input / output unit, decoder unit, meter unit, programmable power supply unit, diagnostic unit, analysis unit, address controller matching units, fault identification unit, first and second digital-to-analog converters, register unit. Each matching node contains a switch, an element OR, a counting trigger, an analog key, a comparator, an AND element, a test memory register, a digital-analog converter, a fault recorder, and a block of settings. The diagnostic block contains the output address register and the multiplexer. The analysis block contains a signature signaling device, the signature register of the faulty contact, the diagnostic signature register, the comparison element. Introduction to the device controller address, fault identification block, two digital-to-analog converters, block registers block. decoders, and in each node matching the malfunction recorder with the appropriate external connections, the device speeds up during dynamic testing of digital synchronous and async-gry circuits by 20–30 times, which ensured testing of this class of circuits at real clock frequency, and It also allowed the organization of an admissible parametric control of the signals of the reaction of control objects, which are fixed analog levels of complex shape, the assessment of the validity of which turned out to be possible oizvodit parallel to all outputs of the control object Uon criterion; Up; - Upn, -, where and the permissible lower and upper limits of the controlled analog level at the i-th controlled output. Connecting the information codes of the signature analyzer with the information input of the interface unit, as well as the clocked input of the signature analyzer with the gate output of the address controller, made it possible to organize diagnostics of digital faults (L

Description

126U974 synchronous and asynchronous circuits on the localization of the fault location and

tal clock frequency in an interactive mode with the operator

identifying its type. 8 hp oh o silt

i The invention relates to a control: measuring technique and can be used to monitor electrical parameters and diagnose digital malfunctions. knots.

The purpose of the invention is to expand the functionality of the device by providing real-time monitoring and diagnostics of digital nodes at a real clock frequency and conducting double-threshold level monitoring at any of the conclusions of the digital node being monitored.

FIG. 1 shows a block diagram of a device for controlling electrically the parameters of digital nodes; in fig. 2 is an address controller circuit; in fig. 3 is a diagram of a fault identification block; in fig. 4 - scheme of the fault recorder; in fig. 5 is a diagram of a test memory block; in fig. 6 is a block register diagram; in fig. 7 is a block diagram of settings; in fig. 8 is a signature analyzer circuit; in fig. 9 is a block diagram of decoders; Kah FIG. 10 is a time diagram of the operation of the address controller in the mode of dynamic testing of digital asynchronous and synchronous circuits in real time.

The device contains calculator I, interface 2 block, input-output block 3, decoder block 4, meter block 5, block 6 of programmable power sources, diagnostics block 7, analysis block 8, nodes 9.1-9. 10 addresses, fault identification block 11, first 12 and second 13 digital-to-analog converters (D / A converters), register block 14, fifth 15, fourth 16, third 17 outputs of the controller 10 addresses, fourth input 18, third 19 and fourth fourth outputs of the fault identification block 11 , address 21 and informational 22 outputs of block 2

4 localization of the fault location and

identifying its type. 8 hp f-ly, About silt.

interfaces, the first 23, the second 24, the fifth 25, the third 26, the seventh 27, the seventh 28, the eleventh 29 and the twelfth 30 outputs of the block 4 of the decoders.

Each node 9.1-9. The matching unit consists of a switch 31, the first element OR 32, a counting trigger 33, an analog switch 34, a comparator 35, the first element AND 36, a test memory block 37, a first DAC 38, a fault recorder 39 and a block 40 settings.

Block 7 diagnostics form the register 41 addresses of the outputs and the multiplexer 42.

The analysis unit 8 has a signature analyzer 43, a register 44 of the signature of the faulty contact, a register 45

diagnostic signatures and reference element 46.

The address controller 10 contains the second 47, the first 48, the fourth 49 and the third 50 binary counters, the first pulse generator 51, the first storage register 52, the first 53, the second 54, the third 55, the fourth 56, the fifth 57 and the sixth 58 triggers, AND elements 59.1-59.k, third 60, fifth and 61

the fourth 62 elements And, the fourth 63, the third 64 and the second 65 elements OR, and the generator 66 of single pulses.

The fault identification unit 11 consists of the seventh trigger 67, the second pulse generator 68, the second double counter 69, the first positional decoder 70, the sixth element SHIII 71 and the fifth elements OR 72.I-72.N.

The fault recorder 39 forms the eighth trigger 73, the sixth 74, the seventh 75, the eighth 76, and the virgins. Tty 77 elements I.

The test memory block 37 includes a storage matrix register 78 and a seventh element OR 79.

 Block 14 of thy 80 and storage.

Block. 40 register 82

registers consists of the third of the 81 registers

settings contains second storage, ninth 83, tenth 84, eleventh 85 and twelfth 86 triggers, eleventh 87, twelfth 88, thirteenth 89, fourteenth 90, fifteenth 91 and sixteenth 92 elements I.

The signature analyzer 43 contains a 16-bit shift register 93 and an adder 94 modulo two.

Block 4 of decoders contains the third 95, fourth 96, second 97, fifth 98, sixth 99, seventh 100, eighth 101 and ninth 102 positional decoders.

The control object 103 is connected to the device input-outputs.

The device operates in the following modes:

1. Functional dynamic checking of Digital Asynchronous and Synchronous Circuits on a real clock frequency using the Goden-Not-Fit method.

2. Diagnostics of malfunctions of digital asynchronous and synchronous circuits at real clock frequency.

3. Functional statistical testing by the Go-no-use method and diagnostics of faults in digital-analog circuits.

4. Functional static testing by the Go-no-use method and troubleshooting of digital-analog circuits.

The device in the mode of functional dynamic testing of digital asynchronous and synchronous circuits at a real clock frequency according to the Goden-not-Goden method works as follows. .

Using the keyboard of the I / O unit 3, the operator sets the mode for loading the initial information into the RAM of calculator 1, while the program for checking the selected control object 03 stored on the external medium of I / O unit 3 is inserted into the RAM of calculator 1 via block 2 mate After entering the initial information, the calculator 1, in accordance with the entered program, starts programming the device blocks, and from the outputs 22 and 21 of the block 2, the interfaces are input to the block

ten

t

 5 20

25

2609744

4 decoders information, address and strobe signals. Block 4 of the decoders converts information signals (control codes with the digit number of the calculator I computer) at the corresponding addresses into control signals that prepare the device blocks for operation and control their operation during the control operations. The sequence of control commands in each operation mode is determined by the operation algorithm. First, the test memory block 37 and the setting block 40 in the matching 9.1 matching nodes, as well as the register block 14, the programmable power supply unit 6 and the address controller 10 are prepared for operation.

The test memory block 37 of each matching node 9.1 contains in its composition the matrix storage register 78, which is a random-access random access memory (RAM),

P

thirty

35

40 I

45

50

55

with the organization of a memory of b2 bits, which serve to store information about test test sequences on one of the inputs and outputs of the object 103 of the control. The information in the storage matrix register 78 is written in an alternating form, i.e. units of memory are written to the bits of the memory with the addresses corresponding to the numbers of the test sets on which the state change should occur, the remaining cells should remain in the zero state. Recording test information; in the form of alternating signs, significantly reduces the number of control commands when programming the test memory block 37. The programming of the test memory block 37 begins with memory zeroing. On the Reset command, all counters, registers, and triggers of the device, except for the matrix storage registers 78 (in memory test blocks 37.i), storage registers 80 and 81 (register registers 14), and storage registers 82 (settings blocks 40.i) initial (zero) states. One of the commands Set 1..1.1. To the register 52 of the controller 10 address selects the frequency of the starting pulse of the measuring pulse generator assembled on the counter 50 and the elements AND 60-62 and OR 65. The pulse frequency

the start is selected when preparing the control program in such a way that the measuring pulses have a following frequency of 5 close to the real clock frequency of the control object 103. By the command Zap.O, the trigger 55 (in the controller 0 addresses) is set to one state at the address inputs Id-A, information inputs D1,

The inputs for writing V read WE and the inputs for selecting the CE matrix storage registers 78 (test memory blocks 37) of all nodes 9.1 matching present O levels, since the outputs of counter 49 are 1p-1p addresses, OR 64 element and trigger 58 (controller 1 O) addresses) there are levels O. This state of the inputs of the matrix registers 78 of the registers storage 37. The test memory corresponds to the write mode O in them at the zero address. To reset the storage matrix registers 78 to the entire address field, the Start 1 command is sent to the input of the address controller 10, which sets the trigger 53 to one, and after this command is issued, the calculator 1 goes into interrupt waiting mode. A single signal level from the output of the trigger 53 starts the generator 51 pulses. The pulses from the output; of the generator 51 are fed to the counting input of the counter 47, which forms at its outputs a grid of frequencies of the trigger pulses, which arrive at the first inputs of the And 59.1-59.K elements. One of the And 59.1-59.K elements, at the input of which there is a single signal level from the previously programmed storage register 52 passes at its output pulses of a selected tracking frequency, which through the OR element 63 arrive at the counting input of the counter 50 and at the first inputs of the And 61-63 elements of the measuring pulse former, of measuring SI pulses counting. and the Strobe is formed with in accordance with the timing diagram shown in FIG. ten.

From the output of the element And 62 signal Strobe through the element OR 65 is fed to the input of the generator 66 single pulses, which on the rising edge of the signal Strobe produces a Polling signal arriving at the first sum 20

25

thirty

35 jg

2609746

The counting input of counter 49 is addressed and the number of addresses of count 48 is subtracted by the counting input of counter.

The address counter 49 with the selected frequency gives out successively increasing address codes to the inputs of the storage matrix registers 78 (test memory blocks 37) of all matching nodes 9, written to them at these addresses by zeros. Since the counters 48 and 49 are of the same size, after the last address code is added, a pulse appears at the transfer output of the counter 48, which sets the trigger 53 to the zero state, and, arriving at the second interrupt input of the calculator 1, signals the end resetting the registers of the 37 memory test for the entire address field. In this case, the pulse generator 51 stops producing pulses, and both counters 48 and 49 remain in the zero state.

If it is necessary to reset the test memory blocks 37 not on the entire address field, but on some part of them, then before submitting the Record O and Start 1 commands using the commands Set.3.3.p and Set.2..2 set

in counter 49, the starting address for zeroing the test memory blocks 37, and in

counter 48 is the required number of addresses where it is necessary to reset the test memory blocks 37. As for the rest, the zeroing algorithm of the test memory blocks 37 is similar to the one presented above.

Then, the unit is written (sign-transferred) to the test memory blocks 37 in accordance with the required test program. By commands Reset dir. and Zap. G in the controller 10 of the address, the trigger 57 is set to the zero state, and the trigger 58 is set to one. Unlike the zeroing mode, the information inputs D 1 and the inputs for selecting the CE matrix registers 78 for storing the memory registers 37 of the test of all matching blocks 9 contain levels 1.

The presence of a cynical level at the inputs of the CE selection and the low level at the input Write-read VVH corresponds to the unselected state of the storage matrix registers 78 in recording mode, while their outputs are in the third high-impedance state and the previously recorded information is stored7

Kom in this case, zeros for all addresses After that, in the controller, 10 addresses by commands, Const.3. G-Set ZP program sets the address of the first test set of the required test sequence and sequentially serves

.informational commands for those 9.1 negotiation blocks in which a record is needed on the given test set

generation of stimulating signals, and output signals by monitoring reaction signals, while block 5 of the meters can parametrically control the output signals of object 103 of the control unit DAC 38 converts the codes of binary numbers supplied to its information outputs from the block 40 of settings to

place units (alternating signs). Informa - Q log levels of input signals

and. in for analog key 34 and in

The command commands arrive at the inputs of the elements OR 79 in the selected test memory blocks 37 at the time of their operation at the inputs CE of the corresponding matrix storage registers 78 there are O levels, and since the information inputs D1 of all matrix registers 78 storage present analog levels of reference reference signals 1 Ugn for comparators 35. DAC 38 programming in input and output nodes 9.1 matching in this mode is carried out once before the start of the test, the signal level 1 can be set in each channel independently mo, what

there is a level

 R

units of data are sequentially recorded in them; this allows you to check control objects performed on elements with different types of logic. Signals Maskir. and Check. Analog., coming from the block 40 of settings to the input to the register address. Upon expiration of the information commands, the matrix registers 78 for storing the test memory blocks 37 (for the selected matching nodes 9.1) go to an unselected 25 fault 39, mask the output of the trigger 73, and set the control mode for the reactions of logic or analog signals. The programming of the block 40 of settings in this mode is 30

state and store previously recorded information, i.e. 1. Then, the test memory blocks 37 are programmed at the next test set, and the Account command is sent to the second count input of the address counter 49, setting the code of the next test set at the output of the address counter 49. The record is known as follows. In the initial state, the triggers 83-86 of the setpoint block 40 are in the zero state, with all the nodes 9.1-9. The matching is masked by the changes at this address carried out -. and are selected as output, block inputs

In the same manner as described in the description of the CIM, blocks of test memory 37 are programmed in all nodes 9.1 matching on the entire required address field (test sets).

Further, according to commands from the block 4 decoders, the blocks 40 are programmed. the settings that determine the state of the elements of the respective matching nodes 9.1, namely the switches 45 31, the D / A converter 38 and the fault recorders 39.

Depending on the control signal Connecting the inputs from the installation unit 40, the switch 31 connects the output of the analog switch 34 and the signal input of the comparator 35 to the object I03 control contact, and the signal Meas. To this pin 55 is connected the input of the block 5 meters. Accordingly, this node 9.1 matching is an input, the meter 5 is disconnected from the contacts of the control object 103, in the fault recorder 39 the control mode of the reactions of logic signals is set. To select matching units 9.1, connected to the inputs of the control object 103, input 4 is supplied from the Mascir command decoder unit 4. to the address controller 10, whereby the trigger 56 is set to one state and enables the installation of the triggers 83 to one state in blocks 40 of the settings of all the nodes 9.1-9. Approval by information commands. After submitting the set of required commands and the command for selecting the input from the block of 4 decoders, the triggers 84 in the corresponding blocks 40 of the settings are set to one state, selecting these coordination nodes 9.1 as input. All unused nodes 9 matching are selected as input so that in registrars 39

eight

The stimulation signals were generated, and the output signals were monitored by the reaction signals, and the meter block 5 can then perform parametric control of the output signals of the control object 103. DAC 38 converts the codes of binary numbers supplied to its information outputs from the block 40 of the settings in the analog levels of the input signals G

analog levels of reference reference signals 1 Ugn for comparators 35. The DAC 38 programming in the input and output nodes 9.1 matching in this mode is performed once before the start of the test, while the signal level 1 can be set on each channel independently, that

l, performed on elements with different types of logic. Signals Maskir. and Kontrolan., coming from the unit 40 installations to the input of the malfunction recorder 39, mask the trigger output 73 and set the control mode of the reactions of logical or analog signals. Programming a block of 40 settings in this mode is

5 meters are disconnected from the contacts of the control object 103, in the fault recorder 39, the mode of control of the reactions of logic signals is set. To select matching units 9.1, connected to the inputs of the control object 103, input 4 is supplied from the Mascir command decoder unit 4. to the address controller 10, whereby the trigger 56 is set to one state and enables the installation of the triggers 83 to one state in blocks 40 of the settings of all the nodes 9.1-9. Approval by information commands. After submitting the set of required commands and the command for selecting the input from the block of 4 decoders, the triggers 84 in the corresponding blocks 40 of the settings are set to one state, selecting these coordination nodes 9.1 as input. All unused nodes 9 matching are selected as input so that in registrars 39

The fault output trigger 73 (Fig., 4) was blocked by a signal to connect the inputs from the AO block, since this prevents the generation of a signal failure during the identification of faults. After that, the Reset Mask command is given, setting the trigger 83 of all the 40 setpoints to the zero state and the Reset Mode command, setting the

the trigger 56 of the controller 10 addresses to zero state.

To set the preset levels of the DAC 38, the Reset Call command is issued. and the required commands Set.3. Installing W.p. on the installation inputs of the counter 49 of the controller 10 address, the output of which the required code number goes to the information

the inputs of the block 40 settings. If it is necessary to set the same levels of signals at the outputs of the D / A converter 38 of all nodes 9.1-9. Reconciliation, the Set Level 2 command is given, according to which the specified code is written to all the registers 82 of the storage of blocks 40 of the settings of all the nodes 9.1-9. If it is necessary to set different unit levels in the nodes 9.1 matching, upon the command Set Level 1 in the controller 10 of the address, the trigger 55 is set to one, allowing writing the required code to the information registers in the storage registers 82. After that, the required number codes are set alternately in the counter 49 in the same way as described above, the required information commands are sent, and the required number codes defining the given DAC 38 signal level are sequentially entered into the storage registers 82 (setting blocks 40) of the corresponding matching nodes 9.1. a reset command is issued, setting the trigger 55 of the address controller 10 to the zero state. For masking one or several measurement channels of the coordination nodes 9.1, the triggers 83. of the blocks 40 of the settings of the corresponding coordination nodes 9.1 are set to one in the same way as described.

On commands from block 4 debrisors, a block 14 of registers is programmed, which determines the state of the first 12 and second 13 DACs, which set the level of the input

Signal O and. for analotov new keys, ,,, ° whose 34 and the level of reference reference

local IJex signals for comparators 35 of all nodes 9, -9. matching. The storage registers 80 and 81 are programmed by register registers 14 in the same way as storage registers 82 (setting AO blocks), the code of the required number is set by the counter 49 of the address controller 10, and the required code is written to the storage register 80 by the command Zap. Pr.1 and in the storage register 81 for the Ko5 Mand Zap.Rg.2.

On commands from block 4 of decoders, block 6 of programmable power sources is programmed, on the corresponding codes of which, connected to the power cable of control object 103, the required potentials of the supply voltages are set.

Controller 10 is programmed by commands from block 4 decoders.

5 addresses. The commands Set 3 are given. The set of w and set 2..2. P, which set, respectively, at the output of the counter 49, the address of the first test set, and in the counter 48 0 the code of the number of addresses (test sets) at which the dynamic test of the control object 103 is performed, and then the Reset mode. command, which sets the triggers 55-58 to the zero state, while the write-read WE matrix storage registers 73 on all inputs of the test memory 37 have level 1, the CE-level O on gate inputs, and address inputs

five

0

AO-AP

five

the address of the first test set of the required test sequence, which corresponds to the reading mode at the first address of the information previously recorded in the matrix registers 78 of the storage of test memory blocks 37 of all matching nodes 9.1, which from the outputs of the test memory blocks 37 are fed to the inputs of the And 36 elements. This prepares the device units for operation in this test mode. The verification of the control object 103 is carried out by cyclically generating stimulating influences and evaluating its reactions, the monitoring cycle being set by the address controller by measuring pulses Read., SI and Strobe, the frequency of which is set

0

ten

20

storage register 52 and coincides with the operating clock frequency of control object 103. The dynamic testing mode starts on the command Start 1, which sets the trigger 53 of the address controller 10 to one, the pulse generator 51 is started, and at the output of the measuring pulse generator the pulses Read, SI, Strobe begin to form. Momentum Reck. sets the beginning of the control cycle. In all nodes 9.1-9. in the fault recorders 39, the fault triggers 73 are set to one and gates the information received at the inputs of the AND 36 elements from the test memory blocks 37, while the codes of alternating variables recorded in the test memory blocks 37 are the address corresponding to the first test set, through the elements AND 36 and OR 32, arrive at the counting inputs of the flip-flops 33, which transform the change sign into real test signals. Moreover, if the node 9.1 matching is an input, then the test signal from the output of the counting trigger 33 is fed to the control input the equal input of the analog switch 34, which, depending on the input signal level O and 1, passes to the output connected through the switch 31 the input j, the contact of the control object 103, the level O from the DAC 12 or the level 1 from the DAC 38 of this node 9.1 matching. The Read signal determines from its leading edge the feed moment. test signals for information outputs. devices. If the control object 103 is a synchronous digital node, then its sync input is connected to the SI output cont. address roller 10 (for asynchronous circuits, the SI output of the address controller 10 is not used). After arriving at the information inputs of the object 103

the role of reaction signals by the amplitude and time selection method; in this case, any output signal at each control cycle can be rejected 5 both in amplitude and in time of occurrence. Reaction signals (Up) are fed through switches 31 to inputs of comparators 35, which perform amplitude selection by comparing the amplitude of reaction signals.

25

40

45

with reference reference levels of signals I Ug and O UOP, arriving at the inputs of the comparators 35 from the DAC converters 38 and 13, with 1 being at the single output of the comparator 35, if the condition Up UQ is fulfilled, and the level O, if and, and the zero output of the comparator 30 is level 1, if the condition is met, and level O, if. The signals from the single and zero outputs of the comparators 35 are received at each node 9.1 of the matching to the inputs of the fault recorders 39, which, according to the Strobe signal, temporarily select these signals. In this mode, from blocks of 40 settings, levels 0 are fed to the inputs Counter. register-fpaTopoB 39 faults that prohibit the selection of signals on element 75 AND and resolve it on element 76 I. The signals from the outputs of counting triggers 33 determine the level of the reaction signal (O or 1) expected at a given monitoring cycle at each node 9.1 matching , herewith, if the counting trigger 33 is in the single state and at the moment the Strobe signal is active, a level 1 is present at the single output of the comparator 35, a signal appears at the output of the And 74 element, which sets the trigger 73 to the zero state, and counting trigger 33 is at zero tion state and action time strobe signal at the zero output of the comparator 35 is present level 1, on the output of the AND element 76

a signal appears that establishes control of stimulating signals and on

.. .. - trigger 73 to zero state, that

its synchronous input of the SI signal from the controller 10 of the address at the output of the control object 103 with a certain delay appears reaction signals.

in both cases, x corresponds to the correct operation of the specified output of the control object 103 at the given clock cycle.

If there is a zero signal level; Previously programmed as output on single or zero output, the output nodes 9.1 of the matching, subcomparator 35 at the moment of action, the Strobe under the described modes, l, are executed in parallel with the described modes Contra-that can be in case of non-fulfillment

 5 ao j,

0974. 12

the role of reaction signals by the amplitude and time selection method; in this case, any output signal at each control cycle can be rejected 5 both in amplitude and in time of occurrence. Reaction signals (Up) are fed through switches 31 to inputs of comparators 35, which perform amplitude selection by comparing the amplitude of reaction signals.

20

 5 Oh,

five

0

five

with reference reference levels of signals I Ug and O UOP, arriving at the inputs of the comparators 35 from the DAC converters 38 and 13, with 1 being at the single output of the comparator 35, if the condition Up UQ is fulfilled, and the level O, if and, and the zero output of the comparator 30 is level 1, if the condition is met, and level O, if. The signals from the single and zero outputs of the comparators 35 are received at each node 9.1 of the matching to the inputs of the fault recorders 39, which, according to the Strobe signal, temporarily select these signals. In this mode, from blocks of 40 settings, levels 0 are fed to the inputs Counter. register-fpaTopoB 39 faults that prohibit the selection of signals on element 75 AND and resolve it on element 76 I. The signals from the outputs of counting triggers 33 determine the level of the reaction signal (O or 1) expected at a given monitoring cycle at each node 9.1 matching , herewith, if the counting trigger 33 is in the single state and at the moment the Strobe signal is active, a level 1 is present at the single output of the comparator 35, a signal appears at the output of the And 74 element, which sets the trigger 73 to the zero state, and counting trigger 33 is at zero At the zero point of the comparator 35 there is a level 1, and at the output of the element 76

VIA

13

or

or at a large delay of the response signal at the output of the control object 103, element AND 74 or 76 do not generate a reset signal of trigger 73 and it remains in one state, remember the presence of a malfunction (failure) at a given clock cycle at a given control in this node 9.i matching.

For a given frequency of test set delivery, the delay of propagation of reaction signals should be for asynchronous circuits no more than С 1 ,, for synchronous circuits triggered on the leading edge of the clock pulse, no more than o2 and synchronous circuits triggered on the trailing edge of the clock pulse, no more than Z3 ( Fig. 10).

If there are delays in the specification for any output of the control object 103 more than those listed, it is necessary to mask this measurement channel and then implement it

check at a lower frequency. After the 25th input of the pre-convolution transmitter 1, the strobe signal of the address controller 10 issues a Poll signal, which polls the status of the triggers 73 of the malfunction recorders 39 of all the nodes 9.1 matching. The interrogation signal is fed to the first inputs of the OR elements 72.1-72.N of the fault identification unit 11 and from their outputs in parallel is fed to the inputs of the output of the Nk recorders 39 non30

malfunction identification is carried out. At the same time, the calculator 1 goes to the fault finding subroutine — reads the test set number code, which from the output of the counter 49 of the block 10 of the address controller enters through the block 2 of the information input of the numerator 1, triggers the Run 2 command and goes into standby mode b

The health of all nodes is 9.1–9. Team Over

owl If in one or more of the matching nodes 9.1 triggers 73 In the fault recorders 39 are in one state and the node 9.1 matching is not hidden and selected as the output one, then at the time of the signal Polling at the output of the And 74 and 77 nodes of the matching 9.1 Signals fail. Signals Failure from all coordination nodes 9.1 are combined on the AND 71 element of the Fault Identification Unit II, and if there is at least one signal, the Interrupt. 3 signal appears at the output of the And 71 Element, which; in the controller 10, the address sets the trigger 53 to the zero state, prohibits further generation of the measuring pulses, and also enters the third interrupt input of the calculator 1, signifying the presence of a fault on this test set.

14

In the absence of malfunctions on this test set, the signals Fail on the Poll signal are not generated and measuring pulses are generated for the next control cycle, etc., until the control object 103 is checked on the entire field of the test sets. After the arrival of the pulse. Polling on the last test set, the counter 48 of the address controller 10 generates a transfer signal that sets the trigger 53 to the zero state, prohibiting further generation of the measuring pulses, and also goes to the second interrupt input of the calculator 1, signaling the end of the object check 103 control on a given field test kits.

When a malfunction is detected on a test suite after stopping dynamic testing. and the arrival of the signal Interrupt. For the third input of the interrupt computer 1

malfunction identification is carried out. In this case, calculator 1 goes to the fault finding subroutine — reads the test set number code, which from the output of the counter 49 of the block 10 of the address controller enters through block 2 of the information input of the calculator 1, triggers the Start 2 command and enters the interrupt signaling mode. Team Over

start 2 flip-flop 67 of the fault identification block 1I is set to one and starts the pulse generator 68, the signals from which are sent to the counting input of the counter 69. When the code is sequentially increased, the counter 69 signals are generated at the outputs of the positional decoder 70, which through the second inputs of the elements OR 72.1-72.N arrive at the inputs of the elements AND 77 of the fault recorders 39 of the corresponding coordination nodes 9.1. Upon reaching the first non-masked output node 9.1 matching, in which the malfunction recorder 39 has the trigger 73 is in one state, the signal Failure is output at the output of the AND 77 element, and a fault signal is received at the input of the OR 71 element in the result identification block 11, which is set to 15.

tanning the trigger 67 to the zero state, and to the third interrupt input of the calculator I, signaling that the first failed output of the control object 103 is located. After the trigger 67 is set to the zero state, the pulse generator 68 stops producing pulses and the code of the first failed output is recorded in the counter 69. The calculator I reads the code of the first failed output that arrives from the output of counter 69 through the interface 2 to the information input of the calculator 1, and sends the Run 2 command again, with the search for the next failed output and writing its code in calculator 1 is repeated. When writing to the operative memory of the calculator 1, the codes of all the failed outputs of the control object 103 on this test set receive a signal from the output (N + I) of the positional decoder 70, which sets the trigger 67 and the counter 69 to the initial zero state and which is received as the Interrupt signal .4 to the interrupt input of calculator 1, signaling the end of the search for faulty outputs on this test set. After that, the calculator I issues the Run 1 command, sets the trigger 53 of the address controller 10 to one, and the dynamic test of the control object 103 at the real clock frequency is resumed. If there are any failures detected on any test set detected during amplitude and time selection of reaction signals, the cycle of searching for failed outputs is repeated, etc., until the failed outputs are determined over the entire field of test sets.

After completion of the test, the test results are removed from the RAM of the calculator 1 through the interface 2 to the I / O unit 3 for registration and indication, and if no faults were detected in the entire field of the test sets, the result is displayed and recorded valid checks, if malfunctions were detected, the result is not valid and the numbers of the malfunctioning output contacts are displayed both on each test set and on

60974. 16

the entire set of test sets In addition, the information on the numbers of faulty output contacts is recorded in a certain area of the operating memory of the calculator I and is further used (as input data) in the second mode check program.

Fault diagnosis of digital synchronous and asynchronous circuits at real clock frequency is carried out as follows.

If at checking object 103 control in the first mode there is at least 15 faulty one contact (the result of the check is Not valid), then the computed | Driver I runs a diagnostic program that uses the work program of the first test mode and the set state information.

va interior points of object 103

control with linking internal points to possible fault paths, which is recorded in the external

5 memory of calculator 1 during the execution of the self-study program. In the course of the self-training program, the signatures are removed from the internal points of the scheme of the known control object 103 and the values of the removed signatures with the sign of the sequence number of the point of the scheme are written into the external memory of the I / O unit 3. The number and location of interior points is selected individually for each control object 103, depending on its complexity and the required depth of searching for the failed elements. The removal of signatures in this case is carried out as follows.

Any of the unused nodes 9.1 matching is selected as the output and is masked, then the calculator 1 issues the command Reg.reg. out and the corresponding sequence of commands Set. Tr, which sets in the output address register 41 the code of the number of the selected node 9.1 matching. The specified code is fed to the control input of the multiplexer 42, which connects to the input of the analyzer 43 the unit output of the comparator 35 of the selected matching node 9.1. Next, the operator connects the output of the selected node 9.1 negotiation to the required internal point of the control object 103 and sends the Start command from the keyboard of the input-output unit 3 to

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The calculator 1, which, after receiving the operator's command, masks all the output matching blocks 9 to prevent the test program from stopping when errors are detected, sends the CASA command and starts the program. Much dynamic testing of the first mode. At the same time, the input test object, similarly to the first mode, receives input test sequences that generate, at a given internal point, a final sequence of signals that the signature analyzer 43, gated by the Strobe signal from the address controller 10, converts to a signature code at a real clock frequency. In this case, the comparator 35 of the selected node 9. matching performs the amplitude selection of the signal sequence at a given internal point, and the Strobe signal performs the time

selection. After the end of the dynamic test on the arrival of the signal Interrupt. 2, the calculator 1 reads the signature code, which arrives at its information input from the output of the signature analyzer 43 through the pairing unit 2 and transforms it with an internal point to the external memory of the I / O unit 3. After reading the signature codes for all selected internal points of the control object 103 in the same way as described in the external memory, it is necessary to add signs of all possible fault paths to the external memory of the calculator 1. For each output contact, a related subset of selected points within the control object 103 that are in the path from the output contact to the input and having a logical connection with the input is determined.

Q; input contacts having a logical connection with an i-M output contact depends on the tree of the logical graph of the control object 103, and the set M of the Q groups; Determination of the number of output contacts of the control object 103 Traces of possible malfunctions are entered by the operator from the keyboard of the I / O unit 3 as follows.

First, the i-ro number of the output contact is recorded, then, in turn, all the numbers of points, located between it and the 3rd input contact, and

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then the number of the 3rd input contact. After that, the next fault line is recorded, etc., until all possible fault paths for the 1st output contact are recorded. Thereafter, subsets of possible fault traces are recorded for another output contact, etc., until all possible fault traces are recorded for the plurality of M output contacts. The subsets of points within possible fault paths can be intersecting, i.e. some

5 points can belong to several traces of possible faults. This completes the self-study program. Record the initial information about the state of internal points

The 0 specific object of control and their location in the fault traces is made once and then stored on external media of the I / O unit 3.

5 f

After running the diagnostic

the program calculator 1 is addressed to the memory area, where information about the numbers of faulty output contacts determined during the test in the first mode is stored, selected a subset of fault traces Q; for a subset of P output contacts from a set of all possible fault paths Q for a set of M output contacts. After that, the calculator 1 programs the address address register 41, the address code of which from the code goes to the control input of the multiplexer 42, which connects the single output of the comparator 35 of the matching node 9.1 connected to the ith output terminal from the subset P, to the input of the signature analyzer 43. Next, the calculator 1 masks all the output nodes 9.1 of the negotiation to eliminate the stopping of the test program when errors are detected, issues the Squad CA command, set the signature analyzer 43 to the zero state, and start the program dynamic testing of the first mode. The inputs of the control object, similar to the first mode, are fed to the inputs of the object 103

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On its output pins, the final sequence of signals (responses), which the signature analyzer 43, gated by the Strobe signal from the address controller 10 at the real clock frequency, will convert to the signature code, will generate it. With this, the comparator 35 of the selected matching node 9.1 performs amplitude selection of a sequence of output signals, and the Strobe signal of the address controller 10 is a time selection. After the end of the dynamic test for the arrival of the signal Interrupt. 2, the calculator 1, through the block 4 of decoders, issues the commands Csr.RNK and Zap. in PCNK (at block 8), while in the register 44 from the output of the signature analyzer 43 the signature code value is written for the selected i-ro faulty output contact of the control object 103. The value of the signature code for the i-ro output contact can be anything and depends on the location and type of fault. After that, the computer 1 through the block 4 decoders gives the command Fill in, Maskir. the address controller 10 and the information command corresponding to the number of the 1st output contact to the setting block 40 of the J-ro of the matching node 9, from the output of the AND 92 element of the setpoint 40 which receives a signal to the inhibitory input of the AND 36 element, while passing the signal from the output of the test memory block 37 of this node 9.J matching to the counting input of the counting trigger 33. Next, the calculator 1 starts the dynamic test program of the first mode again. In this case, all inputs, except for the selected 1st, are generated, the same input sequences as in the previous case. At the same time, if on the track from

The input 1st to vertical i-ro contact has no faults, the signature analyzer 43 records a signature code that differs from the previous one, as there is a constant signal level on the 1st input contact instead of the signal sequence previously fed to it, and if there are one or several faults of the constituent type O or constituent 1 on this route, the signature code equal to the previous one is fixed in the signature analyzer 43, since the disconnection of the 1st input of the control object 103 in the absence of convergent signals occurrences

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in the tree of the logical Graph of the set Q; does not lead to measurement of the output sequence at the output of the i-ro contact defective. After that, the calculator 1 through the block 4 of de-encryptors, performs the commands Cbr.RDS and Zap.RDS at block 8 of the analysis. In this case, from the output of the signature analyzer 43, the value 45 of the diagnostic signature code of the input contact is entered into the register 45. If the signature codes in registers 43 and 45 are equal, then after the command has been given, page Schr. Comparison element 46 generates a signal at the first interrupt input of calculator 1, indicating the presence of faults on the tested path. The absence of this signal indicates the absence of faults on this route. After iterating through all the input contacts of the set Q, for the output i-ro of the faulty contact, the transmitter 1 programs in the register 41 the address of the next faulty contact, for which the same operations are performed as for the i-ro faulty contact in order to detect the fault traces and .d., until all the subsets of P outgoing faulty contacts have been processed. Information on all detected faulty traces is stored in the operational memory of the calculator 1 and is used when searching for failed items with a given search depth in the interactive mode of the operator with a diagnostic program. After that, the information on the mutual location, signs and state of the internal points of the first identified fault path, which was previously recorded during the execution of the self-study program on the external media of the I / O unit 3, is inserted into the RAM of the calculator 1, and the diagnostic dialog box is started. - the operator gives the target indication to the operator, on the display of the input / output unit 3, the number of the first point of the test track. The operator connects one of the unused nodes 9.i matching to the specified point of the route and issues a Start command from the keyboard of the I / O unit 3. In this way, the selected node 9.i matching, removing and

21

write to the operational memory inertier 1 of the signature code of the given trace point. The dialogue diagnostic program sets the order of removal of signature codes at the points of the trace being tested based on the half-pin-point division method, with the starting point of the signature code being captured at the input contact of the trace being tested. Based on the analysis by the method of comparing the detected signature codes with the reference one at the corresponding points of the route, the dialogue diagnostic program makes a conclusion about the direction of movement along the route. Initially, the movement is specified by dividing the regions by half in the direction from the input contact to the output contact. When the first point at which the real code of the signature does not coincide with the reference one is reached, a fault is made between the given point and the previous one, after which the direction of movement along the route by the method of dividing the sections into half is reversed, etc., until The location of the fault with a given search depth for a given faulty path has been determined. Calculator 1 memorizes in memory a symptom of a fault location and proceeds to troubleshoot other detected fault traces that do not have logical connections to this faulty path, etc., until all faults have been determined. After that, the calculator 1 provides information on the locations of faults, indication and registration to 5 blocks of 3 I / O. When troubleshooting with the greatest possible depth of search,

when the signature removal points are located at all inputs and outputs of the elements of the circuit of the control object 103, it is possible to determine not only the fault location, but also the nature of this fault, the mismatch of the signal amplitude required at this point of the circuit or the discrepancy of the signal delay time required at this point, open circuit , short circuit to earth, short circuit to power, short circuit between each other. The discrepancy between the amplitude of the signals required and the presence of delays in the signals larger than those required in a given circuit is identified by the difference between the clear and reference signatures at all points of the circuit. Circuit identification is identified

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the difference in signatures at the output of an element and at the input (s) of another element directly connected with it. Circuit closure on

5, the ground is identified by the presence of a zero signature both at the output of an element and at the inputs of the elements directly associated with it. Circuit with power

0 is identified by the presence of a single signature for a given control object 03 both at the output of an element and at the inputs of the elements directly connected with it,

5 The closure of chains among themselves is identified by the presence of identical signatures on chains that are not really connected to each other, and these signatures differ from the actual for the first and

0 second circuit. With such a depth of the search for the failed elements, the calculator 1 returns to the input-output unit 3, in addition to the information on the location of the fault, also information on the type of non-operability. This is where the troubleshooting of digital synchronous and asynchronous circuits at the actual clock frequency ends.

0 The device is in the mode of functional static testing by the Goden method and the diagnostics of malfunctions of analog-digital circuits works as follows.

r A feature of the organization of testing and diagnosing analog-digital circuits is that the input stimulus signals for them are set cyclically in the form of stepwise functions of complex shape independently of each other and in parallel along all inputs, and the output signals are the usual logical two-level signals. The outcome of this is being built.

 verification algorithm. First, preparation of the device units for operation is carried out. The calculator 1, in accordance with the program entered into its operational memory, performs

Similar to the distribution of nodes 9.1 for input and output circuits described for digital circuits, programming of block 6 of programmable power sources, programming of U levels (, n Sch1 38, which set the reference level 55 at the output nodes

9.1-9.P matching, programming of the Ugj level in the DAC 13, which sets the reference level O. After that

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through the decoder unit 4, the Clear Tr. Tr. command is sent, which goes to the zero installation inputs of the counting triggers 33 of all nodes 9.1-9.P matching, sets them to the zero state, and the sequence of information commands that establish the counting triggers 33 in the input nodes 9.1 match to one state, and in weekends to states corresponding to the first output test set. The method of installing the required test set in this mode differs from the digital test mode in that the alternating signals are sent to the counting inputs of the triggers 33 not from the test memory blocks 37, but from the 4 decoders in the form of information commands that through the OR 32 element arrive at the counting inputs of the triggers 33 of the corresponding nodes 9.1 match, setting them to the state opposite to the previous one.

In each input node 9.1, matching in accordance with the required step function on this test set is programmed DAC 38, from the outputs of which the analog levels Ujj are output to the analog switch 34, since the counting triggers 33 of all input nodes 9.1 matching are in one state, and then through the switch-31 to the inputs of the object 103 controls. The signals of the reactions of the object 103 controls in the form of logical two-level signals are fed to the inputs of the comparators 35 nodes 9 according to the previously selected output. Comparators 35 perform amplitude selection of reaction signals in the same way as described when checking digital circuits. According to the commands of Set.3. The device W.p. in the address controller 10 sets the code of the number of the first test set in the address counter 49, by the command Settr. Triggers 73 in the fault recorders 39 of all nodes 9.1-9. The matching signals are set to one, by the Strobe command in the IO address controller at the output of the element 65 OR the Strobe signal is generated, which is fed to the fault recorders 39 by temporarily collecting the signals received

6097424

from the single and zero outputs of the equipments 35 output nodes 9.1 matching as described for digital circuits, and the start of the goner 5 tor 66 of the single pulses of the address controller 10, at the output of which a Polling signal is generated. If, after amplitude and time selection of reaction signals, triggers 73 in

10 some nodes 9.1 of the matching remain in one state, then the Polling signal arriving at the control results identification block 1I searches for faulty ones.

15 output contacts of control object 103 are similar to those described for digital circuits. If the triggers 73 faults of all output nodes 9.1 matching are in zero.

20 state, the calculator I, which, after the command of the Strobe has entered the idle mode of the interrupt signals, without receiving these interrupt signals, goes to the previously interrupted

5 program. At this point, the monitoring cycle on the first test set ends. The calculator 1 establishes with the help of information commands in the output nodes 9.1 matching the counting triggers 33 in the state corresponding to the second test set, in each input node 9.1 matching matches the DAC 38 according to the required step function, according to the commands of Ref. .3.p sets in the controller 10 addresses in the counter 49 code of the number of the second test set and gives the command Settr. Disrv. and Strobe, repeat control loop on the second test, recruitment, etc., until the entire field is checked

test kits. I

Fault diagnosis of analog-to-digital circuits is performed for the digital part of the circuit in the same way as described for digital circuits using signature analysis methods. The analog part of the circuit is verified using

0 connecting the meter block 5 to the I internal points of the circuit, while using a free node to connect the input of the meter block 5 by the operator to the internal points of the circuit.

5 9 matching, disguised and selected as output, and troubleshooting can be carried out as visually, in the form of stepwise

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Functions with cycling nporpawibi to 1 control with the help of an oscilloscope, which is part of the meter block as well as automatically in the interactive mode of the operator working with a long-term program during the step-by-step run of the test program with connection to internal points of the circuit in which it is necessary to measure Analog levels of a digital voltmeter, measuring unit and part of the unit.

The proposed device in the functional static mode according to the Goden-not-good method and diagnostics of faults of the analogue circuitry works as follows.

A special feature of the organization of testing and diagnostics of digital-analogue circuits is that their input stimuli are specified in the form of ordinary logical two-level signals, and the output signals are in the form of 1-step functions of a complex form, formed independently of each other and in parallel across all channels. Based on this, a verification algorithm is constructed. First, preparation of the device units for operation is carried out. The calculator 1 in accordance with the program entered into the RAM

does the same as described for digital circuits, the distribution of nodes 9.1 input and output, programming block 6 35 programmable power sources, programming Ug level in the DAC 38, setting the stimulation level 1 in the input matching blocks 9, programming level and jjj DAL 12, specifying the level of the logic of the stimulating signals at the input nodes 9.i matching. By command Maskir. in the controller 10, the address 56 is set to one state. The signal from the output of which is fed to the input of the elements AND 88 and the blocks 40 of the settings of all the nodes 9.1-9. After submission of information commands corresponding to the numbers of all output nodes 9.1 matching, and then the command Counter. Triggers 83 and 86 of the block 40 of the settings of all output nodes 9.1 matching set-. 55 are cast in one state. After giving the command Sbr.maskir. and Sat. Triggers 83 in blocks 40

thirty

40

45

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, about

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the settings and trip 56 in the controller 10 addresses are set to the zero state. After that, the command Reset scr. Is issued, which sets the counting triggers 33 of all nodes 9.1-9. The matching to zero states, and the sequence of information commands that set the counting trigger 33 in the input nodes 9. i match to the state corresponding to the first test suite. Then, in each output node 9, the matching in accordance with the required step function on this test set is programmed by the DAC 38, while the reference a1 the analog levels U (, n must be set greater than the expected value of the analog response signal Up by the value of uU - db, where uUp is the maximum permissible deviation of the measured value Up from the nominal value; iUj, is the measurement error of the comparator 35. The reaction signals U., from the outputs of the control object 103 in the form of step functions of a complex form are fed to the information inputs of the comparators 35 output of the common nodes 9.1 matching, which carry out parallel amplitude selection of reaction signals. By the commands Set.Z.Z.p in the address controller 10, the code of the number of the first control cycle of the first test set in the address counter 49 is set, by the command Set.un.dispr. the triggers 73 in the recorders 39 faults of all nodes 1.1-9. The matching is set to one, on command

The strobe in the controller 10; at the output of the element ItTbi 65, a signal is generated. The strobe, which arrives at the fault recorder 39, is realized by the time selection of the sig-. The signals from the single outputs of the comparators 35. The signals from the zero outputs of the comparator 35 do not participate in the selection, since the unit signal level at the input Control. fault recorder 39 permits selection of signals on AND 75 element and prohibits it on AND 76 element. Zero signal levels from the outputs of the trigger 33 in all output nodes 9.1 matching permit the selection of signals from inverse single outputs

27

Comparators Zb through element And 75 Comparators 35 in output blocks 9 matching, in which - series, form on inverse unit outputs unit signal levels, which at the time of the Strobe signal through element And 75 set the triggers 73 to zero states. If at any output node 9.1 of the match L p U, then its comparator 35 at the inverse output has a zero signal level and its trigger 73 remains in one state. In this way, the suitability of analog levels of reaction signals at the upper permissible level is determined. Poll triggers 73 to the weekend

nodes 9.1 reconciliation and search for cbry-1 .-

These output contacts are implemented as in the test of analog-to-digital circuits. Thereafter, the validity of the analog levels of the reaction signals at the lower acceptable level is determined. BQ of all output nodes 9.1 matching with the help of information commands all counting triggers 33

 set to one state, and in the input nodes 9.1 matching all the counting triggers 33 remain in the same state corresponding to the first test set. At each output node 9.1, 1Shch matching 38 is reprogrammed so that the reference, analog levels of the UOD are lower or the expected value of the analog response signal U. by the value of iUp-AL, after that according to commands Set. The setup of W.p. programmed the number of the second cycle. Monitoring the first test set, the command Settr. Not corrected, setting the triggers 73 of all nodes 9 matching to one state, and the command Strobe., Which organizes the time selection of signals in the malfunction recorders 39 of all the output matching nodes 9, while the unit signal levels coming from the outputs of the counting flip-flops 33 in all the output matching nodes allow the selection of signals from the single outputs of the comparators 35. Comparators 35, whose Up U (j, form dissolved in unit outputs single signal levels which action time strobe signal via the AND gate 74 triggers 73 mounted in the zero state 6,097,428

neither If in any node 9.1 of matching Ir-1 pn, then its comparator 35 at the single output has a zero signal level and its fault condition 73 remains in one state. Interrogation of triggers 73 faults and the search for faulty output contacts is carried out as in the test of analog-digital

0 schemes. As a result, in the first test set, two monitoring cycles are used to simultaneously control the output levels of the reaction signals at the upper and lower limits with

5 given accuracy. After that, in the input nodes 9.1 matching, the counting triggers 33 are set to the states corresponding to the second test set, and the monitoring cycle

0 is repeated, etc., until the output analog levels of the signals on all test sets are monitored.

Fault diagnosis of digital-5 analog circuits is carried out as for analog-digital circuits.

The register unit 14 contains storage registers 80 and 81, into which, using control signals from block 4, decrypting ratios Zap.Rg.G and Zap.Rg.2, the codes are received at the inputs of the D / A converter 12 and 13.

Signature analyzer 43 contains a shift register 93, in which signature convolutions are obtained, and modulo two adder 94, summing the input signal with the contents of register 93 to obtain a signature.

Thus, the application of the invention allows to increase the speed of the device during dynamic testing of digital synchronous and asynchronous circuits by 20-30 times, which ensures the verification of this class of circuits at a real clock frequency, as well as organizing the tolerant parametric control of reaction signals of control objects Fixed analogue levels of complex shape, the assessment of the fitness of which is possible to produce simultaneously across all outputs of the object of the control 1 role according to the criterion Uo.Up. U.,

where and UQP are the allowable lower scientific research institutes and the upper limits of the controlled analog level at the 1st controlled output, which expands the functional capabilities of the device

va. In addition, it was possible to organize diagnostics of digital synchronous and asynchronous circuit malfunctions at real clock frequency in the interactive mode of operation with operator 1 with accurate localization of the location of non-distortion and identification of its type, which also enhances the functionality of the device.

 about rmu l and inventions

Claims (9)

one . A device for monitoring the electrical parameters of digital nodes, comprising matching units by the number of monitored parameters, a block of programmable power sources, a interface block connected with the first information inputs and outputs, respectively, with the first information outputs and the calculator inputs, with the second information inputs and outputs t, s and inputs of the I / O unit, the third information inputs - with the information outputs of the meter unit, the signal input of which is connected With the first outputs of the matching nodes, the second outputs and the first inputs of which are stimulating outputs and measuring inputs of the device, the first input of the calculator is connected to the first output of the analysis block, the information input of which is connected to the information output of the diagnostic block the outputs of the matching nodes, as each matching node contains the first element AND, the first element HTOi, the test memory block, the counting trigger, the switch connected by the first, second outputs and The first input with the first, second output and the first input of the matching node, the third output with the first input of the comparator, the second input with the output of the analog key, the third input with the first output of the setting block, the second outputs of which are connected to the information input of the first digital-analogue the converter, whose output is connected to the first input of the analog key and the second input of the comparator, the diagnostic unit contains the output address register, which inputs are the control inputs of the diagnostic unit, and the outputs are connected with control inputs 60974. thirty multiplexer, the signal inputs of which are the information inputs of the diagnostic unit, and the output is the information output of diagnostic unit 5, the analysis unit. contains a signature analyzer, whose information input is the information input of the analysis unit, and the outputs are connected to the information inputs of the signature register a faulty contact and diagnostic signature register whose inputs / strokes are connected respectively to the first and second inputs of the comparison element, the output 15 of which is the first output b analysis locus, connected control of the control inputs with control inputs of the signature analyzer, the register of the defective contact signature and the diagnostic signature register, characterized in that, in order to expand the functionality of the device by providing monitoring and diagnostics 5 at a real clock frequency in real time time, as well as two-threshold level control at any of the outputs of the monitored digital node, an address controller, a fault identification block, a desch block are entered into it bridges, two digital-to-analog converters, a register block, and a registrar fault are added to each matching node, the outputs of the programmable power supplies are the outputs of the device supply voltages, the first output of the address controller is the output of the device synchronization, the second address controller of the address is connected to the second inputs of the matching nodes, the third and fourth outputs with the third and fourth inputs of the matching nodes, the fifth outputs with the fifth inputs of the matching nodes, with a fourth informational inputs of the interface unit and informational inputs of the register unit, the sixth output with the sixth inputs of the matching nodes and the gate input of the analysis unit, the seventh output with the first input of the fault identification block, and the eighth output with the second input of the calculator, the first output of the identification block Fault is connected to the first input of the address controller and the third interrupt input of the transmitter, the second output 0 five 0 five with the fourth interrupt input of the evaluator, the third outputs with the corresponding seventh inputs of each matching node, and the fourth identification block outputs  . the right-handers are connected to the fifth information inputs of the interface unit HHHj, the first outputs of the decoder unit are connected to the control inputs of the programmable power supply unit, the second outputs are connected to the control inputs of the meter unit, the third outputs are to the second inputs of the address controller, the fourth outputs are from the eighth the inputs of the matching nodes are NIN, the fifth outputs are with the ninth inputs of the corresponding matching nodes, the sixth outputs. - with the second input of the fault identification block, the third input of the address controller and the tenth inputs of the matching nodes, the seventh outputs - with the eleventh inputs of the matching nodes, the eighth output - with the twelfth inputs of the matching nodes, the ninth output - with the third input of the failure identification module, ten The outputs are from the control inputs of the register block, the eleventh outputs are from the control inputs of the diagnostic block, and the twelfth outputs of the decoder block are connected to the control inputs of the analysis block, the first and second The outputs of the register block are connected respectively to the information inputs of the second and third digital-to-analog converters, the outputs of which are connected respectively to the thirteenth and fourteenth inputs of the matching nodes connected by the fourth outputs of the corresponding fourth inputs of the fault identification block, the interface block is connected by the third information outputs, address outputs and gating output, respectively, with information inputs, address inputs and gate input unit decoders, the second outputs of the analysis unit are connected to the sixth information input of the interface unit, and in each matching node the second input is connected to the first input of the first element AND and the first input of the fault recorder, the third inputs are connected to the control inputs of the memory block of the test, the fourth inputs - with the first inputs of the block settings, fifth entrances - with. the second inputs of the setpoint and g J Ju 15 20 25 h. . five 0 five the address inputs of the test memory block, the sixth and seventh inputs, respectively, with the second and third inputs of the fault recorder, the eighth input — with the first zero setup input of the counting trigger, the ninth input — with the third input of the settings block, the first input of the first OR element the information input of the memory block of the test, the tenth input — with the fourth input of the setting block and the second zero setting input of the counting trigger; the eleventh inputs — with the fifth inputs of the setting block; the twelfth input — with the fourth input of the recorder the thirteenth input is connected to the second input of the analog key, and the fourteenth input of each matching node is connected to the third input of the comparator, which is connected to the zero and single outputs of the fifth and sixth input of the fault recorder, the output of the test memory unit is connected to the second input of the first And element the output of which is connected to the second input of the first OR element connected by an output to a counting input of a counting trigger connected by an output to a third input of an analog switch and the seventh input of a fault recorder STI, yield fault logger unit and the comparator are respectively third and fourth output node matching,. The eighth and ninth inputs of the fault recorder are connected respectively to the third and fourth outputs of the setting block, the fifth output of which is connected to the inverse input of the first element I, and the sixth output is connected to the fourth input of the switch and the tenth input of the fault recorder, and in the strobe analyzer block - the damming input is connected to the gating input by the signature analyzer, the outputs of which are the second and the outputs of the analysis unit, the control input of which is connected to the third input comparison item, I 2. The device according to claim I, wherein the address controller contains a first storage register, the zero inputs of which are the third input of the address controller and connected to the zero setting inputs of the first, second and third binary counters and the first and second setting inputs of the second two. the counter and the first, second, third, fourth, fifth, and sixth triggers, the second zero setting input of the first trigger is the first input of the address controller, the single setting inputs of the first, second, three first, fourth, fifth, and sixth triggers, second zero setup inputs of the third, fourth, fifth, and sixth triggers, second zero setup input of the second trigger, first input of the second element OR, first summing counting input of the fourth binary counter, second zero setup input of the fourth binary counter, single setup inputs of the storage register, setup inputs of the first binary counter, single setup inputs of the fourth binary counter are the second the address controller moves, the outputs of the fifth and sixth flip-flops are connected respectively to the first and second inputs of the third OR element, the outputs of the second, third and fourth flip-flops are the corresponding fourth outputs of the address controller, the inverse output of the third OR element, and the output of the sixth flip-flop corresponding to the third outputs of the controller the addresses, the outputs of the fourth binary counter are the fifth outputs of the address controller, the output of the first trigger is connected to the triggering input of the first pulse generator pulses connected by the output to the counting input of the second double counter, the outputs of which are connected to the first inputs of the corresponding second AND elements, the second input of which is connected to the corresponding outputs of the storage register, and the outputs to the inputs of the fourth OR element connected to the first inputs the third, fourth, and fifth elements And the counting input of the third, binary counter, the output of the first bit of which is connected to the second inputs of the third and fourth elements And and the first inverse input of the fifth element And that, and the output of the second discharge - a third input of the fourth AND gate, an inverted input of the third and the second inverted input of the fifth AND gates, the outputs of the third and fifth are soot elementov.I 5 Q 0 0 5 0 five Respectively, the first and second outputs of the address controller, the output of the fourth AND element, is connected to the second input of the second OR element, the output of which is the sixth output of the address controller and connected to the trigger input of a single pulse generator, the output of which is the seventh output of the address controller and connected to the second the input of the fourth binary counter and the subtracting counting input of the first binary counter, the carry output of which is the eighth output of the address controller and connected to the third zero installation input of the first trigger. 3. The device according to claim 1, wherein the fault identification block contains fifth OR elements, the first inputs of which are the first input of the block, the first zero installation inputs of the seventh trigger and the fifth binary counter are the second input of the block, the single installation input of the seventh the trigger is the third input of the block, the inputs of the sixth OR element are the fourth inputs of the block, the second zero setup input of the seventh trigger is connected to the output of the sixth OR element and is the first output of the block, the output from the seventh trigger is connected to the trigger input of the second pulse generator, the output of which is connected to the counting input of the fifth binary counter, whose outputs are the quarter outputs of the block and connected to the corresponding inputs of the first binary position decoder, the outputs of which are connected to the corresponding second inputs of the fifth OR elements, the outputs of which are the third outputs of the block, the additional output of the first the binary position decoder is connected to the second zero setup input of the fifth counter and the third one. zero setting input of the seventh trigger and is the second output of the block. 4. The device according to claim 1, wherein the fault recorder comprises an eighth trigger, the first single installation input of which is the first input of the recorder, the first inputs of the sixth, seventh and eighth elements AND are the second input of the register The first input of the ninth AND element is the recorder's standard input, the second single installation input of the seventh trigger is the fourth input of the recorder, the second input of the eighth And element is the fifth input of the recorder, the second input of the sixth And element, and the first inverse of the seventh element. And are the sixth input of the recorder, the third input of the sixth And element, the second inverse of the seventh and first inverse input of the eighth And elements are the seventh input of the recorder, the fourth input of the sixth and second input of the seventh And elements, and the third inverse input of the eighth element And And are the eighth input the recorder, the first and second inverse inputs of the ninth And element are respectively the ninth and tenth inputs of the recorder, the outputs of the sixth, seventh and eighth And elements are connected to the first, second and third it has zero installation inputs of the eighth trigger, the output of which is connected to the second input of the ninth AND element, the output of which is the output of the register. one 5. The device according to claim 1, which differs from the fact that the setting block contains the tenth, eleventh and twelfth elements AND, the first inputs of which are the first inputs of the setting unit, the single installation D inputs of the second storage register are corresponding the second inputs of the setting block, the second inputs of the eleventh and twelfth And elements are the third input of the settings block, the first zero installation inputs of the ninth, tenth, eleventh and twelfth triggers are the fourth input of the settings block,. the first gate input of the second storage register is the corresponding fifth input of the setting block, each of the first inputs of the thirteenth, fourteenth and fifteenth elements AND, the second zero setting inputs of the ninth, tenth, eleventh and twelfth flip-flops separately are corresponding to the fifth the inputs of the settings block, the output of the ninth trigger is connected to the second input of the tenth, thirteenth, fourteenth and n, 26097436 The fifteenth element II, the outputs of the second storage register are secondary. The outputs of the setting block, the outputs of the ninth, tenth, eleventh, 5th, twelfth, and tenth elements of And are the third, sixth, first, fourth, and fifth outputs of the setpoint block, respectively. 6. The device according to claim 1, TL and - 10 such that the block of decoders contains a second binary positional decoder, the inputs of which are the address inputs of the block, the third, fourth, fifth, sixth, 15th, seventh, eighth and ninth binary positional decoders, the inputs of which are informational inputs of the block, the gate input of the second binary positional depressor 20 is the gate output of the block, the first, second, third, fourth, fifth, sixth, seventh outputs of which are connected to the gate inputs of the third, fourth rtogo, fifth, 25 sixth, seventh, eighth and ninth positional binary decoders, outputs the third, fourth,. The fifth, seventh, and eighth binary positional decoders are 3Q, respectively, first, second ,. eleventh, third, fifth. block outputs, first, second, tre5 0 five 0 five The fifth, fourth, fifth, sixth outputs of the sixth binary positional decoder are the corresponding twelfth outputs of the block, the seventh and eighth outputs of the tenth outputs of the block, the first, second, third, fourth, fifth, sixth, seventh, eighth outputs of the ninth positional the decoder are the seventh outputs of the decoder unit, the ninth, eleventh, twelfth outputs of the ninth position decoder are the eighth, ninth, fourth and sixth outputs of the unit. 7. The device according to claim 1, which is duplicated in that the test memory block contains a matrix storage register whose address inputs are the corresponding inputs of the text memory block, the first input of the seventh OR element is the information input of the memory block test, input Record-read matrix pv storage horn is connected to the second input of the seventh OR element and is the corresponding control input of the test memory block, information The input of the matrix storage register and the inverse input of the seventh element OR are the corresponding control input of the test memory block, the inverse output of the seventh element OR is connected to the input of the selection of the matrix storage register whose output is the output of the test memory block 8. An apparatus according to claim I, wherein the signature analyzer comprises a 16-bit shift register, the gate input and the zero set-up inputs of which are the gate and control inputs of the signature analyzer, respectively, the first input of the modulo two is information entry signature26097438 The analyzer and the output are connected to the information input of the 16-bit shift register, all outputs of which are outputs of the signature analyzer, and the seventh, ninth, twelfth, sixteenth outputs are connected to the second, third, fourth and fifth inputs, respectively. - an element of addition modulo two, 10 9. The device according to claim I, characterized in that the block of registers contains the third and fourth storage registers, the information inputs of which are interconnected 15 and are information inputs of the block, the control inputs are the corresponding control inputs of the block 1, and the outputs respectively the first and the second outputs of the block | registers. Hasff.y fW / 77. OmSn.ti dm 6l JO I ctnpoS ycm.mff.Htucnp. 0mm S3 Vsh.shch. Mark 14 Post.35 , J comp. A 75 Otza.Z ° "ffР  MOSNIR. Omsn.tfH nodKa.ixoSot Rev. 11 МЖФи .5 Cffou nk BUT 6P. It 73 L 77 41. If H9S.n noelp unadl.2 Fi9.9 Compiled by I. Shvets Editor L. Pchelinska Tehred M. Khodanych Order 5234/51 Circulation 671 Subscription VNIIPI 1 of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk office, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader O. Lugova