SU1257827A1 - Device for generating pulses from sine signal - Google Patents

Abstract

The invention can be used in measurement technology. The purpose of the invention is to increase the speed of the device. The device contains a voltage comparator 1, an inverter 2, a peak voltage detector 4 of positive polarity, keys 8 and 9. Introduction of an attenuator 3, a peak voltage detector 5 of negative polarity, analog inverters 6 and 7, reset blocks 10 and 11 and connection them with the elements of the device maintains the phase constant of the output pulse signal of the driver when the amplitude of the input sinusoidal signal changes. 2 Il. tc SP 00 to

Description

The invention relates to a pulse technique and can be used in a measurement technique.

The aim of the invention is to increase the speed by maintaining the phase constant of the output pulse signal of the driver when the amplitude of the input sinusoidal signal changes.

FIG. 1 shows a flow chart of a former; in fig. 2 - time diagrams of his work.

A pulse shaper from a sinusoidal signal contains a voltage comparator 1, an inverter 2, an attenuator 3, a peak positive voltage detector 4, a peak shaper detector 5 at a positive input voltage half-wave, and an output voltage U4 of the peak alternating wave 4 positive voltage. wives When the maximum amplitude of the positive half-wave of the voltage U4 is reached, a voltage proportional to this maximum value is memorized at the output of the peak detector 4 at this maximum level 10 (Fig. 2c). Since the input voltage of the device is fed to the inputs of the peak detectors through the attenuator 3, the voltage U4 allocated at the output of the peak detector 4 is less than the maximum amplitude of the positive

voltage, the first 6 and second half-waves of the input voltage. With a voltage of 7 analog inverters, the first 8 and second 9 keys, the first 10 and second 11 reset blocks. The input sinusoidal signal is fed to the input bus 12 of the driver, the output pulse signal of the driver is removed from the output bus 13.

The input bus 12 of the imager is connected to the first input of the voltage comparator 1 and to the input of the attenuator 3, the output of which is connected to the signal inputs

The output from the peak detector output 4 is inverted by the first 6 l analog inverter, this voltage Us (fng.2d) is fed through the open first key 8 to the second input 2Q of the voltage comparator 1.

At the moment when the input voltage UBX reaches the first input of the voltage comparator 1 at a negative half-wave of the input voltage Ue, the second input of the comparator 1 (Fig. 2d) the comparator 1 is tilted to detectors 4 and 5 and 25 is generated and a negative voltage is generated at its output wives accordingly. The output of the peak detector 4 is connected to the input of the first analog inverter 6, and the output of the peak detector 5 is connected to the input of the second positive voltage surge voltage Ui (Fig. 2g). This pulse voltage Ui from the output of the comparator 1 is inverted into its antiphase voltage U2 (Fig. 2i) by the inverter 2. In this case, the voltage inverter 7. The outputs of the first 6 and second voltage Ui from the output of the voltage comparator 1 and U2 s the output of the inverter 2, the first switch 8 is closed, and the second switch 9 is opened and the output of the second analog inverter 7 to the second input of the voltage comparator 1 receives the voltage U (Figure 2e) obtained by inverting the output voltage Us (Fig. 2d) of the peak voltage detector 5 negative half-wave input voltage. At the same time, the voltage pulse Uio (Fig. 2h) from the output of the primary 7 analog inverters is connected respectively to the signal inputs of the first 8 and second 9 keys, the outputs of which are connected to the second input of the voltage comparator 1. The output of the voltage comparator 1 is connected to the control, the input of the second switch 9 and the inputs of the inverter 2 and the second reset unit P. The output of the inverter 2 is connected to the output bus 13 of the driver, as well as to the control input of the first key 35

Cha 8 and the input of the first reset unit of the 10th reset unit 10, the voltage U4 to the outputs of the first 10 and second 11 reset units are connected to the inputs Reset peak detector 4 and peak detector 5, respectively.

The pulse driver from the sine of peak detector 4 is reset to zero.

The next triggering of the comparator 1 voltage occurs when the amplitude of the input variable voltage signal is reached, operating as follows: UBX. with its positive half.

If there is a sinusoidal voltage Uex at the input. (Fig. 2a) it is fed to the first input of the voltage comparator 1 and to the input of the attenuator 3. In particular, the voltage U (Fig. 2e). A negative voltage drop Ui is formed at the output of the voltage comparator 1 (Fig. 2g), and the second reset unit 11 is the voltage Us at the output

In this case, as attenuator 3, 50 peak detector 5 can be reset to zero.

for example, a resistive voltage divider is used. From the output of the attenuator 3, a weakened alternating voltage, proportional at each given moment in time to the input alternating voltage of the driver, arrives at the signal inputs of the peak detectors 4 and 5. In the process of increasing the input alternating voltage 55

At the same time, the voltage pulses Ui from the output of the voltage comparator 1 and U2 from the output of the inverter 2 simultaneously open the key 8 and the second key 9 closes.

Thus, the voltage comparator 1 is triggered once with a positive one, and the second one with a negative half-shaper when the input voltage has a positive half-wave, the output voltage U4 of the peak alternating-voltage detector 4 also rises. When the maximum amplitude of the positive half-wave of the voltage U4 is reached, a voltage proportional to this maximum value is memorized at the output of the peak detector 4 at this maximum level (Fig. 2c). Since the input voltage of the device is fed to the inputs of the peak detectors through the attenuator 3, the voltage U4 allocated at the output of the peak detector 4 is less than the maximum amplitude of the positive

half wave input voltage. The voltage from the output of the peak detector 4 is inverted by the first analog 6 L inverter, this voltage Us (fn.2d) is fed through the open first switch 8 to the second input of the voltage comparator 1.

At the moment when the input voltage UBX reaches the first input of the voltage comparator 1, the negative input voltage Ue of the second input of the comparator 1 (Fig. 2e) negatively causes the comparator 1 to overturn and output positive voltage at its output and positive output voltage Ui is formed at its output (Fig. 2g). This pulse voltage Ui from the output of the comparator 1 is inverted into its antiphase voltage U2 (Fig. 2i) by the inverter 2. In this case, the voltage Ui from the output of the voltage comparator 1 and U2 from the output of the inverter 2 is closed, and the second key 8 9 opens and a voltage U (Fig. 2e) is received from the output of the second analog inverter 7 to the second input of the comparator 1, obtained by inverting the output voltage Us (Fig. 2d) of the peak detector 5 of the negative half-wave of the input voltage. At the same time, the voltage pulse Uio (Fig. 2h) from the output of the first reset unit 10, the voltage U4 at the output of the peak detector 4 is reset to zero.

The next triggering of the voltage comparator 1 occurs when the amplitude of the input variable voltage UBX is reached. with its positive half-life UBX. with its positive half-wave voltage U (Fig. 2e). A negative voltage drop Ui is formed at the output of the voltage comparator 1 (Fig. 2g), and the second reset unit 11 is the voltage Us at the output

peak detector 5 is reset to zero.

 50 peak detector 5 is reset to zero.

55

At the same time, the voltage pulses Ui from the output of the voltage comparator 1 and U2 from the output of the inverter 2 simultaneously open the key 8 and the second key 9 closes.

Thus, the comparator 1 voltage is triggered once with a positive, and the second with a negative input voltage half-wave, i.e. triggered with the frequency of the input signal shaper.

If the input voltage UBX. at some point in time changes (Fig. 2g), the values of the voltages U4 and Us generated at the output of the peak detectors 4 and 5, and hence the voltages Ue and Uy, alternately fed through the keys, also change by the same amount 8 and 9 to the second input of the voltage comparator 1. As a consequence, the phase of the generated pulse signal at the output of the device remains unchanged with respect to the original pulse sequence. In this case, the speed of tracking the phase of the output pulse sequence, more precisely the speed of tracking the phase constant of the output pulse signal, is not more than one period of the input sinusoidal signal of the driver.

Claims (1)

Invention Formula A pulse shaper from a sinusoidal signal containing a comparator, the first input of which is connected to the input bus and the output connected to the input of the inverto The pa, the output of which is connected to the output bus, the control input of the first key is connected to the output of the inverter, the control input of the second key to the output of the inverter, and the outputs of the keys are connected to the second input of the comparator, characterized in that, in order to increase speed, an attenuator, a peak voltage detector, a peak voltage detector, a first and a second analog inverter, a first and a second reset unit, and an input attenuator connected to the input bus, and its output Dinene with signal inputs of peak voltage and positive polarity detectors, the output of each of which is connected respectively to the input of the first and second analog inverters, the outputs of which are connected respectively to the signal input of the first and second keys, and to the input "Reset peak detectors positive and negative The polarities of the voltage are connected respectively to the output of the first and second reset units, the input of the first of which is connected to the output of the inverter, and the input of the second to the output of the comparator.