SU1677649A1 - Sinusoidal voltage measuring device - Google Patents

Abstract

The invention relates to electrical measuring technology and can be used to compensate for measuring the amplitude of a sinusoidal voltage. The purpose of the invention is to increase the measurement speed. The device contains a generator of reference voltage 1, an adjustable voltage divider 3, a comparator 6 and a counter 13. Introduction of a determiner 2 characters, keys 8, 9, 16, switch 10, inverters 4. 7, 11, driver 5, generator 12, counter 14 and the coincidence unit 15 provides a reduction in the measurement time, first of all, of low-frequency signals, due to the fact that compensation takes place at each half-period of the signal until the amplitude of the reference voltage is equal to the instantaneous value of the measured signal corresponding to phase e, at L / 2. 2 Il.

Description

ABOUT

Vj h o Ј o

Thebes 1

The invention relates to electrical measuring equipment.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams that show his work.

The device contains a shaper 1 of the reference voltage and a determinant of 2 characters, the inputs of which are connected to the input of the device. The output of the driver 1 is connected to the input of the adjustable voltage divider 3, the output of the detector 2 is connected to the input of the first inverter 4 and the driver 5 pulses, the second output of the divider 3 is connected to the first output of the device, and the first output is connected to the second input of the comparator 6, the first input of which is connected with the input of the device, and the output with the input of the second inverter 7 and the input of the first key 8. The output of the inverter 7 is connected to the input of the second key 9, the output of which is connected to the output of the key 8, to the first input of the switch 10 and the input of the third inverter 11, and the control input is with the output of the inverter 4. The control input of the key 8 is connected to the output of determinant 2, the output of the reference frequency generator 12 is connected to the synchronization inputs of the first (reverse) and second counters 13 and 14 pulses, whose outputs are connected to the first and second inputs of the block 15 coincidence, the output of which is connected to the second output of the device and through the third key 16 to the control input of the divider 3. The control input of the key 16, the reset inputs of the counters 13 and 14 are connected to the output of the imaging unit 5, the subtractive input of the counter 13 is connected to the output key 8, the summing input - with the output of the inverter 11. The second input of the switch 10 is connected to the common bus device, and the output - to the summing input of the counter 14.

The device works as follows.

The input of the device is a voltage of 3–2 pms (fmg. 2a). The former 1 generates bipolar pulses of stable amplitude Uo (Fig 2 a) and frequency 0). These pulses are fed to an adjustable divider 3, which in the initial state is set to the maximum division factor. The determiner of 2 characters forms a logical signal Ua (Fig. 26), the value of which corresponds to one for positive and zero for a negative half-wave of the signal. Accordingly, the output voltage of the inverter 4 (fmg. 2 c), g.a. at

the key 8 is open to the positive half wave, and the key 9 is negative. Comparator 6 operates in such a way that at its output a single signal Ue {FIG. 2e) if UQ Ux,

and zero if uo ux.

When the signal under study passes from a negative half-wave to a positive one at the moment to, a single signal U2 from determinant 2 opens the key 8 Us (Fig. 2g) and

closes the key 9 Ug (Fig. 2h), the Single signal from the output of the comparator 6 through the key 8 goes to the subtractive input of the counter 13, and the pulses from the generator 12 begin to be subtracted from it. At the time ti the comparator 6 flips to zero and through the inverter 11 ns counter 13 is enabled for the summation of pulses. At the time tz, the output of the comparator 6 is again set at one and the counter 13

performs the subtraction again. Thus, by the end of the low half period in counter 13, the counted number of pulses corresponds to the difference in the duration of time intervals ti, t2J and to, ti, ta, to,

This results in a counter 14 accumulating the total (pulses over the intervals to, ti to tz, TO (at the position of the switch 10, ukosan -; see fmg, 1). These codes are continuously compared by block 15 matches, output

which becomes zero when they are equal. When the signal under study passes through zero from the positive half-wave to the negative, at the output of the imaging unit 5, an impulse Us appears (Fig. 2d), which

the time of its duration opens the key 16, In the absence of equality of the codes from counters 13 and 14 (ygi tg / 6), the single signal from block 15 through key 16 reduces the division factor of divider 3, increasing the amplitude of the reference voltage. At the same time, the signal of the driver 5 resets the counters 13 and 14. In the negative half-wave in the interval to, ti, the signal from the comparator 6 through the inverter 7 U (Fig. 2e)

and the public key 9 sets the counter 13 to the subtraction, in the interval ti, tz through the inverter 7, the key 9 and the inverter 11 to the addition, and s the interval tz, to again to the subtraction. In the absence of equality of the codes of the counters 13 and 14 on the signal of the driver

5, the division factor of divider 3 is again reduced. The measurement process ends with npf, the achievement of equality of the codes of counters 13 and 14. It signals the zero signal of block 15 at the second output

devices.

If switch 10 switches to zero potential input of counter 14, then the measurement process will end when & H1 JT / 4 is reached.

Claims (1)

Claim device A device for measuring a sinusoidal voltage containing a sample voltage driver, the input of which is connected to the device input and the first input of the comparator, the second input of the comparator is connected to the first output of the adjustable voltage divider, and the first pulse counter, from which that, in order to increase the speed of measurement, a sign determinant, a pulse shaper, three keys, a switch, three inverters, a reference frequency ramp, a coincidence unit, and a second counter were entered into it. pulse, the determinant input is connected to the input of the device, and the output to the control input of the first key directly, to the control input of the second key through the first inverter, to the control input of the third key and the reset inputs of the pulse counters through / Ou o pulse generator, adjustable voltage divider input is connected to the output of an overvoltage generator, control output - with the third key output, and the second output - with the first output of the device, comparator output is connected to the input of the first key and through the second inverter - with the input of the second key the outputs of the first and second the keys are combined and connected to the first input of the switch, the input of the third inverter and the subtractive input of the first counter, the summing input of which is connected to the output of the third inverter, the input synchronization - to the output of the reference frequency generator and the synchronization input of the second pulse counter, e output - to the first input of the coincidence unit, the second input of which is connected to the output of the second counter pulses, and the output with the second output of the device and the input of the third key, the second input of the switch is connected to the common bus, and the output to the summing input of the second pulse counter.