SU1246348A1 - Device for detecting failure of generator - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in synchronization and control devices when backing up and monitoring the performance of generators. The purpose of the invention is to increase the reliability of the control. For this, a device containing block 1 start-up, counter 6, logic elements 2.3, bus 10, main signal 11, reference signal, output bus 14, input element 4, triggers 7.8, bus 13 interrogation and start, elements AND-NOT 5.9. In order to ensure the continuity of control, a delay element 16 and an OR 15 element are additionally introduced. The start block 1 consists of frequency divider 17, trigger 18, element AND 19. The diagram shows: 20, 21 — outputs of triggers, 7, 8, 22 - output of start-up unit 1, 23 - counter input. If continuous monitoring is necessary, the links shown in the figure by a dotted line are entered. 1 hp f-ly, 2 ill. i (Л .11 23 .I I 1-я 20 г- 5 2Т f3 8yАоЗ 14 And ts9 Ш Р 00 4 СХ)

Description

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The invention relates to an impulse technique and can be used in synchronization and control devices for reserving and controlling the operability of generators.

The purpose of the invention is to increase the accuracy of control, as well as to ensure the continuity of control.

FIG. 1 shows a functional diagram of the device; FIG. 2 - timing charts of the device.

The device contains 1 startup unit, AND 2–4 logic elements, AND-HE 5 elements, counter 6, triggers 7 and 8, AND-HE element 9, input terminals Yu – 13, output bus 14, element OR 15, and element 16 delays. Launch 1 consists of frequency divider 7, trigger 18, and element 19. There are also indicated outputs 20 21 triggers 7 and B, output 22 of start unit 1, input 23 of counter 6.

The input of the start-up unit 1 is connected to the main signal bus 19, and the output is connected to the input of the first logic element 2, the second input of which is connected to the reference signal bus 11 and the output is connected to the counting input of the counter 6, whose outputs are connected to the inputs of the second logic element 3, the output of the second NAND logic element 9 is connected to the output bus 14, one of the inputs to the polling bus 13 and the other to the output of the first NAND logic element 5 connected by one of its inputs to the forward output of the first trigger 7 whose input is connected to the output logical element, and another input the first logical element AND-NOT 5 is connected to the inverse output of the second trigger 8, the input of which is connected to the output of the logical element I 4 connected by its inputs to the outputs of counter 6, the first and second logical elements being in the form of elements I. The startup unit 1 is executed in the form of a trigger 18, the first input of which is connected to the bus 10 of the main signal, the output to the first input of an AND 19 logic element, and the frequency divider, whose input is connected to the output of an AND 19 logic element, and the output a second input flip-flop 18, the second input of AND gate 19 is connected to the trigger bus 12 and the output tri1 ger

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18 to the output 22 of the startup block 1. The device additionally introduces a delay element 16 and an OR element 15, one input of which is connected to the output 22 of the startup block 1 and through the back element 16, the holders to the inputs of the installation in O of the counter 6 and the trigger 7 and 8 and the other input is connected to the inverse E1OUT of the second trigger 8, and

.the output to the interrogation bus 13, the buses of the main signal 10 and the start 12 are interconnected.

The device works as follows.

During normal operation of the generators on the Start signal on the bus 12 trigger 18 block. 1 start is tilted and impulses from the bus 10 arrive at the input of the divider 17 through the element I 19

the main signal, and the counting input 23 of the counter 6 through the element And 2 receives pulses from the bus 11 of the reference signal. After a certain number of pulses on the bus 10 of the main signal, the overflow signal at the output of the frequency divider 17, the trigger 18 returns to its original state and the logical zero at the output 22 of the start-up unit 1 prevents the passage of voltage pulses to the counting input of the counter 6. Pulse counting from the bus 11 the reference signal is terminated. At the same time, at the outputs of counter 6, a code is set,

proportional to the frequency of the generator. The inputs of the And 3 element are connected to the outputs of the rocket 6 in such a way that a signal appears at its output with a code value equal to the lower frequency limit of the generator, and the inputs of the And 4 element so that its output appears with a code value equal to the upper limit of the generator frequency.

If the obtained code value in the counter 6 corresponds to the permissible value of the generator frequency, then in the process of counting at the output of the element I 3: a pulse is generated and the trigger 7 is tilted. Thus, at the inputs of the element AND-NOT 5, signals of logical units are set, and at its output - a signal of logical zero. When a signal arrives, and the polling bus 13 on the device bus 14 retains the signal of a logical unit, indicating that resiepaTopa

If the received code value in the counter is less than the permissible frequency value, then trigger 7 is not displaced and a logical zero signal remains at its output. Consequently, the signal of a logical unit is generated at the output of the AND-HE element 5. If the obtained code value in the counter 6 is greater than the permissible value of the generator frequency, then the output of the element 4 during the counting process shows the signal tipping the trigger 8, and c. its output to the input element AND-NOT .5 receives a logical zero signal. At the output of the element AND-NOT 5 a signal of a logical unit is formed.

When a signal is received from the interrogation bus 13 on the device bus 14 in the last two cases, a logical zero signal is generated, indicating a generator failure.

Since the frequency of the pulses on the buses of the main Yu and reference 11 signals is close, and several frequency periods are required for generating the code in counter 6 with the required accuracy, frequency divider 17 is used from the reference input in start block 1.

If necessary, continuous monitoring is introduced, the connections depicted by the dotted line (Fig. 1). Then, the pulse 18 overturns from the pulse from the bus 10 of the main signal and the device continues to operate as before. When Trigger 18 returns to its initial state, a signal from the output 22 of the launch unit 1 through the OR element 15 generates a signal to the polling buses 12 and counts the element 6 and the triggers 7 and 8 through the element 16. A signal to the polling bus is also generated when the trigger is skipped eight-. After the trigger 18 is set to the zero state, with the first impulse from the main signal of the main signal, it reverses and the operation cycle repeats.

Claims (2)

1. An apparatus for detecting a malfunction of the generator, comprising 246348 -4 a triggering unit whose input is connected to the main signal bus, and the output to the input of the first logic element, the second input of which is connected to 5 by the reference signal bus, and the output with a counting input of the counter, the outputs of which are connected to the inputs of the second logic element, and an output bus, characterized in that 10 -that, in order to increase the reliability of control, the logical element AND, two triggers, interrogation and start bus, the first and second logical elements AND-NOT, the output of the second logical element AND-NOT connected to the output bus, one of the inputs - to the interrogation bus, and the other to the output of the first NAND logical element connected by one of its own 20 inputs to the forward output of the first trigger, the input of which is connected to the output of the second logic element, and the other input of the first logic element IS NOT connected to the inverse 25 to the output of the second trigger, the input of which is connected to the output of the logical element I, connected by its inputs to the outputs of the counter, the first and second logical elements 30. Made in the form of elements And, and the start-up unit is executed in the form of a trigger, the first input of which is connected to the start bus, the output to the first input of the logical element And, and the frequency divider, the input of which is connected to the output of the logical element And, and the output to the second trigger input, the second input of the AND gate is connected to the main signal bus, and the trigger output is connected to the output of the trigger unit. 2. The device according to claim 1, which is to ensure that, to ensure continuity of control, a delay element and an OR element are additionally introduced into it, one input of which is connected to the output of the trigger unit and through the delay element to the installation inputs About the counter and triggers, the other B1SOD is connected to the inverse output of the second trigger, and the output is connected to the interrogation bus, with the main signal and start buses interconnected. 35 40 45 50 FIG. 2 Compiled by EdSurov Editor N. Bobkova Tehred L. Oleinik Proofreader M. Sharoshi Order 4020/54 Circulation 816. Subsidy VNIIPI USSR State Committee on affairs of inventions and otkrypgy 113035, Moscow, Zh-35, Raushskgda iab., d. 4/5 Production and printing company, Uzhgorod, st. Project, 4