SU1246295A1 - Device for controlling three-phase inverter - Google Patents

Abstract

This invention relates to electrical engineering and can be used in BToiJH4Hbrx power supplies. The purpose of the invention is to increase the quality of regulation of the output voltage. The device contains a master oscillator 1, a pulse-phase control unit 4.1, a ring register 8, a logic unit 9. The introduction of a control unit (CU) 2.1, a generator of 3 tick, modulation and filling pulses, a T-flip-flop 5 to the elements Both 6 and 7 allow you to change the modulation frequency of the output voltage curves as a function of the output frequency; inverter. In the upper frequency range there is a limited regulation of the output voltage with the same quality of the output electric energy, BU 2.1 is performed on registers 2.2 and 2.3 of the reference codes and 2.4 registers of the tasks. Registers are generally reversible counters, information in which can be recorded either in automatic or in manual mode. The operation of the control device can be coordinated with the digital control computer using the above program. 3 il. (L and N9 I; D SP

Description

The invention has slopes to converter technology and can be used in secondary power sources with a quasi-sinusoidal output three-phase voltage.

The purpose of the invention is to improve the quality of regulation of the output voltage of the inverter.

Figure 1 shows the functional diagram of the device; figure 2 - diagram of the inverter; FIG. 3 is a graph of inverter output voltage and control signals.

The device contains a master oscillator 1, block 2.1 control, coc

thirty

from the 2.2 n 2.3 registers of the reference codes and the 2.4 registers of the reference, two 2.5 and 2.6 elements of the comparison and the 2.7 element, the driver of the 3 clock pulses, modulation and filling - 2 nd pi 4.1 pulsed phase block - equal, consisting of RS-trigger 4.2 / element And 4.3, counter 4.4, adjuster 4.5 of the control angle of the comparison element 4.6, T-flip-flop 5 elements-25 you And 6 and 7, ring register, 8, logical block 9, amplifying and decoupling unit to,

The inverter (fig. 2) contains the main unit 5 assembled on fully controlled keys 11–16, the auxiliary unit assembled on fully controlled keys 17–22, the blocks connected in series using transformers 23–25.

Fig. 3 shows the curve () of the linear voltage of the main unit of the inverter, the curves (.i) of the linear voltage Ug., P U., the auxiliary unit of the inverter, the curve (|) of the resulting linear voltage

i.i., - u ,, j.

The device works as follows.

Two elements 2.5 and 2.6 of block 2.1 control the values of the code codes G-Code and Code-2, recorded in registers 2.2 and 2.3, and the code of the task recorded in register 2.4, Registers

35

40

If the signal P1 is present, which corresponds to the upper value of the inverter output frequencies, the modulation frequency t 12 at the outputs of the shaper 3 and the filling frequency is f m12f. With a single P2 signal, the frequencies of f 24f and f 1 m24f 5 are formed at the outputs of form rotator 3, and at a signal of the RE f 48f and f m48f. Consequently, the modulation frequency f and the frequency f, change to the function of the output frequency of the inverter.

The signal at a frequency of 12 from the first output of the imaging unit 3 is supplied to the 12-bit register 8. On its output, alternate single-unit signals of equal duration are formed, which appear in block 9, the Inverter output voltage period (Fig, 32) is divided into 12 clocks intervals I-XII,

On block 4.1, signals f and f „are received from shaper 3. The 4.5 key contains the code of a number proportional to the value of the output voltage of the inverter.

Pa. Consider the operation of block 4.1 at the fundamental modulation frequency of 12 f. At each clock interval (s of signals f 12 to the input of trigger 4.2, the pulse triggers proportional to the duration of the output voltage.) With the trigger 4.2 set to one, the element 4.3 is open and the pulses are filled with a frequency f 12mf begin to flow through it, into the counter 4.4. At the moment of equality of the codes of the numbers recorded in the setpoint 4.5 and the counter

2.2-2.4 set the output frequency of the inverted-output element 4.6 manifests a pulse resetting the trigger 4.2 and the counter 4.4 to the zero state. When the modulation frequency fn is received at block 4.1 equal to 24f and 48f5, the filling frequency in24f or m48f is set accordingly. On the other hand, caMMvi on each clock interval triggers 4.2 either form two or Jm6o four pulses.

torus or magnitude of the output voltage. Let the intermediate values be recorded in registers 2.2 and 2.3, and the current specified value of the output frequency of the inverter of the torus in register 2.4. In this case, the entire output range is often “- the inverter will be divided into three subranges, each iy of which will correspond to a single value

P1, P2, RZ signals at the outputs of the block 2.1 a, Signal generation conditions for

P1 f, f

f), f. No. Ag

S

0

about 5

five

0

for P2

f if -WAI

for RZ

Under the influence of the signals of the master oscillator 1 and the signals of the block 2.1, the driver 3 produces a clock frequency of 12 fs where f is the output frequency of the inverter, as well as the modulation frequency f and the filling frequency f ..

If there is a signal P1, which corresponds to the upper value of the output frequencies of the inverter, at the outputs of the formers 3, the modulation frequency is t 12f, and the filling frequency is f m12f. With a single signal P2, the frequencies f 24f and f 1 m24f 5 are generated at the outputs of the imaging unit 3, while the RE signal f 48f and f m48f. Consequently, the modulation frequency f and the filling frequency f are changed in function of the output frequency of the inverter.

The signal at a frequency of 12 from the first output of the imaging unit 3 is supplied to the 12-bit register 8. On its outputs, alternately, single signals of equal duration are formed, which appear in block 9, the Inverter output voltage period (Fig, 32) is divided into 12 clock intervals I-XII,

On block 4.1, signals f and f „are received from shaper 3. In push-button 4.5, a code of a number proportional to the value of the output voltage of the inverter is stored.

Pa. Consider the operation of block 4.1 at the fundamental modulation frequency of 12 f. Upon receipt of each of the clock intervals (s of signals f 12 to the input of the trigger 4.2, the trigger produces a pulse proportional to the duration of the output voltage of the voltage. With the trigger 4.2 set to one, the element 4.3 is open and the pulses are filled with frequency f 12mf begin to flow through him, into the counter 4.4. At the moment of equality of the codes of the numbers recorded in the setpoint 4.5 and the counter

 at the output of element 4.6, a pulse appears, resetting the trigger 4.2 and counter 4.4 to the zero state. When the modulation frequency fn is received at block 4.1 equal to 24f and 48f5, the filling frequency in24f or m48f is set accordingly. At that caMMvi, at each clock interval, trigger 4.2 generates either two, Jm6o four pulses.

The pulses produced by trigger 4.2 arrive at block 9 and, under the influence of the 12-channel system of output signals of register 8, act as control pulses for a kg clock interval simultaneously to six inverter power switches, in accordance with the algorithm

With the help of T-flip-flop 5 and elements 6 and 7, key control pulses are generated, ensuring zero voltages at the outputs of the inverter. This is achieved by applying to the input of the trigger 5 a frequency 12f and connecting the first inputs of elements 6 and 7 alternately to the direct and inverse outputs of the T-flip-flop 5, and the second inputs to the inverse output of the flip-flop 4.2. Produced by the elements 6 and 7, the signals also arrive at block 9.

With the aid of block 9, the 12-channel voltage system of register 8 is modulated by the duration of the trigger signal 4.2 and the sequences of pulses Y,, are generated. . . , Y, P: wired through the amplifying and decoupling unit 10 to the inputs of the power switches of the inverter.

The number of pulses in the linear voltage of the inverters and in the output voltage.: The operating voltage, as seen in Fig. 3, is two, i.e. is given for the average output hour-y range, when the carrier frequency is f 24f and the filling frequency is f m24f. In the device in question, the number of pulses generated at each clock interval can be set to 1.2.4.

The proposed device allows the frequency of modulation of the output voltage curves to be varied as an output frequency function of the inverter. In the upper frequency range, there is a limited regulation of the output voltage with an increase in the quality of the output electrical energy.

The registers are generally reversible counters in which information can be recorded either in automatic or in manual mode. The operation of the device for controlling the inverter can be coordinated with the digital control computer.

Claims (1)

Invention Formula i 2 , -. .,five A three-phase inverter control device comprising a driver 2954 generator, pulse-phase unit control, the ring register, the outputs of which are connected to the first inputs of the logic unit, whose inputs through the amplifier-decoupling unit are connected to the top of the device, about p10 15 20 :, th . - 50 35 40 55 In order to improve the quality of regulation of the output voltage of the inverter, it is equipped with a control unit, a pulse shaper, modulation and pulse generator, a T-trigger and two AND elements, the control unit contains two comparison elements, two reference code registers, an instruction register for the And element, the pulse-phase control unit contains an RS-trigger, a counter, an And element, a control angle setter and a comparison element, and in the control unit, the outputs of the registers of the disputed codes are connected to the first inputs of the comparison elements, the second inputs which are connected to the output of the reference register, the first output of the first comparison element is the first BE: the control unit input, the second output of the first comparison element and the first output of the second comparison element are connected via the AND element to the second output of the control unit, the third output of which is the second output of the second comparison element, in the pulsed-phase control unit, the first input of which is S-r. RS trigger module, the direct and inverse outputs of which is the first and second outputs of the pulsed-phase control unit The second input of which is the first input of the AND element, the second input of the Koi oporo is connected to the forward output of the RS flip-flop, the output of the AND input is connected to the first input of the reference element via a counter, and to the second input of which the output of the control angle adjuster, vpsod the comparison element is connected to the R-BXO by RS-trigger and the installation input of the counter, the output of the master oscillator is connected to the clock input of the clock, modulation and filling pulses, the control inputs of which are connected to the outputs of the control unit, output Connected to cycles vhodam annular register and T trig- reps, outputs modulation and filling are connected to first and second inputs of the block pulse-phase control, pervsh vpsod which is connected to the second input of the logic unit, vtoS .12462956 the swarm output is to the first inputs of the elements with the third inputs of the logical block I, the second inputs of which the connection of which is defined to the output from the outputs of the T-flip-flop, the outputs to. . Y, X, 5 (X vX vX3vX vXjVX,) vX ,, (, vXfVX vXgVX ,,); 8 9 V X ,, VХ, d) VX, / X V X, v X, v X,); 3 X, 5 (, v / X, v / X, vX, vXjVX, / X, vXvX5VX, vXgVX);  ; Y, ..V. Y, X ,, (X, vX ,, vx, yX, pvX, / XvX ,, vXgVX); Y, X ,, (XjVX, vKK5VX, vX, vXg) VX (. Y, X ,, (X, vX, vXjVX, .X,) vX (X, vX, vXjVX, vXgVX P; Yj X, 5 (, VX, VX5VX ,,) VX (, VXgVX, vX, p; Y9 X, (X vX vX5VX vXgV:, (X, vXзVXJvX, vX5vX ,,); Y, o V..P i / j VXftVX vX,) ;, Y, X vXjV XjV XgV X ,,) (X, V XjV XjV X / XgV X); Y, 7 5 (WVW ,,, VX ,,),, - signals of elements And; - signal on the first output of the pulse-phase control unit Y, one , Y - output signals of the lo -.- gi, ical block; . X output signals Ring Register: 20 ra;  : laziness. Compiled by V. Mironov Editor V. Petrash Tehred V. Kad-ar Proofreader V. But ha Order 4017/52 Circulation 631 Subscription VNIIPI USSR State Committee on inventions and open) ai 113035, Moscow, F-ZZ Raushsk nab. d. 4/5 . Production and printing company, Uzhgorod, Projecto st., 4,