SU1246282A1 - Device for controlling frequency converter - Google Patents

Abstract

This invention relates to the field of electrical engineering and can be used in frequency converters. The purpose of the invention is to improve the shape of the output voltage while providing a wide range of output frequency control. The device сt holds the digital frequency adjuster 1, the outputs of which are connected to register 2 of the output frequency code (RCWF) and to register 3 of the multiplicity code (RCCH). The output of REFR 2 is connected to the input of the master oscillator 4, the output of which is connected to the multivibrator 5. The control switch 6 connects the time to the resistor to the waiting multivibrator 5. The code with RSC 3 is fed to the inputs of the reversible counter 7, to the subtracting input of which pulses are received from the standby multivibrator 5. The output of the reversible counter 7 is connected to the counting input of the address counter 8, the outputs of which are connected to the address inputs of a permanent storage device (ROM) 9. Younger the address bit of the ROM 9 is connected to the output of the multivibrator 5. The code from the output of the ROM 9 is fed to the control circuit of the force (L tsD 4a O5 S 00 to Figure 1)

Description

the output keys of the frequency converter, the Output Frequency Knob 1, controls the operation of the master oscillator 4, and the output frequency range is divided into a number of subbands. The output frequency adjuster 1 using the microprocessor device included in it performs the calculation of the code of the pulse period at the output of the master oscillator

The invention relates to electrical engineering and can be used in the design of frequency converters, for example, for frequency control of electric drives operating in a wide range of rotational frequencies.

The purpose of the invention is to improve the shape of the output voltage while providing a wide range of output frequency control.

FIG. 1 is a functional block diagram of the control device in FIG. 2 shows a single-phase direct frequency converter circuit on a fully controllable 1 st key with two-way conductivity; Fig. 3 shows timing charts explaining the operation of the frequency converter control device; in fig. 4 shows an embodiment of the control device.

The device (figure 1) contains a digital frequency adjuster 1, the outputs of which are connected to the register 2 of the output frequency code and to the register 3 of the multiplicity code. Register 2 of the output frequency code is connected to a master oscillator (DG) 4, the output of which is connected to the waiting multivibrator 5. Controlled switch 6 connects the time to the master multivibrator 5 to the master resistors. The code from the register 3 is fed to the inputs of the reversible counter 7, to the subtracting input of which pulses are received from the waiting multivibrator. The output of the counter 7 is connected to the counting input of the address counter 8, the outputs of which are connected to the address inputs of a constant

torus 4 and the multiplicity code, depending on the frequency of the voltages at the outputs of the frequency converter. Moreover, at lower frequencies, large values of multiplicity codes are selected, which decrease as the output frequency of the converter increases. The device implements a pulse-width control mode. 4 il.

memory device (ROM) 9. Junior address bit ROM 9 is connected to the output of the multivibrator. The code from the ROM output goes to the circuit.

control power switches 10-15 frequency converter 16 (figure 2).

In addition, in FIG. 4, microprocessor 17, generator 18 clock pulses, ROM 19 commands,

20 state register, bus driver 21, RAM 22, subtraction counter: 23.

The device works as follows.

The 1-output frequency adjuster controls the operation of the master oscillator 4. The output frequency range is divided into a number of subbands, since the IF applies multiple

pulse width control

(ШИ1). Each subrange corresponds to a certain factor of multiplicity K. The number from the output of the setter is entered into register 2 of the output code

frequency. From the register, the code of the output frequency, tots is fed to the digital input of the master oscillator 4, which produces a frequency

thirty

1: ,, 6К. f + 300 Hz,

ГIttLfv f

I EXIT

where f jj. - frequency of the master oscillator;

-8th frequency inverter; TO; - coefficient of multiplicity.

1 1G pulses start the standby multivibrator 5, the output of which is a series of pulses following

frequency equal to

: and duration i,

TO

Where

1 ™

pulse duration at the output of the waiting multivibrator at a given multiple: T.K .; if, is the pulse duration

at the output of the waiting multivibrator dp multiplicity K., G.

When switching from one sub-band of the output frequency to another, the multiplicity factor changes. The defined value of Kj corresponds to the code value at the outputs of register 3. Ratio

Yc

1 to g is provided by the selection of the corresponding resistances of the time of the driving resistors of the switch 6, which is controlled by a code received from the multiplicity code register. The signal from the output of the waiting multivibrator 5 post10

462824

It goes to the low-order bit of the address input of the ROM 9 and determines the state of the Dauz frequency converter or voltage pulse. - The signals from the multivibrator 5 are also fed to the subtracting input of the reversible counter 7. The pre-recording input of the counter 7 is received. A transfer signal is received, while the multiplicity code from the output of the register 3 is written in parallel. The signal from the output of the reverse transfer of counter 7 enters the counting input of the address counter 8. The code from the address counter 8 arrives at the higher bits of the address inputs of ROM 9. Each of the binary codes on the address inputs of ROM 9 corresponds to a specific code on the outputs, which determines the combination on chennyh power

frequency converter keys.

 Table 1 for keys 11-15 shows the output code of the ROM U, depending on the status of the address counter.

15

20

A value of 1 at the outputs of 10-15 ROM 9 corresponds to the signals for switching on the power switches 10-15 of the frequency converter 16.

t

Table 1

As follows from the state diagram of the power switches, in some states of the address counter (e.g., even), these keys form a pulse of the output voltage; and in other states (odd), the voltage pause. Thus, in the proposed device, a pulse-width adjustment mode (WID) is realized.

One of the possible options for the implementation of the control system of the inverter is presented in figure 4.

The setpoint 1 output frequency is implemented using a microprocessor device based on, for example, a K580 series microprocessor set. The microprocessor device implements the multiplicity code and calculates the pulse period code at the digital-type output, which in turn consists of a high-frequency reference generator, pulses G, and a multi-bit subtraction counter CT.

The microprocessor device of the output frequency sensor 1 calculates the code of the pulse-following period at the output of the SG in accordance with the expression

N,

one

6K; - Nf, +300

where NP is the pulse period code on

ZG exit;

N is the code of the output frequency of the inverter; K - coefficient of multiplicity.

This code is entered into register 2 and is rewritten into subtractive counter 23 by a transfer signal received at the pre-recorded input.

at the moment when the number equal to zero appears in the subtracting counter 23, P1 from the generator G, the subtracting input decreases the content of the subtracting counter and at the moment when it becomes equal to zero, the N code is written to the subtracting counter 23 and the process is repeated.

Element 17, which can be used as a standard screen processor K580 F 80, receives signals from an 18-clock pulse generator. Element 17, in accordance with the program I, recorded in the ROM 19 of the commands, outputs Sh1 information containing a certain value of the frequency period code and the corresponding value of the multiplicity code K | to the data bus. In addition, this information contains control words that are stored in the state register 20. Data via bus driver 21 is fed to external devices and memory. The multiplicity code and frequency period code are stored in register 2 of the output frequency code and in register 3 of the multiplicity code contained in the programmable parallel interface (for example, standard} 1st element CR580BB55), Element 22 is the RAM that is needed to store accurate calculation results.

In Table 2, as an example, the calculated values of the frequencies f of the master oscillator for different subbands are given. The calculations are performed for a direct frequency converter connected by zero and bridge circuits. The NFC provides power to the motor windings.

table 2

The microprocessor-based sensor I of the output frequency calculates the required multiplicity code K, depending on the frequency of the voltages at the inverter outputs. Moreover, at lower frequencies, large values of multiplicity codes are chosen and reduced as the output frequency of the frequency converter increases.

Claims (1)

Invention Formula A device for controlling the frequency converter, containing the output frequency setpoint, connected to the master oscillator and the address counter connected to the upper address inputs of the permanent memory device programmed according to the control law, and its outputs are connected to the corresponding control circuits of the power switches of the converter, in contrast to the fact that, in order to improve the shape of the output Continuation of table 2 voltage while providing a wide range of output frequency control, it is supplied with a register of the code the frequency, the short code register, a control switch and a reversible counter, the subtracting input of the reversible counter connected to the output of the waiting multivibrator connected to the MP address input of the permanent storage device, and the output of the register of the multiplicity code to the information input of this counter, connected via a controllable switch with the time setting input of the standby multivibrator, the information input of this register is connected to the output of the output frequency setting device, which through The output frequency code register is connected to the information input of the master oscillator, the output of the latter is connected to the input of the waiting multivibrator, and the output of the reversible counter is connected to the counting input of the address counter. Fig.Z FIG. Editor V. Petrash Compiled by V. Bunakov Tehred O. Sopko Order 4016/51 Circulation 631 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader A.Zimokosov