SU987579A1 - Programme-control device - Google Patents

Description

The invention relates to aBToMatHr ke and is intended to control the atomization mode of atomic absorption spectrophotometers, and can also be used in various installations, the control circuits of which

require a sequence of signals determined by predetermined laws.

A device is known in which a programmed controller generates control pulses in a repeating time sequence used by the on-board unit of contactors to turn the device on and off. Between pulses of short duration there are intervals for manual control of the block. com contactors. The system can be used to control motors or solenoid closhes 1.

It is also known that the .nporpciMHoe setting device contains a block of a set of time intervals, an adder, a comparison block, a time master, a program switch, and an encoder that can only be used to automatically turn on hardware in

preset time with a high point. 2.

The closest to the invention is a programmable device with digital indication and analogue output, which contains a series of pairs of decade switches, stepping, register, time counter, time setting device with counter,

10 digital-to-analog converter, valve circuit. The device controls the evolution of a quantity as a function of time by the same or different linear increments.

15 steepness 3.

However, the device does not have the ability to set the gradient of the output function, the accuracy is low and, as a result, it is not applicable to control the atomization mode of an atomic absorption spectrophotometer.

The aim of the invention is to improve the accuracy of the device.

The goal is achieved

25 in that a control device comprising a pulse generator, an output connected to the first input of the control unit, the first output of which is connected

30 with the first inputs of the fixed memory unit, the second output with the first inputs of the RAM unit, the second inputs of the control unit connected to the third output and the second inputs of the permanent memory unit, the reversible counter, the output connected to the input of the digital-analog converter and first. the input of the comparison unit, the driver; signals, an output connected to the third input of the RAM, and a block time, entered a code converter, an operator console, a frequency divider with a variable division factor, first and second registers and a control and display unit, the output connected to the operator console, and inputs respectively, with the outputs of the control unit, the signal conditioner, the code converter, the time of the master unit and the reversing counter, whose input is connected to the output of a frequency divider with a variable division factor, the first input connected to the output of the comparator unit, the second input — with the output of the second register, the third input — with the output of the pulse generator, the fourth input with the fifth output of the control unit, the first input of the first and second registers and the first input, specifying the iO current, the second input of which is connected to the first the output of the code converter, to the second input of the first and second registers, the third input to the output of the pulse generator, the fourth input to the output of the comparing unit, the second output the time of the master unit connected to the second input of the control unit and, by the third inputs of the operator console co-connected with the first outputs, the second output of which is connected to the third input of the RAM through the driver and the first and second outputs of which are connected to the first and second inputs of the code converter, the first and second outputs of the constant block, respectively, and the third output - from the device's output. FIG. 1 shows a functional block diagram of the device; Fig. 2 is a diagram explaining the operation of the device; in fig. 3. is an example of a functional block diagram of a control unit; Fig. 4 is a diagram illustrating the operation of the control unit; in fig. 5 is a block diagram of the register, and the frequency divider in FIG. 6 shows the timing of the master block; in fig. 7 is a diagram of the control and display unit. The device contains a control panel 1 operator, a driver .2 signals, a control unit 3, a main memory unit 4, a fixed memory unit 5, a 6 kbda converter, a time master unit 7, the first 8 and second 9 registers, a frequency divider 10 with variable factor, reversible counter 11, digital-to-analog converter 12, comparison unit 13, pulse generator 14, control and display unit 15. The control unit 3 (FIG. 3) contains the first 16 and second 17 one-shot, pulse counter 18, element OR 19, converter 20, synchronization node 21, trigger 22, element 23, counter 24, decoder 25, (Switch 26, block of elements And 27, element OR 2B, trigger 29 and element And 30. Blocks 9 and 10 of Fig. 5). consists of a register of 31, a divider counter 32 frequency, trigger 33, elements And 34 36, inverter 37. Block 7 contains a register 38, counter 39, element And 40, a trigger. 41, the element OR 42 and the divider 43 frequency. Block 15 (Fig. 1) contains the switches 44 and 45, the decoders 46 and 47, the counter 48 and the generator 49 of the reference frequency. A single vibrator 16 is designed to form a single pulse when the operator dials a step number on the operator’s console, Single vibrator 17 is used to generate a pulse when the device starts up (chart t.r of Fig. 4), and counter 18 is used to generate the address of memory cells. When the program is entered, the clock pulse to the counter 18 comes from the one-shot 16, and when processing the program from the element OR 19, which receives the device start signal, as well as the signal from the time of the setting device 7, which is the signal of the end of the previous stage. The converter 20 PE is designed to provide information about the stage number to the control and display unit 15 in a binary-tenable code. The node 21 of the sync signals is designed to form from the pulses coming from the generator 14 (CJ diagram), sequences of pulses shifted relative to each other diagram-5, B, Fig. 4 J. The trigger 22 serves to issue a resolution signal (diagram 9, fig. 4) for the passage of pulses B through the circuit 23 to the counter 24 (diagram e. The counter 24 is designed to determine the number of cycles of the shaping signals of the recording and sampling program. is a counter for four states, three of which determine three such signals, corresponding to the sample signals (g) and records L k) of the program, and the fourth state is used to form

trigger signal (diagram d, figure 4) frequency divider 10.

The indicated states 3 are formed by the decoder 25 and are used for sampling the memory, and also are resolution signals for generating from pulses in the recording signals to the selected words. The output signal of the decoder is used to form the recording signal of the next stage E.

The switch 26 is intended for transmitting signals, sampling s, generated in the decoder, to block 4 in the case of working with RAM, and to block 5 in the case of working with permanent memory. Sampling of one of these two modes is carried out by two signals (Experiment and Automat, served from the operator console.

The trigger 29 is designed to form a permission signal for the passage of pulses through the element 30 to the block of elements 27 only after the first impulse 5 passing to the counter 24. This ensures the temporal relationship between the sample and write signals.

The control unit is reset by a Reset signal from the operator console.

When entering the program for each stage (from the first to the sixteenth, the one-shot 16 produces one pulse, and counter 18 the address of the memory line selection. From the operator's console, switch 26 transmits to block 4 three column sampling signals (diagram h) corresponding to three parameters the completion of the input of parameters from the operator console, the one-shot 17 receives a trigger, which corresponds to the first address of the memory line, and the signals shown in FIG. four .

In the following, the trigger signal for generating the next address and generating the signals shown in FIG. 4, is a pulse signal coming from the time of master block 7, which corresponds to the current stage.

The device provides a sixteen-step change in the output signal set by the operator or automatically by the program.

The RAM block 4 is designed to accumulate, store information about the parameters of the function performed by the device and output data, and contains three columns built on high-speed memory elements.

The block 5 of the permanent memory is intended for storing information about the three parameters of the functions implemented by the device in the Automatic mode.

Memory blocks 4 and 5 contain sixteen binary-decimal bits, the sixteenth bit through block b (Fig. 1) is fed to the input of the register

31c gradient sign.

This bit determines the mode of operation of the reversible counter 11 (Fig. 1). in the case of a single bit state, the output of the divider

32 frequencies through the element I 35 is fed to the input of the forward stroke of the counter.

and in the case of a zero state, to the entrance of the reverse stroke. In the future, depending on the value of the sign bit, the pc: hier operation mode for each stage changes.

The converter 6 combines information from blocks 4 and 5 according to the wired OR scheme and transmits it to block 15 and to the control object, as well as converts binary-binary code to binary code and transmits the timing block 7 and registers 8 and 9 for a time.

Block 7 is the time setting of the block (timer) and is intended for

determine the duration of flat sections of the diagram (Fig. 2).

The register 38 of block 7 is built on the elements K 1557IE7, representing

are counters with pre

installation, which makes it possible to use them as buffer storage elements. The counter 39 is built on the elements K155IE2 and is designed to receive the time value in a binary-decimal code with the subsequent issue to the control and display unit 15 (Fig. 1).

The device works as follows.

in a way.

After starting the programmable device for the time of action of the third signal (Fig. 4) intended for sampling the trigger of the memory column, the input of the register 38 contains information about the time duration of the flat sections of the diagram (Fig. 2), the third signal to (Fig. 4) is a strobe signal for

register 38. The countdown in seconds begins at the completion of the growing part of the diagram, (FIG. 2). At this moment, trigger 41 from block 13 of the cxeNBJ comparison (Fig. 1 receives a signaling (pulse) throwing trigger in a single position. As a result, register 38, which is already a counter in the reverse mode, and counter 39, through element 40 from the block 14 (fig. 1) is pulsed

sequence with a frequency of 1 Hz. At the moment of zero register 38, a transfer pulse is emitted, which, through the OR element 42, enters the zero setting of the trigger 41 and the counter 39,

and the account is terminated. The same impulse. arriving at block 3, is the trigger for the next stage. For a flat section of the following step, the operation of the circuit. Will be similar. Registers 8 and 9, representing the trigger scheme, are used to receive data, respectively, on the size of the output function and on the gradient function at each stage. A variable frequency divider 10 with a variable division factor is intended to receive pulsed series of different frequencies. The output reversible counter 11 is designed to obtain the code value of the current value of the output signal. The mode of operation of the counter (forward or backward) is determined in advance for each step of the program, since the circuit is given using a single cell K155IE8 and, therefore, the definition of the output frequency of frequency divider 10 (Fig. 1 and the table of code values of the gradient functions are given For this case, at a clock frequency of 1000 Hz, Fig. 5 shows a functional block diagram of register 9 and frequency divider 10 with control circuits. In the initial state, the inputs of frequency divider 32 are in the zero BOM state; locked up Element 34 is also fed to the counting input. After starting the programmable device, first register-31 receives a write-to-pulse (Fig. 4), which records the binary value of the gradient of the functions (coefficient M) selected by signal 3-1 ( Fig. 4) from the memory block. After completing the recording of the information of the remaining two parameters; (the value of the output function — temperature and holding time) in registers 8 and 7 (Fig. 1), the recording signals k-1 and kz on the trigger 33 signal l (fig. 4), is the signal from the node being written and, thus, the beginning of the programmable device operation according to the diagram (Fig. 2; frequency divider 32 to the elements 35 and 36 begins to produce a pulse sequence with a frequency corresponding to the coefficient M in the formula l m M -ef- A digital-to-analog converter 12 is designed to convert the output digital signal to a corresponding analog value and contains the actual DAC with an operational amplifier at the output. Comparison unit 13 is a logic circuit of the same modulo-two and is designed to emit a start-up signal of the setting device at the moment when the set value of the output function is reached. The 14-pulse generator generates stable frequency square-wave pulses. The control and display unit 15 (Fig. 1) provides the generation of signals for ten seven-segment indicators located on the operator panel 1 (Fig. 1). Four of these indicators serve to highlight the value of the output function (in our particular case the temperature values, four to highlight values, the three parameters of the output function (temperature J, the exposure time and the gradient of the output function. Switch 44 (Fig. 7) is built on the Elements, К155КП7 and is intended for switching signals from blocks 2, 6 and 7 (Fig. 1), carrying the corresponding information. The address of the corresponding mode is determined from the operator console 1 using a key switch through block 2 of FIG. one). The outputs of the switch 44 are information for the last four seven-segment indicators indicated,. The switch 45 is built on the elements of K155KII1 and is intended for switching the information of the mentioned ten seven-segment indicators. For all seven-segment indicators, information is fed in parallel from the decoder 46, and the selection of the corresponding indicator is carried out using the decoder 47, ten outputs of which are used to control the anode circuits of the seven-segment indicators. The inputs of the decoder 47 are the outputs of the counter 48, the same outputs are used as the address inputs of the switch 45, which determines the synchronous supply of information on each indicator with a corresponding anode signal. Counter 48 operates continuously with (defined reference frequency (1 kHz)) Each stage corresponds to a functionally completed stage of the device operation cycle. Three parameters are set and controlled by the device: output function value (both code and analog}, output function gradient and time out The device is capable of reproducing complex characteristics with a piecewise-linear approximation. The device implements the function FAST ft –t - time in seconds, and for F gjjij there is both a digital and an analog value. determines the value of the function F f (t at different points in time, the second, the rate of change of the incremental section of the diagram, the third, the duration of the flat sections of the diagram.; One value of these parameters for each stage is found in block 5 or entered from control panel 1 Operator's work with block 4. On fig. 4 are given. The signals accompanying the process of entering these parameters are in block 4. Signals and, g of are signals of the sample corresponding to each of the named parameters of the memory column, and signals are intended for you Yes, the typed parameter values in the memory block. These signals are formed in block 2 by pressing the corresponding key switch on the operator’s console 1. In order to obtain pulse sequences of different frequencies, when receiving both the lifting sections and the falling sections, a frequency divider 10 with a variable division factor is used. The frequency of the output pulses depends on: what speed (gradient). The output of the DAC 12 should change, which is determined by the rate of change of the code signal of the reversing counter 11, which in turn is determined by the frequency of the output I1 n1ul co-frequency divider The table shows a part of both the code values of the gradient of the output function (coefficient M) and the approximate values of Fe),). When using the device to control the temperature regimes of atomic absorption spectrophotometers, the numerical value of the frequency of the output pulses determines the rate of temperature change (temperature gradient). Knowing the required value of the temperature gradient, the operator enters the value of the coefficient I, corresponding to the required value of the gradient; From the operator's console to the memory unit. Together with the value of the coefficient M from the operator panel, the sign of the gradient is entered into the block of memory using the keypad. A switch with which in the last bit of the memory column, where the values of the temperature gradient are accumulated, is written O (negative gradient value) or 1 (positive gradient value). The frequency of the counter output (155IE8) is determined by the formula. The coefficient M is a number entered by the operator from the console, fgy 1000 Hz. The device works in two modes: Experiment and Auto. In the Experiment mode, the program is manually entered into block 4 from the operator's console. In the Automatic mode, work proceeds according to predetermined control laws, information with which is stored in block 5. Consider the operation of the device according to the functional block diagram in the Experiment mode. (The device operates in the Automatic mode in the same way with the only difference being that there is no process for entering the program from the operator’s console). The information accumulated on the operator's console 1 through the driver 2 signals arrives at block 4, and the program recording impulse simultaneously arrives there. As a result, a stepwise accumulation of information occurs at the addresses determined by the address counter 18 from the control unit 3. By pressing the Start button on the operator’s console, the information accumulated in block 4 {or stored in block 5 in Automatic mode) starts working. In control block 3, recording and sampling signals are generated, which determine the recording of information selected from the memory, respectively, during block 7, in registers 8, the output function values, and in register 9, the gradient of the output function. With a time delay relative to the indicated signals, a start signal of a frequency divider 10 with a variable division factor is generated. The output of this divider is the clock signal for the output reversible counter 11. Its overflow rate determines the rate of increase of the output signal. When the codes of the contained counter 11 and register 8 are equal, the comparison unit 13 generates a signal to prohibit further increase (with a positive gradient value) or decrease (with a negative function gradient value). The same signal is used to start the time of the master block 7, which determines the exposure time from the resulting level of the output function, after which a pulse is generated. End of cycle. At this stage one stage is completed, the next stage of the program is started. The number of steps being worked out, it is determined by the operator before the start of the mining process.

Thus, a variable division frequency divider introduced into the proposed device makes it possible to programmatically set the overflow rate of the output counter, the operation mode of which (addition or subtraction) is determined in advance for each step of the program. As a result, it is possible to obtain an output function with a positive (lifting sections) or negative (falling areas) gradient, i.e. You can get a curve of any shape.

The equipment of the device with blocks of operational and permanent memory makes it possible to work both in advance

given laws, and in various experiments of the technological process. Increased system flexibility.

The device has outputs of discrete signals capable of controlling, according to the program, various organs of the controlled object by the principle of open / closed.

The indication of the current value of the function provided in the device, as well as the program entered by the operator and the ability to check the accumulation in block 4 or placed in block I 5, eliminates programming errors.

Claims (3)

1. For the UK 147438 cl. G 3 N, 1972. 2. The copyright certificate CCCJ 667955, cl. G 05 F 15/00, 1972., 3. For France 2254816, CLO 05 B 19/04, “a 05 D 23/00, published. 1975 prototype). Fig. / F- f (i) Ff6 fts Flt ft 0 t (t2 t3 t -t2123123130tSf i32 FIG. g / r. i ffffi Sff, I FIG. ppppppppppp Ip p p p p / I p p p p p l p l omSa.tS omSa.n T 33 3 not fit. tl FIG. 9 l t total oSp. OJ Sa. / 4 JUUV. - ate 15 h Fig.b