SU1130832A1 - Device for program control having self-checking capability - Google Patents

Abstract

A SOFTWARE-CONTROLLED DEVICE WITH SELF-MONITOR, containing an operator's console, connected by an information input to the output of the first switch, the first information output — to the input of the first converter — a code — a code, and a second information output — to the first input; control unit connected by the first output to the control input of the first switch, the second output to the start input of a frequency divider with a variable coefficient and gating inputs of the time master, the first and second registers, and: the third and fourth outputs, respectively, to the control and the address inputs of the operative and permanent memory blocks connected by the outputs to the inputs of the second converter; the code associated with the first output with the new information input of the first switch; and the second output with info the input inputs of the first and second, registers and the time setter, connected by the information output 5m to the second information input of the switch, the control output — to the start input of the control unit; ny, clock input - to the first output of the pulse generator and to the clock input of the frequency divider with a variable factor, and the start input - to the blocking input of the frequency divider with a variable coefficient connected by the information input with the output of the second register, and outputs with the summing and subtracting inputs of the first the reverse counter connected by the output to the first inlet of the first block compared with the second input connected to you (L by the first register stroke, the digital-to-analogue converter connected by the input to the third to it the information input of the first switch, connected by the fourth information input with the output of the first translator code - code and information input of the operating memory block, which differs from TeMj, that for the purpose of increasing the reliability of the device 00, the second third and even fourth comparison blocks are entered J second switch pulse shaper, second reversible, pulse counter, and diagnostic unit containing the first trigger, first and second elements OR, first and second elements AND, second trigger, third trigger ep and the fourth trigger associated with the zero input x: the control output of the time setter and with the zero of the second trigger and the third trigger connected by a single input to the output of the second block compared to

Description

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and the first input, the first element OR, connected by an output to the start time start input, and the second input - to the output of the third comparison unit and to the single input of the second trigger connected by an inverse output to the first input of the first element AND connected to the output with a single input of the first ..: trigger, and the second input - with the direct output of the fourth trigger and with the first input of the second element AND connected to the second input .to the inverse output of the third trigger, and output to the first input of the second element OR connected About the second bus input Reset the device, and the output with the zero input of the first trigger connected by the outputs to the control inputs of the second switch connected to the input of the D / A converter, the first information input with the output of the first reversing pulse counter and the first information input the third comparison unit, connected by a control input to per 30832

the output of the pulse maker connected to the second, third and fourth outputs, respectively, with the reference inputs of the second comparison unit, the operational and fixed memory blocks and the single input — the fourth trigger, clock input, | home — with the second output of the I-pulses generator, and the input start-up - with the output of the first comparison unit and with the output of the fourth-comparison unit, connected by the first information | 1st. the input to the first register register, and the second information input to the output of the second reversible counter, to the second information input of the second switch and to the first information input of the second comparison unit, connected by the second information input to the second information input of the third comparison unit and the second output the second transducer code is a code, and the sum-: peace and subtract inputs of the second reversible counter are connected to the corresponding codes of a frequency divider with a variable coefficient ..

The invention relates to the field of automation and is intended to control the mode / atomization of an atom: but also absorption spectrophotometers j and can also be used in various installations, control circuits require a sequence of signals determined according to predetermined laws.

It is known a software device that contains a block of a set of time intervals, the exact time settings, the output of which is connected to the first input of the comparator block, a serially connected program switch, an encoder, a accumulator, the second input of which is connected to the output of the set of time ™ intervals, output - to the second input of the comparison block G | .

The closest technical solution to the invention is a device for program control s containing a control unit, the first

The first output of which is connected to the first inputs of the fixed memory unit, the second output with the first inputs of the operating memory unit, the second inputs of the direct-coupler unit connected to the third output and the second inputs of the constant unit: a memory, code converter, remote controller, variable frequency divider the division ratio, the first and second registers and the control and display unit, the output connected to the operator’s console, and the inputs respectively to the outputs of the control unit, the generated signals, the code converter, the time setting Loka and reversive counter, the input of which is connected to the output of a frequency divider with a variable division factor, connected by inputs to the output of the comparison unit, to the output of the second register, to the output of the control unit 5 to the inputs of the first and second registers and to the time inputs of the master unit, clock generator 2, The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that the device for program control with self-control, containing an operator console, is connected by an information input to the output of the first switch, the first information output is to the input of the first converter, a code is a code, and the second information output is connected to the first input of the control unit the first output with the control input of the first switch, the second output with the start input of the frequency divider with a variable coefficient and with the gate inputs of the time, first and second time controller the third and fourth outputs, respectively, with the control and address inputs of the RAM and fixed memory blocks connected by the outputs to the inputs of the second converter; the code associated with the first output with the first information input of the first switch, and the second output with by the formation inputs of the first and second registers and the time base connected by the information output to the second information input of the switch, the control output to the control input start input, the clock input to the to the output of the pulse generator and to the clock input of the frequency divider with a variable coefficient, and the start input to the blocking input of the frequency divider with a variable coefficient connected by the information input to the output of the second register, and the outputs to the summing and subtracting inputs of the first reversible counter connected the output to the first input of the first comparison unit connected to the second input with the output of the first register; a digital-to-analog converter connected by the input to the third information input of the first About the switch connected by the fourth information input with the output of the first converter code-code and with the information input of the RAM block, the second, third and fourth comparison blocks are entered, the second switch, the pulse former, the second reversible pulse counter, and the diagnostic block containing the first trigger, the first and second elements of the NL, the first and second elements And, the second 1 1. trigger, third trigger and fourth trigger, connected by zero input to control output of the time master and zero inputs of the second trigger and trigger connected by a single input to the output of the second comparator unit and to the first input of the first OR element connected to the time trigger start input , and the second input - with the output of the third comparison unit and with the single input of the second trigger connected by the inverse output to the first input of the first element And connected with the output with the single input of the first trigger, and the second input - with the direct output of the fourth trigger and with the first input of the second element AND connected by the second input to the inverse output of the third trigger, and output to the first input of the second OR element connected with the second input to the Bus Reset device, and the output with zero the input of the first trigger connected by the outputs to the control inputs of the second switch, connected by the output to the input of a digital-to-analog converter, the first information input to the output of the first reversible pulse counter and the first information the input of the third unit, the comparison connected by the control input to the first output of the pulse former, connected by the second, third and fourth outputs respectively to the control inputs of the second comparison unit, the operational and fixed memory blocks and the single input of the fourth trigger, a clock input with the second output of the pulse generator, and a start input with the output of the first comparison unit and with the output of the fourth comparison unit connected by the first information input to the output of the first register, and the second the information input to the output of the second reversible counter, to the second information input of the second switch, and to the first information input of the second comparison unit connected by the second information input to the second information input of the third comparison unit and the second output of the second converter code-code, and summing and the subtractive inputs of the second reversible counter are connected to the corresponding outputs of a frequency divider with a variable coefficient. FIG. 1 is given a block diagram of the proposed device; in fig. 2 diagram of the diagnostic unit; in fig. 3 is a control block diagram; in fig. 4 diagram of the pulse generator; in fig. 5 is a diagram of the synchronization node; in fig. 6 is a diagram illustrating the operation of the device; in fig. 7 is a timing diagram of the control unit; in fig. 8 is a timing diagram explaining the operation of the impulse generator and the diagnostic unit; Fig. 9 shows the relationship between decimal values, the code value of the gradient of the function, and the output frequency of a frequency divider with a variable coefficient. The device contains an operator 1 console, the first converter code 2 code, control block 3, RAM block 4, constant memory block 5, second code code converter 6, time setting 7, ne Bbrii and second registers 8 and 9 , divider 10 frequencies with variable division factor, first reversible counter 119 second reversible counter 12, first comparison block 13, third comparison block 1-4, fourth comparison block 15, second comparison block 16, pulse shaper 17, diagnostic block 18, second switch 19, digital-to-analog converter ( CAI) 20j first switch 21, generator 22 pulses. The diagnostic unit contains the first second, third and fourth triggers 23-26.j of the first and second elements of AND 27 and 2B, the first and second elements of OR 29 and 30, the Reset bus 31. The control unit contains the first and second one-shot 32 and 33, fifth and sixth triggers 34 and 35, third and fourth elements AND 36 and 37, third and fourth elements OR 38 and 39, third converter code 40J code first and second counters 41 and 42 pulses, first decoder 4 third switch 44j block 45 fifth elements And, node 46 is synchronized. The pulse driver unit contains the fifth element OR 47, the seventh trigger 48, the sixth element AND 49 the third counter 50 pulses the second decoder 51. The synchronization node contains the seventh, eighth, ninth and tenth and seventh elements OR 56 and 57, the first and second Inverters 58 and 59. The device operates in two modes: Experiment and Automatic, which differ from each other in that in the first case the program is entered manually from the operator’s console 1 into block 4, and in the second case the program is in block 5 and the operation of the circuit in this The case is considered from the moment of starter. From this point on, the description of the operation of both modes is the same. Therefore, below is a description of the operation of the circuit for the Experiment mode. The information collected in the operator's console 1 in the decimal code through the code converter — the code 2, which converts the decimal code to binary, goes to the information inputs of block 4. The address inputs of block 4 are from the control unit 3 pos. The memory address code stumbles, and the control inputs are recorded and sampled from a memory column. Unit 4 operative memory has three columns for storing the value of three parameters: temperature gradient, temperature values and dwell time. In each column, six hexagons are recorded. value of each parameter. When entering values of a gradient, the sign of the gradient is also entered. Its positive value corresponds to the enabled state of the corresponding key on the operator’s console. The correctness of the information is observed on a digital display via the switch 21. In this case, on the operator's console I, the Enter info key was pressed. After the program entry was completed, the correctness of the program entered into the memory block is checked. Include key Read info. (the Enter key is turned off) and pressing the Step key (the same key forms addresses when entering the program) in block 3 of the control, the address for the memory block is generated. The information read from the memory block through the blocks 21 is fed to the digital display. After checking the entered program, press the Start button, from which the control unit: expires the first address of the memory block, three signals for sampling the parameter values from the memory block, three signals for recording the parameter values into the corresponding registers (temperature gradient in register 9, temperature values in the register 8 and the dwell time in the time setting unit 7, the inputs of which at that moment from block 6 receive the binary values of the specified parameters) and the trigger signal of the divider 10, designed to receive pulse sequences of various frequencies. This frequency determines the rate of rise of temperature, the slope of the angle of the function F S (t). The pulse sequence from the divider 10 enters the summing input of the reversing counters 11 and 12, if the gradient sign is positive (in the sixteenth column bit of the gradient values of the memory block is written 1), or to the subtracting input, if the gradient sign is negative (in the corresponding bit d recorded O). The comparison units 13 and 15 compare the output information of the 11 and 12 s counters, respectively. with the set temperature value recorded in register 8. If the register codes and counters 11 and 12/5 blocks 13 and 15 are equal, the trigger signals of the pulse generator 17 are generated, generating four signals: the signal for gating the comparison unit 1.4, which controls the correctness of the temperature 11 that the counter has spent, controls the signal gating the comparison unit 16, which controls the correctness of the temperature value worked by the counter 12, the signal to be sampled from the memory unit at the time of monitoring the temperature values and the block start signal ka 18 diagnostics. For the duration of the sampling signal from the memory block, at the inputs of blocks 14 and 16 there is information about the real temperature value. The gate signals to blocks 14 and 16 are delivered separated in time. This achieves an advantageous transfer to the output through the switch 19 of the information of the first reversible counter 1 1, if both channels are working correctly. The diagnostic unit 18, after detecting an error in the operation of one of the channels, causes the enable signal for the switch 10 to pass the information of the other channel and the signal to stop further counting the 10 C divider temperature reached a predetermined level), which is also the start signal of the setpoint generator 7, which works for the delay time temperature values. This completes the development of one stage. The transition to the next stage starts with the appearance of a signal that the end time of the master time controller, which starts the control unit 3 to execute the program of the next stage.

The pulse generator 22 is designed to obtain clock frequencies for the setpoint generator 7, the splitter 10, the driver 17. The DAC 20 converts the digital code received at the output of the switch 19 into an analog signal. (Fig. 6 shows a diagram of the operation of the device, on which the stu-i foam character of changes in the output analog signal of the UMIJ is shown.

The purpose of the elements and the operation of the circuit of the control unit 3 is as follows.

Single-vibration 32 is designed to form a single pulse when the operator dials a step number on the operator’s console. A single vibrator 33 is designed to generate a pulse when the device starts. Counter 41 is pre-assigned to form the address of the memory cells. When entering the program, the clock pulse to the counter 41 comes from the one-shot 32, and when processing the program from the element OR 38, which receives the device start signal, as well as the signal from the time setter 7, which is the completion signal of the previous stage. Transducer 40 is designed to provide step number information via a switch for shaddling in binary-decimal code.

Synchronization node 46 is designed to form from pulses coming from generator 22 (FIG. T) pulse sequences shifted relative to each other:. (Fig. 7S, b). Trigger 34 is intended for the signal being placed,. (Fig. 7th) for the passage of pulses b through the element I 36 to the counter 42 (Fig. 7 e). The counter 42 is designed to determine the number of clock cycles for generating the recording and sampling signals of the program. It is a counter for four states, three of which determine three clock cycles corresponding to the sampling signals (r and recording (k) of the program, and the fourth state U is used to form the trigger signal, dividing 10 frequencies (Fig. The / 5 states are formed by the decoder 43. These signals are used as resolution signals in a block of 45 elements -I to form signals K. and L. Switch 44 is designed to transmit sampling signals extracted in the decoder to block 4 in slashchae work. with RAM and block 5 in case of working with a fixed memory. Sampling of one of these two modes is carried out by two signals (Experiment and Automatics fed from the operator console ... Trigger 35 is designed to generate a permission signal for the passage of pulses b through elements 37 at block 45 of elements I only after the first pulse S s passing to the counter 42 This provides a temporary relationship between the sampling and recording signals.The control unit is brought to the original signal by the Reset signal from the control panel. When entering the program for each stage Hb (1 to A 6) monostable multivibrator 32 generates one pulse, and the counter 41 - select address memory line. From the operator's console, the switch 44 transmits to block 4 three signals, a column sample (diagram) corresponding to three parameters. After completing the input of the parameter values from the operator panel to the one-shot 33, a trigger signal is received, which corresponds to the first address of the memory line and the signals shown in FIG. 7c In the following, the Start signal to form the next address and form the signals is a nm pulse signal, arriving from preset, time 7, which corresponds to the work:; current stage. Unit 4 of the RAM consists of three columns. Ka) in the second column contains four memory elements. Elements of the 1 slliffl column are designed respectively for storing the temperature gradient values, temperature values and time values. Each column has 6 data and four address inputs, which are respectively combined with each other, the information recording inputs are also combined, and the sample for each column served separately. The last bit of the 1st column of the memory, where the value of gradients accumulates, is significant and determines the operation mode of the reversible counters 11 and 12. Block 5 is constructed in the same way, only it uses the elements of the constant memory. information from blocks 4 to 5 according to the wired OR scheme and its transfer to block 21, as well as the conversion of a binary-decimal code into binary and transmission to time master 7, registers 8 and 9, and blocks 14 and 16 of the comparison. The time adjuster 7 is for determining the duration. flat sections of the diagram (Fig. 6) with the subsequent issue on the display. The device works as follows. After starting the programmable device for the duration of the 3rd signal (Fig. 7), intended for sampling. The 3rd column of memory at the input of time sensor 7 is the information about the value of the duration of time of the flat chart diagrams (Fig. 6) 5 3rd signal | (FIG. 7) is a gating signal for the setter 7. The time in seconds begins after the monitoring process is completed by the diagnostic unit 18. A signal about this from block 18 is fed to the input of the setting device 7, which sets it to the single position. In this case, the generator 22 (Fig. I) receives a 1-1 pulsed sequence with a frequency of 1 Hz, which is counted to a predetermined value, after which the counting stops and a pulse is generated, which arrives at block 3 and serves as a trigger signal for the next station. For a flat section of the next degree, the operation of the device is similar. Registers 8 and 9 represent the trigger and are designed to receive data, respectively, about the size of the output function and the gradient of the function at each stage. A variable frequency divider 10 (kc 3) is designed to receive pulse trains of various frequencies. Output reversible counters 11 and 12 are designed to obtain the code value of the current value of the output signal. The operation mode of the counters (forward or backward) is determined in advance for each step of the program, since the circuit is given using one K155IE8 cell and, therefore, the definition of the output frequency of the frequency divider 10 (Fig. 1) and the table of code values of the gradient functions (Fig. 9) for This case corresponds to a clock frequency of 1000 Hz. The blocks 13 and 15 of the comparison are logical modulo-two logic diagrams and are intended for the trigger signals of the former 17 when the output function reaches a predetermined value at the outputs of the reversible counters 11 and 12. Blocks 14 and comparisons are designed to control the results of joint operation of blocks 11, 13, and 8, 12, and 15, respectively. The output information of counters is fed to one input of blocks 14 and 16, respectively. 11 and 12, and the other entrances - sign. control parameter (temperature) from the memory blocks of the pulse body. The purpose of the pulse generator 17 (Fig. 4) is to form the signals m, n, n, p, (Fig. 8). When a signal arrives from block 13 or 15, or both signals are delivered simultaneously, a trigger 48 is started, and a pulse sequence arrives at the input of counter 50 through the element 49. The decoder 51 provides receiving signals M5K P, p (Fig. 8). The diagnostic unit 18 of FIG. 2 is intended to recognize channel operation errors and generate permitting signals for the switch 19 to pass information of a properly operating channel. The following cases are considered in the operation of the diagnostic unit 18. Both channels — consisting of blocks 11, 13, 14, and 11 and consisting of blocks 12, 15, 16 — work normally. In this case, the output pulsed signals of blocks 13 and 15 of the comparison with fall with each other and arrive at the start of the imaging device 17. One of the channels as a result of the incorrect operation of the reversible counter or the comparison unit generates a signal until the increasing portion of the specified level is reached. One of the channels does not work. VILNO, and the signal from the comparison block is obtained after the output function has reached a predetermined level. This case is not taken into account because the control given here confirms the incorrect operation of this channel, issuing an error signal on this channel, and on the operation of the rest. This does not affect the circuitry, since the output of the information is correctly received by the channel. An error in the operation of the circuit is detected after a signal p from the driver 17 is applied to the trigger 26. By this time, the triggers 25 and 24 have already been transferred to one state by the signals from blocks 16 and 14, respectively, if both channels are working correctly or one of them remains there is no zero if there is no signal of correct operation from the corresponding channel. FIG. 8 shows an example of incorrect operation of channels 11, 13, and 14. At the output of element 27, in this case, a signal appears that sets trigger 23 to the state of logic 1. In this case, trigger 23 outputs for channel information blocks 11, 13, 14 is Forbidden and for channel information blocks 12, 15, 16 are permitted by them. The signal c (Fig.8 corresponds to the change in the output of the trigger 24, the signal GT) - the change in the output O; trigger 25, signal ij - change of output 1 of trigger 26, signal o - change of output .1 of trigger 23. Switch 19 is intended for supplying a DAC unit 20 through switch 21 for indication of information of a properly working channel. Digital to analog, converter 20 is designed to convert the output digital signal to the corresponding analog value and contains the DAC itself with an operational amplifier and output. Switch 21 provides a signal for ten seven-sevens; Mentnyh indicators located on the console I operator. Four of these indicators serve as a highlight.

values of the output function (in this case, the temperature values), four-length: displaying the values of three parameters — the output function (temperature), the delay time and the output function gradient when the program is entered from the operator’s console I, or if you want to read the accumulated memory information, two indicators serve to highlight the number of the operated stage. Kazshcha stage corresponds to the functionally completed stage of the device operation cycle.

The device is capable of reproducing complex characteristics with a piecewise linear approximation. It implements the function Pn, fj (t), where t is time in seconds, and for F, there is both a digital and analog value.

i The device sets and controls three parameters. The first parameter determines the rate of change of the growth areas. The second parameter determines the value of the function F f (t) in various time arguments. The third parameter determines the duration of the flat sections of the diagram. One value of these parameters for each stage is located in block 5 or is entered from the type-setting field of the console 1 of the operator when working with block 4.

In order to obtain pulse sequences of different frequencies when creeping up of both the lifting and the falling segments, a frequency divider 10 with a variable division factor is used. The frequency of the output pulses is set depending on the speed with which. (Gradient) the output signal of the digital control unit should change, which is determined by the rate of change of the code signal of the reversible counters P and 12, which, in turn, is often determined214

the output pulses of the frequency divider. The table (Fig. 9) shows a part of both the code values of the gradient of the output function (coefficient M),: and the approximate values of Tjbix. When using a device for controlling the temperature regimes of atom-absorption spectrophotometers, the numerical value of the output frequency

pulses determines the rate of temperature change (temperature gradient) in ° C / s. Know the required value of the temperature gradient, the operator enters the value of the coefficient M,

corresponding to the required gradient value from the operator console to the memory block. Together with the value of the coefficient M from the operator’s console, the sign of the gradient with

A key switch that records O (negative gradient value) or 1 (positive gradient value) in the last bit of a memory column where the values of the temperature gradient are accumulated.

The frequency of the output of the counter is determined by the formula

-. -

I O O 64

where the coefficient M is a number entered by the operator from the console, IBX 1000 Hz.

The invention makes it possible to control the values of the output function of reversible counters by re-comparing these values with the values placed in the memory blocks. The correct comparison result is output to the device, and the incorrect result is blocked. As a result, the probability increases.

the reliability of the device.

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Claims (1)

A DEVICE FOR PROGRAM CONTROL WITH SELF-CONTROL, comprising an operator panel connected by an information input to the output of the first switch, the first information output to the input of the first code-to-converter, and the second information output to the first input, from the control unit connected to the control output by the first output the first switch, the second output with the input of the start of the frequency divider with a variable coefficient and with the gate inputs of the clock, the first and second registers, the third and fourth output respectively, with the control and address inputs of the RAM and read-only memory blocks, connected by the outputs to the inputs of the second code-converter, connected by the first output to the first information input of the first switch, and the second output with information inputs of the first and second; registers and master clock connected by the information output to the second information input of the switch, the control output to the start input of the control unit: ny, the clock input to the first output of the pulse generator and to the clock the input of the frequency divider with a variable coefficient, and the start input to the blocking input of the frequency divider with a variable coefficient, connected by the information input to the output of the second register, and the outputs - with the summing and subtracting inputs of the first reversible counter connected to the first input of the first comparison unit, connected the second input with the output of the first register, a digital-to-analog converter connected to the third information input of the first switch connected to the fourth information th input to an output of the first code converter - code and an information input memory block, characterized in that, in order to increase the device reliability, it introduced a second, third and fourth comparing blocks, the second switch, a pulse shaper, a second reverse _(pulse counter , and a diagnostic unit containing the first trigger, the first and second elements OR, the first and second elements AND, the second trigger, the third trigger and the fourth trigger connected by a zero input to the control output of the time setter and with zero the inputs of the second trigger and the third trigger ^ connected by a single input ^ to the output of the second block are comparable to SU.,. 1130832 and to the first input, the first OR element, connected by the output to the start input of the time delay unit, and the second input - with the output of the third comparison unit and with a single the input of the second trigger connected by an inverse output to the first input of the first AND element, connected by the output to a single input of the first: a trigger, and the second input - with the direct output of the fourth trigger and with the first input of the second And element connected w the first input to the inverse output of the third trigger, and the output to the first input of the second OR element connected by the second input to the Reset '' bus of the device, and the output to the zero input of the first trigger connected by the outputs to the control inputs of the second switch connected by the output to the digital-analog input transducer, the first information input - with the output of the first reversible pulse counter and with the first information input of the third comparison unit, connected by the control input to the περί 130832 output of the shaper and pulses connected by the second, third and fourth outputs, respectively, with the control inputs of the second comparison unit, random-access memory and read-only memory blocks and with a single input of the fourth trigger, clock input, - <'; DOM - with the second output of the pulse generator, and the start input - with the output of the first comparison unit and with the output of the fourth comparison unit connected to the first information one. the input to the output of the first register, and the second information input to the output of the second reversible counter, to the second information input of the second switch and to the first information input of the second comparison unit, connected by the second information input to the second information input of the third comparison unit and to the second output of the second converter code - code, moreover: summing up and subtracting the inputs of the second reverse counter connected to the corresponding outputs of the frequency divider with a variable coefficient .. 12