SU984041A1 - Analogue-digital converter - Google Patents

Description

(54) ANALOG-1CHF-FORMER CONVERTER

The invention relates to a pulse technique, more precisely to analog-to-digital conversion devices, and can be used to communicate primary physical parameter transducers with digital processing devices of automated control systems, for example, in the steel industry, to convert an analog signal coming from and carrying information about the mass of the material, into a digital code supplied to the weighing dosing system. An analog-to-digital converter is known, containing a sawtooth generator voltage, comparator, two valves, pulse counter, auto-tuning amplifier, operating mode switch, key, command device, pulse generator, the output of the saw-tooth voltage generator is connected to the first input of the comparator, the second input of which is connected via the key to the first and the second inputs of the device, the output of the comparator is connected to the first input of the first valve, the second input of which is connected to the output of the pulse generator, and the third turn is connected to the output of the command device having The connection with the sawtooth generator, the output of the first valve is connected to the counter input of the pulse counter, the initial state setting BX05I of which is connected to the second output of the command device, the outputs of the pulse counter bits are outputs of the device, the high output of the pulse counter is connected to the first input of the second valve, the second input of which is connected to the third output of the command device, the output of the second valve is connected to the input of the auto-tuning amplifier, the output of which is connected to the input the generator of the sawtooth voltage and the third input of the device, the fourth output of the command device is connected to the input of the operation mode trigger switch, the output of which has a mechanical connection with the key. The first, second and third inputs of the device are respectively fed into an input convertible analog signal, a reference signal and a reference signal. To improve the accuracy of the conversion, cycles of periodic calibration of the converter with its subsequent adjustment 1 were introduced. The main disadvantage of such a converter is the complexity of the soE. A generator of a sawtooth voltage with high linearity characteristics. In addition, additional time is required during periodic calibration. Also known is an analog-to-digital converter containing four pulse counters, a memory register, three flip-flops, three pulse shapers, four AND elements, an OR-NOT element, a two-key, a potentiometer, and a standby capacitor. multivibrator, two comparison elements, the first input of the first of which is connected to the input bus, the output is connected to the input of the first pulse shaper, the second inputs of the first and second comparison elements are connected to the output of the first switch, the input of the second switch and the first capacitor plate, the input of the first switch is through The charging resistor is connected to the bus of the source of the reference voltage and the first terminal of the potentiometer, the second terminal of which, the second capacitor lining and the output of the second switch are connected to the common bus, of the potentiometer 2 It is connected to the first input of the second comparison element, the output of which is connected via the second pulse shaper to the first input of the first flip-flop, the second input of which is connected to the second inputs of the second and third flip-flops (output of the third pulse shaper and input Reset of the first pulse counter, the output of which is connected to the first input of the first additional trigger), the first output of the first trigger is connected to the second input of the first And element and the second input of the third And element, the second output of the first trigger under The key is connected to the second input of the fourth element. And the second output of the second trigger is connected to the first input of the fourth element AND whose output is connected to the second input of the OR-NOT element, the first input of the second trigger is connected to the second input of the second element AND whose output is connected to the first input of the element OR NOT, the output of which is connected to the third inputs of the first and second elements AND and to the input of the third pulse generator, the output of which is connected to the input of the waiting multivibrator, input writing the third counter and pulses and the first input of the third circuit, the first and second outputs of which are connected respectively to the inputs of the second and first key, the reference frequency pulse bus is connected to the first inputs of the first and second And elements, the outputs of which are connected respectively to the sum and the subtracting inputs of the first pulse counter, the bit outputs of which are connected to the corresponding inputs of the second pulse counter, the counting input of which is connected to the clock pulse bus, the outputs of the third bits The pulse counter is connected to the corresponding inputs of the fourth pulse counter 27. The disadvantage of this converter is the low conversion accuracy when changing the value of the input signal corresponding to the zero value of the measured parameter. In addition, there is no possibility to scale the output code in the converter. The purpose of the invention is to increase the conversion accuracy by taking into account the change in the zero of the input source and expanding the functionality. The goal is achieved in that an analog-to-digital converter containing four pulse counters, a memory register, three triggers, three pulse shapers, four AND elements, an ILINE element, two keys, a charging resistor, a potentiometer, a capacitor, a waiting multivibrator, two the comparison element, the first input of which is connected to the input of the device, the output is connected to the input of the first pulse shaper, the second inputs of the first and second comparison elements are connected to the output of the first key, the input of the second key and howl capacitor plates, a first key input through a charging resistor sub; connected to the bus of the voltage source and to the first terminal of the potentiometer, the second terminal of which, the second capacitor plate and the output of the second key are connected to the common bus, the potentiometer slider is connected to the first input of the second reference element, the output of which is connected to the first input of the first trigger, the second input of which is connected to the second inputs of the second .and third trigger, the first output of the first trigger is connected to the second input of the first element And the second input of the third element And, the second output of the first trigger is connected to the second input of the fourth element And, the second output of the second trigger is connected to the first input of the fourth element AND, the output of which is connected to the second input of the element OR NOT, the first output of the second trigger And and the first the input of the third element And, the output of which is connected to the first input of the element OR NOT, the output of which is connected to the third inputs of the first and second elements AND and to the input of the third pulse generator, the output of which is connected to the input a monostable multivibrator, the input of the third recording pulse counter and the first input of the third flip-flop, the first and second outputs which are respectively connected to the inputs of the second and the first key, the tire

- “reference frequency pulses are connected to the first inputs of the first and second elements And, the outputs of which are connected respectively to the summing and subtracting inputs of the first pulse counter, the discharge outputs of which are connected to the corresponding inputs of the second pulse counter, the counting input of which is connected to the clock pulse bus, the outputs of the bits of the third pulse counter are connected to the corresponding inputs of the fourth pulse counter; three pulse counters, a register zero, five And elements, and pulse generator, trigger, OR element, frequency divider by two, write control unit in register zero, with the first output of the first trigger connected to

the third input of the fifth element And, the second input of which is connected to the first output of the second trigger, the first input - with the output of the waiting multivibrator, and the output is connected to the second inputs of the sixth and eighth elements And, the outputs of which are connected respectively to the subtracting: input / p of the counter pulses and the first input of the OR element, and the first inputs are connected to the clock frequency pulse bus and the counting input of the sixth pulse counter, the bit outputs of which are connected to the corresponding buses, and the output is connected to the counting input The seventh pulse counter, whose bit outputs are connected to the corresponding inputs of the memory register, the output of the second pulse counter is connected to the first input of the seventh And element and to the input of a frequency divider by two, the output of which is connected to the counting input of the fourth pulse counter, the output of which is connected with the first input of the ninth element AND the output of which is connected to the second input of the OR element, the output of which is connected to the subtractive input of the third pulse counter, the summing input of which is connected to the output of the seventh element And, the outputs of the transfer pulses minus and plus the third pulse counter are connected

respectively with the first input of the fourth trigger and the first input

the second trigger, the second output of which is connected to the second inputs of the seventh and ninth elements, the outputs of the bits of the third pulse counter are connected to the corresponding 5 inputs of the fifth pulse counter and register zero, the outputs of the bits of which are connected to the corresponding inputs of the third pulse counter, output the first driver and the IMS is connected to the input of the recording of the fifth pulse counter and the second input of the writing control unit to the register zero, the first input of which is connected to the zero setting pulse bus and the output connected to the input Record register zero, the transfer pulse output minus the fifth pulse counter is connected to the input Record of the memory register and the input of the fourth pulse generator, the output of which is connected to the second input of the first trigger, inputs Reset the third and fourth pulse counters and the second input

5 of the fourth flip-flop, the output of which is connected to the input of the 7th pulse counter.

The drawing shows a block diagram of the converter.

 The converter contains counters 1-7 pulses, elements AND 8-16, elements 17 and 18 of the comparison, for example, scientific research institutes, drivers 19-22 pulses, triggers 23-26, element OR-NOT 27, divider 28 frequencies into two, element , Or 29, waiting multivibrator. 30, keys 31 and 32, write write control unit 33 to register zero, potentiometer 34, resistor 35, capacitor 36, register 37 zero, register 38

01pam tee.

The analog signal Ugj arrives at the first input of the voltage comparison circuit 17. At the counting input counter-.

5 ka 2 receives a sequence of pulses of clock frequency Gd. The first inputs of the elements And 8 9 receives a sequence of pulses of the reference frequency fg. At the first entrance

The write control rod 33 registers a zero setting pulse to the zero register. The bit inputs of counter B are fed with a code from a scale switch. The reference voltage below leads to a charging resistor, 35 and a potentiometer 34.

A feature of the proposed converter is the presence of two functional signal generators of exponential form: analog and digital. The analog generator consists of a resistor 35, a capacitor 36, keys 31 and 32. A digital generator consists of counters 3 and 4, a divider 28, elements I 13, 15 and

element OR 29. Analog input

the signal is compared to an exponential voltage generated by an analog generator, the output of which is the first capacitor plate 36. The time equality of these voltages determines the output code value in proportion to the value of the input signal.

Counters 2, 4, 6 are frequency dividers with a variable division factor.

The device works as follows.

The start of the conversion cycle is determined by the moment of the appearance of a pulse at the output of the generator 22. This pulse triggers 23-26 are reset and the counters 3 and 4 are reset. The logical 1 signal from the second output of trigger 24 goes to the second inputs of the And 13 elements, 15, allowing the passage of frequency f from the output of counter 2 through element I 13 to the summing input of counter 3 and frequency f s. the output of counter 4 through elements AND 15 and OR 29 to the subtracting input of counter 3. At the initial moment of time, the frequency f, depending on the code value in counter 3, is zero. The N code in counter 3 begins to increase at a rate determined by the frequency f. As the N code increases, the frequency f at the output of counter 4, which, arriving at the subtracting input of counter 3, slows down the rate of increase of the code N. Thus, due to feedback circuits including divisor 28, counter 4, elements AND 15 and OR 29, code N in counter 3 increase exponentially.

The logical 0 signal from the first output of the trigger 23 opens the key 32, and the logical 1 signal from the second output of this trigger closes the key 31. The capacitor 36 starts to charge through the resistor 35 with the current of the source of the reference voltage. And the voltage of the capacitor 36 on which the exponential law is changed, begins simultaneously with the start of the formation of the digital exponent.

During the formation of both exponents, the frequency fn g determining the growth rate of the digital exponent remains unchanged, as the inputs of the AND 10 element from the first outputs of the flip-flops 24 and 25 receive logical 1 signals. From the output of the AND 10 element, the logical 1 signal is fed to the input of the OR element -NON 27 logical O, from the output of which goes to the third inputs of the elements And 8, 9, prohibits the passage of pulses of frequency fp to the summing and subtracting inputs of counter 1. Code L

counter 1, which determines the magnitude of frequency f, does not change. A change in frequency f, automatically carried out by the converter circuit for the purpose of tracking the digital exponent beyond the analog, is performed

after finishing one of the exhibitors. When the input voltage UBXC is equal to the voltage of the capacitor 36, the voltage comparison element 17 is triggered, the signal from the output of which through the shaper 20 records the instantaneous code value from counter 3 to counter 5. The code in counter 5 is stored until the end of both exponents, after which with

5, it performs operational zero-code subtraction and scaling. During the charging of the capacitor 36, the voltage across it changes according to the law

- “and and.

Tc.

current time;

the time constant of the analog capacitor charge generator 36; reference voltage. 3, the code is changed by

Nnd-tN

where TC is the time constant of the digital generator; NO is the code you are aiming for.

digital exhibitor. Substitute

and

-T0ep (1st

will get

N (i - -) 4 ::

From this it can be seen that at Td Tc, the linear dependence of the code in the counter 3 on the voltage across the capacitor 36 is obtained.

ki o ii o ii

The frequency f at the output of counter 2 is determined by the expression

, fo- L 1 -RG5

1 where L is the code in the counter 1;

n2 is the number of bits of counter 2.

f2K-fi

where K is a coefficient indicating how many times the frequency f is less than the frequency f.

at the output of the counter 4 pulses follow with frequency

f .0 N

2

where N is the code in the counter 3;

n is the number of bits of the counter 4. In the steady state N .No, choosing the volume of the counter is 32 0.5 where PI is the number of bits of the counter 3 we get 0. 20 If the volumes of all the counters are single kov, then in the converter circuit the frequency fj 0.5 f Obtained with the help of the divisor -28 frequency on 2. We obtain the constant for the time of the digital generator. In the first instance of the conversion cycle time, the code in the 3 N O counter, so the frequency f - at the output of counter 4 is zero. The rate at which the code grows in the counter at t О is determined only by the frequency f dN / Jii f. (From here 2 2 NO fT, O, 5 f o L By changing the value of the L code in counter 1, the constant time of the digital oscillator can be changed. After turning on the power, the converter changes the TC in such a way that the equality tc holds (t where tg is the time9 from the beginning of the analog exponent is formed to the comparison of its comparison with the Unop voltage, the time from the beginning of the digital exponent to the point of reaching its magnitude as T t and |, NO I- {I Nf, op is determined by the volume of the counter 3, equal to 0.5No, i.e.

the transfer pulse plus counter 3 corresponds to the moment when the digital exponent is reached.

0.5No.

Substituting the value

then we get IL1- {0.5G, where ot To obtain a linear dependence of the code to the counter 3 on the voltage on the capacitor 36, it is necessary that ot 1. Then Unop O, sit ,. The magnitude of the threshold voltage is set using a potentiometer 34. - The change in the time constant of the digital oscillator Tc occurs as follows. Suppose Hz is greater than t ,. In this case, the comparison pulse of the analog exponent with the magnitude (the voltage comparison element 18 is wits earlier / than the comparison pulse of the digital exponent with Nnop from the transfer output plus counter 3. The pulse from the output of the voltage comparison circuit 18 translates the trigger 25 into one state Triggers 25 and 26 will also have opposite states, at the outputs of elements 10 and 11 there will be logical O. At the output of element ILINE 27, logical 1 turns on, which opens elements 3 and 8, 9 on the third inputs. the second input element And 8 logical 1 is supplied from the first output of the trigger 25, therefore the sequence of pulses of the frequency fo passes through the element AND 8 to the summing input of counter 3, and does not pass through the element 9 because it is closed at the second input. After the digital exponent is completed, the pulse from the transfer output plus the counter 3 sets the trigger 24 to the one state on the first output, the output of the element OR NOT 27 appears logical O, prohibiting the passage of the frequency f through the element 8, 9. Thus, the frequency fo goes to the summing input of the counter 1 during time tc-tcj, the code L in counter 1 is increased, so in the next conversion cycle the digital exponent will increase with a smaller time constant TC and reach the value Nfjop earlier, the time 1C will decrease. If Hz was significantly higher than tg, which is possible immediately after switching on the power source, then several cycles of formation of dp ug jensheni Tz are necessary in order for tu tu to be equal. In the case when Hz turns out to be less than tjj, element 9 will be opened for time tc. Pulses with frequency fg will be sent to the subtracting input of counter 1, reducing the code in it and, therefore, increasing the constant time T ,,. ,one . At the moment of termination of the second exponent digital or analog), the output of the element OR NOT 27 produces a negative voltage drop, according to which the driver 19 generates a pulse that writes the H code from the zero register 37 to the counter 3 and translates the trigger. 23 in a single state on the first exit. Logic 1 from the first output of the trigger 23 closes the key 32, and logical 0 from the second output of this trigger opens the key 31 begins. The discharge of the capacitor 36, the discharge time of the capacitor 36 is determined by the duration of the pulse of the waiting multivibrator 30, which is the same started by the pulse from the output of the former 19, and the time of the account is the mode of subtraction-counter5. After the exponent of the exponent, the signals of the logical 1 from the first outputs of the flip-flops 24, 25 arrived at the second and third inputs of the element 16. After the end of the pulse of the waiting multivibrator 30, the logical output of the first output of the element 16 also appears and the passage of the frequency pulses is allowed on the subtractive inputs of counters 3.5. Since counter 3 contains the NH code from register 37 zero corresponding to the initial value of the input signal, and counter 5 contains the code corresponding to the current value U, the pulse from the transfer output minus counter 3 is faster than from the transfer output of the counter 5 o I / C; transfer counter 3 trigger. 26 is transferred to zero state on the second output, the Reset signal is removed from the input of counter 7, and during this time-t in this counter, the code is stolen at a frequency f fo. 4 - where, where M is the code applied to the bit inputs of the counter b from the scale switch; п6 - number of bits of the counter 6.

The transfer pulse of the counter 5 records the code from the counter 7 into the memory register 38. The value of the code recorded in the memory register 38, which is the output code of the pre-.

N

fi-t

A digital signal generator of exponential form is transformed into a SIGGS generator, - linearly varying. generator, defined by the expression b, - 4-t - N4) The code corresponding to the initial value of the input voltage ex and the zero register 37 is written upon the arrival of the zero setting pulse. This pulse prepares the write control block 33 to the zero register, which passes only the analog comparison pulse first after the arrival of the zero setting signal (the analog exponent with the input voltage to the register entry 37 zero, recording the instantaneous value of the HH code from counter 3 to 37 is zero and into counter 5. The output code N bw will be zero. Subsequently, in all conversion cycles, the code will be subtracted from the N code corresponding to) the measured value Ug; (. Before the start of the new measurement, the impulse will come again ki zero, in which the corresponding code will be written to the zero register 37. Thus, setting zero allows eliminating the error associated with Ci by changing the input voltage corresponding to the zero value of the measured parameter and increasing the accuracy of the conversion. It allows non-linear conversion of the input analog signal to a code in accordance with the formula - (- 4: -P, where, ot may be greater than 1 or less than 1. In this case, the converter works It is exactly the same as described above, only the circuit instead of a TC Ta supports equality TC 7. The threshold voltage set at the first input of the voltage comparison element 18 is determined from the expression for Unop. Moreover, using this transducer, one can obtain the transformation input analog signal to the code in a logarithmic law. To do this, it is necessary to disable the frequency fj from the subtracting input of counter 3. Then the code in counter 3 will vary linearly. The frequency f at the output of counter 2 will be equal to the dependence of the code in counter 3 on the value of the proposed transducer in devices Coke weighing can be noted the following advantages. Storing the code corresponding to the tare weight at a zero setting signal, which arrives before each new weighing, eliminates the error associated with changes in the input signal as the tare weight changes. The change in the input signal, the lack of information about the mass of the container, is possible when the material sticks to the walls of the weight bin, as well as when the parameter of the strain gauge changes under the influence of the destroying factors (temperature, humidity). . The use of a digital scaling converter, necessary to bring the output code value into conformity with the measured mass, allows us to improve scaling accuracy and expand the range of application of the transmitter, since it can be used to work with different tener sensors that have the same the output signal may correspond to different values of the measured value. In addition, the transducer has the ability to automatically rescale the transform. To do this, the bit inputs of counter B, instead of the code from the large-scale switch, must be supplied with the code from the output of the external automated process control system. of the invention An analog-to-digital converter containing four pulse counters, a memory register, three flip-flops, three pulse shapers, four AND elements, an OR-NOT element, two keys, a charging resistor, a potentiometer, a capacitor, a waiting multivibrator, two comparison elements, the first one. of which are connected to the input bus, the exhaust is connected to the input of the first pulse shaper, the second inputs of the first and second comparison elements are connected to the Btjx of the first key, the input of the second key and the first capacitor plate, the input of the first cell Through the charging resistor, it is connected to the bus of the voltage source and to the first terminal of the potentiometer, the second terminal of which, the second capacitor plate and the output of the second switch are connected to the Common bus, the potentiometer slider, connected to the first input of the second reference element, the output of which is through the second driver impulses connected to the first input of the first trigger, the second input of which is connected to the second inputs of the second and third triggers, the first output of the first trigger connected to the second input of the first element And V The first input of the first element is And the second input of the third element is And the second output of the first trigger is connected to the second input of the fourth element And the second output of the second trigger is connected to the first input of the fourth element AND, the output of which is connected to the second input of the element OR NOT, the first output The second trigger is connected to the second input of the second element AND and the first input of the third .I element, the output of which is connected to the first input of the OR-NOT element, the output of which is connected to the third inputs of the first and second elements AND and to the input ter its pulse generator, the output of which is connected to the input of the waiting multivibrator, input Record of the third pulse counter and the first input of the third trigger, the first and second outputs of which are connected respectively to the inputs of the second and first key, the reference frequency pulse bus is connected to the first inputs of the first and second elements And The outputs of which are connected respectively to the summing and subtracting inputs of the first pulse counter, the bit outputs of which are connected to the corresponding inputs of the second counter by them pulses, the counting output of which is connected to the clock pulse frequency bus, the outputs of the bits of the third pulse counter are connected to the corresponding inputs of the fourth pulse counter, characterized in that, in order to improve the conversion accuracy by taking into account the change of the zero, the input signal source and the expansion of the functional capabilities, it contains three pulse counters, register zero, five AND elements, pulse shaper, trigger, OR element, divisor often.two by two, write control finoK to register zero, than the first output of the first trigger is connected to the third input of the fifth element I, the second input of which is connected to the second output of the second trigger, the first input is with the output of the waiting multivibrator and the output is connected to the second inputs of the sixth and eighth elements I, the outputs of which are connected respectively to the subtracting input the first pulse input and the first input of the OR element, and the first inputs - to the clock frequency pulse bus and the counting input of the sixth pulse counter, the bit inputs of which are connected to the corresponding scale The output bus is connected to the counting input of the seventh pulse counter, the bit outputs of which are connected to the corresponding inputs of the memory register, the output of the second pulse counter is connected to the first input of the seventh And element, and the input of the frequency divider to two, the output of which is connected to the counting input the fourth pulse counter, the output of which is connected to the first input, the ninth element AND, the output of which is connected to the second input of the OR element, the output of which is connected to the subtractive input of the third pulse counter, the dir ing input of which is connected to the output of the seventh element I, the outputs of transfer pulses minus and plus the third pulse counter are connected respectively to the first input of the fourth trigger and

the first input of the second trigger, the second output of which is connected to the second inputs of the seventh and ninth elements, the outputs of the bits of the third pulse counter are connected to the corresponding inputs of the fifth pulse counter and register zero, the outputs of which bits are connected to the corresponding inputs of the third pulse counter, output first

pulse generator connected to the input Record of the fifth pulse counter and the second input of the write control unit in the register zero, the first input of which is connected to the bus

the zero pulse is set, and the output is connected to the Record register zero input, the transfer pulse output minus the fifth pulse counter is connected to the Record register of the memory register and

the input of the fourth pulse former, the output of which is connected to the second input of the first tzigger, the Reset inputs of the third and fourth pulse counters and the second

the input of the fourth trigger, the output of which is connected to the Reset input of the seventh pulse counter. Sources of information taken into account in the examination

1. Design Engeneeriuq, 1973,

June. p. 103 ..

 2. USSR author's certificate in application number 2958448/21, 01.22.81.

Claims (1)

Claim An analog-to-digital converter containing four pulse counters, a memory register, three triggers, three pulse shapers, four AND elements, an OR-NOT element, two keys, a charging resistor, a potentiometer, a capacitor, a waiting multivibrator, two comparison elements, the first input of the first of which is connected to the input bus, the output is connected to the input of the first pulse shaper, the second inputs of the first and second comparison elements are connected to the output of the first key, the input of the second key and the first lining of the capacitor, the input of the first key The charging resistor is connected to the bus of the reference voltage source and to the first output of the potentiometer, the second output of which, the second capacitor plate and the output of the second key are connected to the common bus, the potentiometer engine is connected to the first input of the second comparison element, the output of which is connected to the first through the second pulse shaper the input of the first trigger, the second input of which is connected to the second inputs of the second and third triggers, the first output of the first trigger is connected to the second input of the first element And and the second, in during the first element And and the second input of the third element And, the second output of the first trigger is connected to the second input of the fourth element And, the second output of the second trigger is connected to the first input of the fourth element And, the output of which is connected to the second input of the element OR NOT, the first output the second trigger is connected to the second input of the second AND element and the first input of the third AND element, the output of which is connected to the first input of the OR-NOT element, the output of which is connected to the third inputs of the first and second AND elements and to the input of the third form Pulse generator, the output of which is connected to the input of the standby multivibrator, the Record third pulse counter input and the first input of the third trigger, the first and second outputs of which are connected respectively to the inputs of the second and first key, the reference frequency pulse bus is connected to the first inputs of the first and second elements And, the outputs of which are connected respectively to the summing and subtracting inputs of the first pulse counter, the bit outputs of which are connected to the corresponding inputs of the second pulse counter, the first output of which is connected to the pulse bus of the clock frequency, the outputs of the bits of the third pulse counter are connected to the corresponding inputs of the fourth pulse counter, characterized in that, in order to increase the conversion accuracy by taking into account changes in the zero · of the input signal source and expanding the functionality, it is introduced three pulse counters, a zero register, five AND elements, a pulse shaper, a trigger, an OR element, a frequency divider by two, a control unit for writing to the zero register, and the first output The first trigger is connected to the third input of the fifth element And, the second input of which is connected to the first output of the second trigger, the first input is connected to the output of the standby multivibrator and the output is connected to the second inputs of the sixth and eighth elements AND, the outputs of which are connected respectively to the subtracting input of the fifth pulse counter and the first input of the OR element, and the first inputs - to the clock pulse bus and the counting input of the sixth pulse counter, the bit • inputs of which are connected to the corresponding scaling buses, and the output with is single with the counting input of the seventh pulse counter, the discharge outputs of which are connected to the corresponding inputs of the memory register, the output of the second pulse counter is connected to the first input of the seventh element And and the input of the frequency divider by two, the output of which is connected to the counting input of the fourth pulse counter, the output of which is connected with the first input of the ninth AND element, the output of which is connected to the second input of the OR element, the output of which is connected to the subtracting input of the third pulse counter, the summing input of which is connected is connected with the output of the seventh element And, the outputs of the transfer pulses minus and plus of the third pulse counter are connected respectively to the first input of the fourth trigger and the first input of the second trigger *, the second output of which is connected to the second inputs of the seventh and ninth elements And, the outputs of the bits of the third pulse counter are connected to the corresponding inputs of the fifth pulse counter and the zero register, the outputs of the bits of which are connected to the corresponding inputs of the third pulse counter, the output of the first pulse shaper is connected is connected to the input. The fifth pulse counter is recorded and the second input of the control unit is written to the zero register, the first input of which is connected to the zero-setting pulse bus, and the output is connected to the zero-register entry, the transfer pulse output minus the fifth pulse counter is connected to the memory register entry. the input of the fourth pulse shaper, the output of which is connected to the second input of the first trigger, the inputs of the Reset of the third and fourth pulse counters and the second input of the fourth trigger, the output of which is connected to the input of Sat grew the seventh pulse counter.