SU421117A1 - DIGITAL AND ANALOG SQUARE CONVERTER - Google Patents

Description

I

The invention relates to a combination of computing, measuring technology, can be used in automatic control devices and other areas of technology that require a quadratic conversion on the values represented in binary code.

A device containing an operational amplifier with an average C-circuit feedback circuit is controlled, which is controlled by a linear digital conductivity, the control inputs of which are connected to the outputs of a binary counter, the input of which is connected to a counting pulse generator.

However, using such a device it is not possible to perform a quadratic transformation operation on digital quantities.

The proposed converter is characterized in that, in order to extend the functionality, an electronic analog single-pole key and a code comparison circuit are introduced into it, one inputs of which are connected to the outputs of a binary counter and control inputs of controlled digital digital conductivity, other inputs to the digital inputs of the entire device, and the output to the control input of the electronic analog single-pole switch connected between the output controlled digital digital conductivity and the input of the operational amplifier.

The drawing shows the proposed Converter.

C contains an operational amplifier 1 direct current, a binary counter 2, a generator of 3 counting pulses, a controlled linear C 1 direct conductivity 4, an electronic analog single-pole switch 5, a source of 6 direct voltage reference, a smoothing capacitance 7, constant

a resistor 8 and a binary code comparison circuit.

The input circuit of the operational amplifier 1 includes a circuit of series-connected via controlled linear digital conductivity 4 sources of the reference voltage of direct current and an electronic analog single-pole switch 5. Output of the generator of counting pulses 3 p. 1 chip to the count input of the binary counter 2, output

which is connected to the control input of the controlled linear digital conductivity 4 n to one of the go ways of the binary code comparison scheme 9, to the other input of which the converted code N is fed. Output

circuits with double-ended codes 9 are connected to the control input of the electronic analog single-pole switch 5. A feedback resistor 8 is turned on in the feedback circuit of the operational amplifier 1,

Squatted smoothing capacity 7.

The counting pulse generator 3 starts at the moment the input code L arrives. The arrival of each successive counting pulse to the counting input of binary counter 2 changes by one the least significant bit of the code in that counter, which corresponds to the next excited state of its output bit buses controlling the linear digital conductivity 4.

This conductivity changes its value in proportion to the code supplied to the switching of the corresponding bit-like conductors:

poppy

f ,,,

 max-max

e N - the current value of the manager

code;

LCH-s - maximum value of the control code;

ViiaKc is the maximum value of controlled linear digital conductivity;

/ cf is the repetition frequency of the counting pulses; (- current time;

If the conditions are met:

-f fr}

/ V. - / Ms M -. )

./sch /

there is a periodic with a period equal to T a linear change in time of the control code L and, consequently, controlled linear digital conductivity 4.

The code comparison circuit 9 controls the electronic analog single-pole key so that during the time t when the current code value N on binary counter 2 does not exceed the value of the input code N 1, the electronic analog single-pole key 5 is closed, otherwise (the current code value 7V on the binary counter 2, the value of the input code N 1) is open.

Thus, the electronic analog single-pole switch 5 closes the input circuit of the operational amplifier 1 for the time tco / V I and opens for T time (T is the period of the linearly varying control code N).

In this case, the current / in flowing into the summing point of opamp 1 from the input circuit

and, W at PG pT -f t

P.

About when; gg + t / (/ g4-1) g,

where, 1, 2 ...;

Oo is the value of the voltage of the source of the reference DC voltage 6. The average value of the current / in will be equal to

/ w yff / o / C d - / fe, (

about

where ki is the proportionality coefficient. The output voltage of the device U, if we neglect the pulses L / L (n, 2, 3 ...) after averaging at the output of the amplifier 1, is defined as;

.. U, (N, Y,

where a is the coefficient of proportionality,

equal

R is the resistance of the constant resistor 8.

With a variable reference voltage f / o, proportional to the second input value, the converter allows reproducing the multiplicative quadratic dependence of the form

z x .xl

when setting Z and direct current voltage, and Xz - in the form of a binary code.

The speed of the device is limited by the inertia of the RC filter 7, 8, which ensures the separation of the average values from the pulse train.

Subject invention

A digital-to-analog quadratic converter containing an operational amplifier with an averaging QC circuit in feedback, controlled digital linear conductivity, the control inputs of which are connected to the outputs of a binary counter, the input of which is connected to a counting pulse generator, characterized in that the goal of extending the functionality

it contains an electronic analog single-pole key and a code comparison circuit whose odd inputs are connected to the outputs of a binary counter and control inputs of controlled linear digital conductivity, other inputs to digital inputs of the entire device, and the output to the control input of electronic analog single pole key connected between the output of controlled linear digital conductivity and

the input of an op-amp amplifier.