SU1218488A1 - Device for generating amplitude-modulated signals - Google Patents

Abstract

The invention relates to radio engineering and can be used in a telegraph radio transmission equipment. The level of out-of-band components decreases with cich at an arbitrary manipulation rate. The signal from the output of the source 1 of the manipulating signals is fed to the block 8 of the front of the FAS and through the expander 2 pulses to the source 3 of the manipulated signals (IC) to start it. The pulses from IC 3 are fed to a 4 frequency divider (DF) and through a digital-to-analog converter 7 to the output. DF transmits to the counter 5 pulses each N -and pulse. Pulse counter 5 forms the address code for memory block 6. The multiplier code from memory block 6 is fed to a digital-to-analog converter 7 for changing the amplitude of pulses received from ICM 3. The voltage from the additional output of the counter of 5 pulses is fed to another input of an AMF 8. The signal from its output is controlling for RF 4 and the expander 2 pulses. The division ratio of the PM 4 varies depending on the speed of manipulation. I nl.

Description

I

The invention relates to radio. technology and can be used transmitting equipment radio line telegraph communication.

The aim of the invention is to reduce the level of out-of-band components at an arbitrary manipulation rate.

The drawing shows a structural electrical circuit of the proposed device.

The device for generating amplitude-manipulated signals contains a source of 1 manipulating signals, an expander 2 pulses, a source of 3 manipulated signals, a divider 4 frequencies, a counter of 5 pulses, a memory block 6, a digital-to-analog converter 7, a block 8 in the front section.

The device works as follows. ; .

The initial state is a steady pause. In this case, at the output of the source 1, the manipulating signals and at the additional output. counter 5 pulses - logical O, causing logical O at the output of block 8 of the front. This signal locks the divider 4 frequencies and simultaneously enters the second input of the expander 2 pulses, providing at the output of the last a signal locking the source 3 of the signals being manipulated.

The signal from the output of the source 1 of the manipulating signals is fed through the expander 2 pulses to the control input of the source 3 of the manipulated signals and enables the latter to operate. At the same time, the signal (logical I) is fed to the first input of block 8 of front 3, this moment at the second input of block 8 connected to the additional output of pulse counter 5 - logical O, therefore logical 1 occurs at the output of block 8 of front, allowing the divider 4 frequencies to work . The division factor N of the divider 4 frequency is inversely proportional to the speed of manipulation. The divider 4h of the hour passes each Nth pulse from the output of the source 3 of the manipulated signals to the input of the pulse counter 5. This pulse changes the state of the counter18488

5 pulses, i.e. changes the address code at the inputs of memory block 6. Accordingly, the change is made: the multiplier code arriving from the output of the memory block 6 to the input of the digital-to-digital converter of the D / A converter 7.

In the pause, before the manipulation signal, the multiplier is zero. With each pulse at the input of the counter 5 pulse 0, the multiplier monotonously increases according to the chosen law (linear, sinus, sin - sin or even more complex). On, signal auxiliary.

15 unmodulated oscillations from the output of the source 3 of the manipulated signals. The amplitude of these oscillations at the output of the D / A converter 7 is determined by the multiplier code at the output of memory block 6.

20 The choice of a complex law of change in the multiplier (from O to P provides for the fulfillment of all-union and international standards for the range of out-of-band emissions.

25 When the counter 5 pulses are filled, an address code is set at its outputs, calling the multiplier code equal to 1 at the input of memory block 6. Simultaneously, at the additional output of the counter 5 pulses connected with the second input. block 8 in front of the front, there is a logical 1. Logical levels on both inputs of block 8 in the front of the front are the same, therefore

 the output is a logical Oh, i locking divider 4 frequency. The formation of the front edge of the kit ends here. The output of the DAC 7 sets the maximum signal amplitude.

Upon completion of the feed from the source 1 of the manipulating signals, logical O is received at the first input of the front-end unit 8. At this moment, logical 1 enters the second input of the front-end block 8 from the auxiliary: counter 5 output. which passes through the expander 2 pulses, prolongs the resolution of the source 3 of the manipulated signals and re-enables the divider 4 frequencies to work. Mode

5 of the divider 4 frequency and the counter 5 pulses is the same as during the formation of the leading edge of the padding, and the operation mode of the block 6

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five

the memory is somewhat modified - now each pulse at the input of the counter of 5 pulses causes a monotonic decrease in the multiplier value. A technically reversible interrogation of multiplier values is performed either by recoding, or by addressing to another memory region. In both cases, the command is a signal from the additional output of the counter 5 pulses to the additional input of the memory block 6.

When the counter 5 pulses are filled, an address code is set at its outputs; the output code of the memory block 6 will be a multiplier code equal to zero. Simultaneously, at the additional output of the pulse counter 5, a logical O occurs, which arrives at the second input of the block 8 in the front slot. The presence of the same logical levels at both inputs of the block 8 at the front edge causes a logical O at its output. This signal locks the 4-frequency divider and, through the expander, 2 pulses, prohibits the operation of the source 3 of the manipulated signals, since logical impedance 2 is applied to both inputs of the 2-pulse extender.

When the manipulation rate changes, information about its value goes to the 4 frequency divider. The division factor 4 of the frequency divider is inversely proportional to the speed of manipulation so that the duration of the rounding front is approximately 20% of the duration of the elementary parcel.

Compiled by O. Geller Editor N. Shvyschka Tehred T. Tulik Proofreader S. Shekmar

Order 1139/61 Circulation 624 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch SHSh (in Patent, Uzhgorod, Proektna St., 4

2184S8

The combination of a complex law of change in the amplitude of the output signal on the fronts with the dependence of the duration of the front on the 5th speed of manipulation reduces the level of out-of-band components and ensures that all-union and international standards are met at an arbitrary speed of manipulation.

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Claims (1)

Invention Formula A device for generating amplitude-manipulated signals, containing a source of manipulating signals, the output of which is connected to the first input of the pulse expander, the output of which is connected to the input of the source of the manipulated signals, the output of which Connected to the first input of a frequency divider, characterized in that, in order to reduce the level of out-of-bandwidth at an arbitrary manipulation speed, a front-end unit, a memory unit, a digital-analogue converter and a pulse counter are introduced into it, the main outputs of which are connected to the main the inputs of the memory block, the main outputs of which are connected to the main inputs of the digital-analog converter, the auxiliary input of which is connected to the first input of the frequency divider, the second input of which is connected to the output b flash separating the front and to the second input of the dilator pulses, a first input coupled to the first input vscheleni front unit, the second input of which is connected to an additional input of the memory unit "to an additional output of the pulse counter having an input connected to the output of the frequency divider.