SU1243100A1 - Device for detecting and correcting errors - Google Patents

Abstract

The invention relates to communication technology and can be used in devices that provide noise-tolerant reception of multiple repetitive information. Fast performance. The device contains a conversion unit 1, a major block in block 1, a block 3 for determining the reliability of symbols, registers 4 and 5, an adder 6 modulo two, elements AND 7-12, elements OR 13-15, a decoding unit (DB) 16, counters 17 -19, triggers 20-24, block 25 comparisons. The information encoded by the cyclic code is fed through the element OR 13 to (DB) 16, and through block 1, which converts the serial code into parallel code, to block 3 for determining the authenticity of symbols and block 2 of the majority sample B DB 16 is checked for consistency cyclic code. If at least one of the three repeated combinations is correct, it is triggered by the trigger 20 and the element AND 8 is output. If all the combinations are distorted, then from the identical bits of the repeated combinations, block 2 forms the final com- (C (L to 00

Description

Bin, and from block 3 to register 4, the sequence 1 and O enters, in which the units are located in those positions where there was a discrepancy between the bits of the original combination.

one

The invention relates to a technique in serie and can be used in a transmission apparatus in the development of devices that provide the interference-resistant reception of repetitively repeated information.

The purpose of the invention is to increase speed.

The drawing shows the electrical structure of the device for detecting and correcting an error.

The device contains a transposition block 1, a majority sampling block 2, a symbol reliability determination unit 3, the first 4 and second 5 registers, the adder 6 modulo two, the first 7, the second 8, the third 9, the fourth 10, five and the sixth 12 elements AND , first 13, second 14 and third-15 elements OR, decoding unit 16, first 17, second 18 and third 19 counters, first 20, second 21, third 22, fourth 23 and fifth fifth triggers, comparison block 25.

Unit 3 for determining the reliability of symbols contains the first 26, second 27, third 28 additional modulo-two adders and the additional element OR 29.

The device for error detection and correction is as follows.

in a way. I

Before receiving the information, the first and second triggers 20 and 21 are transferred to one state, and the rest of the memory is zero.

Information encoded by a cyclic code, in the form of n element-code combinations, is fed to the input of the device: in block 1, which converts information from a sequence code to a parallel one.

243100

Information from block 2 through the element OR 13 enters DB 16 and further to the code if there are no errors. If an error is detected, the formation of error polynomials, 1 Il.

0

and through the first element OR 13 - to the decoding unit 16 ,, In the latter, the combinations are checked for consistency with the cyclic code.

5 In the case when at least one of the three repeated combinations is correct, it is output to the device through the first trigger 20 and the second element AND 8. With the passage of

About the last pulse of the output combination, the circuit of the device is brought to the initial state. According to the last pulse received at the input of the third code combination, it is included in

For the 5th bot, the first counter 17, calculated for counting 2 n work cycles and issuing signals at the first output after passing n cycles, at the second (2 n-1) cycles and at the third - 2 n work cycles. If all combinations are distorted, the same bits, repeated combinations from block 1 are received in block 2, which is form-: Rugs of them are the symbols of the final combination according to the majority principle, and in block 3j it implements a logical function

Y x

Block 3 provides information to the first register 4 as a sequence of zeros and ones in such a way that the units are located at those positions where there is at least one discrepancy in the corresponding bits of the original combinations.

The information that has passed the majority processing cycle in block 2 is recorded in the second n-bit register 5 is fed to the decoding unit 16, the first OR 13 element, from which it is output to the device in the absence of errors in the same way as described,. If an error is detected, then the combination received from the second register 5 is previously

0

five

one

adder 6 superimposes the first-error polynomial generated.

. The meaning of the formation of an error polynomial consists of a combination of mismatches of single error polynomials. For example, for m7 and the mismatch combination 0110100, the first single error of the type 0000100 is selected by the polynomial. If this does not eliminate the distortion, it is formed by the polynomial of the next single error 0010000, etc. This is accomplished by the scheme as follows, With the passage of the first unit of the combination of mismatches through the first element And 7, prepared by the first schema. 17 after passing the clock cycles from the moment it is turned on (and only after the device starts working, it will go on a series of clock cycles) using the first trigger 24, which also activates the third counter 19, through the third element OR 15 the second trigger 21 goes to the zero state. In this case, the permission signal for the passage of information from the first register 4 through the first element 75 is removed and the third pulse 19 is prohibited from counting clock pulses, thereby memorizing in it p, the clock number in which the mismatch occurred.

The capacity of the third counter 19 is designed to calculate the P (n + 1) work cycles. The single error polynomial generated in this way is superimposed in adder 6 on a combination of second register 5.

The result obtained enters the decoding unit 16. After (2) operation cycles (here and below, the time is counted from the moment the first counter 17 is turned on), by the signal of the first counter 17 via the fourth trigger 23. The preparation of the sixth element And 12 for the passage of information.

If an error is not detected, the decoding unit 16 provides information output through the information channel to the device output.

With the passage of 2 n cycles of operation through the second element OR 14, the prepared sixth element And 12, the first counter 17 translates the third trigger 22 into one unit, providing 43100 L

By this, the passage of clock pulses through the fifth element I 11 to the input of the second counter 18, calculated for counting ti operation cycles. 5 Block 25 (comparator), when counting by the second counter 18 of the same number) 1 clock cycle as the third counter 19, sends a signal to the second trigger 21 through the third element OR 15, setting it to one and ensuring that the remaining (p-ft,) part of the code combination, the first part of it, up to and including P; - the bit was issued by the first 15 register 4 to the closed first element I 7 before entering the next unit through the first element I 7. In addition, this signal zeroes the second counter 18 and the third trigger 22, 2Q and prohibits the passage of clock pulses through the fifth element I 11 to the input of the second counter 18. With the arrival of the combination part, the third counter 19 continues to count 25 clock pulses from the number ((1 + 1) to the number Pr (the bit number of the next unit) polynomial error with the unit only in the jij bit enters the adder 6, where the second 3Q input receives information from the second register 5. The total combination is supplied to the decoding unit 16. In case of detection After the next n series of clock passes the first counter 17 through the third trigger 22, the second counter 18 starts to work, and the second and third counters 18 and 19 are compared in block 25 and on c. Mmator 6 receives the remaining part of the mismatch combination with (n-jb), with the arrival of the next unit, the corresponding Rd-bit of the combination from the second register 5 is inverted to the adder 6. The third counter 19 starts from the number (2 1), stops with a countdown and waits for the same count at the second counter 18, after which it continues counting clock pulses from the number (/, + 1),

In the future, the device works 5 as described. If the error after applying all the single polynomials of errors is still detected, (the third counter 19 with the count

five

0

five

The (n + 1) clock signal gives an indication of the presence of a malfunctioning error, which is also used to bring the device circuit into its initial state.

Claims (1)

Invention Formula A device for detecting and correcting errors, containing a conversion unit and a majority sampling unit, first and second modulo-two registers, first and second AND elements, first OR element, decoding unit, character confidence determination unit, and comparison unit, while the outputs of the unit calls are connected to the corresponding inputs of the majority sampling block and the corresponding inputs of the block determining the reliability of characters o the output of which is connected to the input the first register whose output is connected to the first input of the first element I, the first output of the decoding unit is connected to the first input of the second element I, the output of the second register is connected to the first input of the modulo two adder, the second input of which is connected to the output of the nepWoro AND element, that, in order to increase the speed, the third, fourth, fifth and sixth elements And, the second and third elements of the CTS, three counters, five triggers were entered into it, while the block for determining the reliability of symbols contains three additional mmatora modulo two and an additional OR gate, whose inputs are connected to respective outputs of the first, second and third additional adders modulo two inputs of which are co. the corresponding inputs of the symbol reliability determination block, while the output of the additional element OR is the output of the symbol reliability determination block. The output of the majority sampling block is connected to the input of the second register and the first input of the first IL, the output of which is connected. is not with decoding block input. VNIIPI Order 3716 / .55 Circulation 816 Subscription Proizv.-polygr. pr-tie, Uzhgorod, st. Project, 4 the second output of which is connected to the input of the installation O of the first tigger, the inverse output of which is connected to the second input of the second element I, the output of which is the output of the device, and the direct output of the first trigger is connected to the first input of the third element I, and the second input : is connected to the output of the modulo two adder, and the third element of the third element is connected to the second input of the first CMM element whose third input is connected to the input of the conversion unit and is the device input, the input of the first counter and the first inputs of the fourth and fifth AND elements are the clock inputs of the device, the first output of the first counter is connected to the first input of the second OR element and the input of installation 1 of the second trigger, the direct output of which is connected to the second Eq. of the first AND element, the third input of which The direct output of the third flip-flop, whose count input connected to the output tret1) of its member OR .First input coupled to an output of the first element I, and the second input - with the output of the comparison unit and the installation inputs 1 of the fourth trigger and the second counter; the second and third outputs of the first counter are connected to the installation input of the 1st fifth trigger and the second input of the second OR element, the output of which is connected to the first input of the sixth element And, the second input and output of which connected, respectively, to the direct output of the fifth trigger and the installation input 1 of the fourth trigger, the output of which is connected to the second input of the fifth element I, the output of which is connected to the counter input of the second counter, the inverted output of the second trigger, connected to the inverse output of the third trigger and an inverse input of the fourth element I, the output of which is connected to the input of the third counter, while the outputs of the second and third counters are connected to the corresponding inputs of the comparison unit.