SU1241256A1 - Device for performing spectrum analysis - Google Patents

Description

The invention relates to computing and can be used in specialized computing devices for omnipresenting a phase and a mutual spectrum module in real time.

The purpose of the invention is to expand the functionality of the device by determining the mutual spectrum module and obtaining the spectral characteristics on a logarithmic scale.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 is a time diagram of the operation of the device when the size of the mantissa registers is equal to 8 and the size of the registers is on the order of 6

The device contains (operational) registers 1 and 2, the elements UNEQUALITY 3 and 4, trigger 5, shift register 6, trigger 7 shift-register 8, multiplexers 9 and 10, one-bit adders 11 and 12, block 13 comparison, multiplexer 4 one-bit , adder 15, register 6, the element UNKNOWNESSNESS 17, trigger 18, shift-register 19, multiplexer 20, one-digit adder 21, binary counters 22, 23, registers 24 and 25 times, multiplexers 26-28, trigger 29, multiplexers 30 and 3J, one-bit adder 32, clock input 33, input 34 specifying the number of shifts, An auxiliary input 35 of Correction, an input 36 of resolution of task 36 and a control input 37 of a trigger.

The device works as follows.

The calculated Fourier transform coefficients A (K), B (K) in the serial binary code are entered in the lower bits in the front-end registers 1 and 2, the UNEQUALITY element 3 analyzes two adjacent bits of the binary number A (K). The counting input of the binary counter 22 and the clock input of the registers 1, 2 and I6 receive clock pulses on the bus 33 (Fig. 2a). Counter 22 counts the number of shifts. With each discrepancy between the bits at the output of the element 3, a signal appears allowing the recording in register 6 of the contents of register 1, not including the most significant bit following the most significant bit in the trigger

 2

5 and the contents of the binary counter 22 in the register 24 order. The last entry occurs when the input element 3 is the first

5 signed and the next significant digit of the number. After the last entry in register 24 contains the order of the binary number A (K) - the characteristic of the logarithm, in the register

10 6 - significant part of the number without the most significant bit, in the trigger 5 - the next significant number of the number after the most significant one. The number B (K) is normalized in a similar way: under

15 by the control of the UNCONFIGURATION element 4, the significant part of the number is entered without the highest significant unit in the register 8, the order of the number from the counter 23 is put into the register

20 order of 27, following the most senior bit - in the trigger 7.

Simultaneously with the process of normalization of the numbers A (K), B (K), the norms occur, aliasing their sum. The sequential code of the sum A (K) + B (K) from the output of the one-bit adder 15 is entered forward by bits into the register 1b. Then the sum is normalized by the described method simultaneously with the normalization of the numbers A (K), B (K). The UNEQUALITY element 1 7 controls the insertion of the sum of the mantissa without the highest significant unit and the next highest rank of the mantissa in the register 19 and the trigger 18, respectively. I

After finishing entering numbers under

the action of the signal at the input 34 (Fig. 2b) for the first n pulses

40 (where n is the size of registers b, 8, and 19). a shift of the registers 6, 8 and 19 occurs, during which the binary codes contained in these registers are corrected.

 The register code b is corrected by a bit-wise summation starting with the least significant bits on the one-bit adder 11 of the binary code of the register with the direct code

50 corrections, if the contents of the trigger, and with the reverse, if - 1, the forward or reverse correction code is transmitted to the adder 11 through the multiplexer 9 5 which controls the trigger 55 ger 5. The correction is equal to the binary register code 6 shifted by 3 bits in the side of the mile; At the same time, the binary code of register 8 on adder 12, multiplexer 10 and trigger 7 and the binary code of register 19 on adder 21, multiplexer 20 and trigger 18 are corrected in the same way. On the adder 21, the mantissa of the sum and subtraction of the corrected mantissa of a larger number of bits occur simultaneously. starting with the least significant bit. A corrected mantissa of a larger number is fed to the subtracting input of the adder 21 through multiplexer 14 under the control of comparison unit 13. During correction, multiplexers 26 and 27 under the control of input 35 (Fig. 2d) are connected to the serial information input of registers 6 and 8 of the outputs of adders 11 and 12 accordingly, and the input of the register 19 is connected to the output of the adder 2I. Thus, the corrected mantissas of the normalized numbers A (K) and B (K) after correction (n shifts are in registers 6 and 8, and their orders are in registers 24 and 25, respectively. Binary logarithms of numbers are obtained, determined by the relation :

P,

P,

9M-9

7M-6 8

if, 5

if 1 ,,

where P is the order of the number A, represented in binary code with floating point

M - mantissa. . - At the same time in the register 19 received a binary code proportional to the phase-f (K) in the range of 0-45. The phase of the mutual spectrum is determined by the ratio:

Jl.

| - Mj, if UM il, 5; UM ,, 5 7Мг-2М, + 3

g, if it is 1,5; 1, +

+ M 2

Z

g M if 1,, 2; 1 ,,, gg

(2).

where M and H are the mantissas of the respective larger and smaller of the numbers A (K) and B (K).

After n correction offsets under the control of input 34 (Fig. 2b), the process of extending the obtained binary logarithms of the numbers log.A (K) and

1241

ama ten

t5

20

25

thirty

one)

40

five

2, gg

).

l

- 55 and

2564

log-B (K) with a sequential code of low bits ahead, with the serial information input of registers 6 and 8 being connected under control of 35 (Fig. 2d) serial outputs of registers, 24 and 25 orders through multiplexers 26 and 27, respectively. The shift control inputs of the shift registers of the mantissas 6, 8, and 19 receive shear pulses for performing correction and adjustment (Fig. 2b), and for orders 24 and 25, the pulses for lifting (Fig. 2c).

Binary logarithms of numbers are received by a serial code at the inputs of multiplexer 28, at the output of which, under the control of block 13, a binary logarithm of a larger number appears and is fed to the first input of a one-bit adder 32. Simultaneously with the extension of the logarithms of numbers it is pushed from the serial output of register 19- ( The first digit is the binary code of the low order bits. C (nl) -ro bit register 19

phase code at cf comes in second

the input of the adder 32, at its third input receives an adjustable binary phase code, shifted by two bits in the direction of the lower bits, from the (n-2) -th register output 1 9,

The correction of the phase code is as follows.

In the trigger 29 in the last correction cycle under the control of the input 36 of FIG. 2e) the most significant bit of the code is remembered. The output of multiplexer 30 transmits the forward or reverse code of the contents of register 19, shifted by two bits towards the lower bits, depending on the contents of trigger 29 - l or O, respectively. Next, the corrected phase code is fed to the input of the multiplexer 31, which, under the control of input 37 (Fig. 2e), passes 32 five minor bits to the input of the adder, and the remaining bits are filled with units. At the output of the adder 32, a serial code (lower bits ahead) of the binary logarithm of the mutual spectrum modulus .logj, C (K) is formed. Accordingly, the mutual spectrum modulus is determined by the following relationship:

log ,, C (K) where c is a binary code, proportional to

(K) + N- (H), with A (K) B (K)

(3) logj, B (K) + 1 (tf), at. A (K) B (K),

now

and phase C | (K) in the range of 0-45.

Thus, the modulus of the spectrum in the proposed one is determined by the binary number and by the two phases of the mutual spectrum, the ratios obtained by (1) and (2) in (3):

f (l |)

7G № if if 0.5 | 1-Vj, priGs | g 0.5 36M1 + 9M5.-36

ten

(four)

Thus, the mutual spectrum modulus in the proposed device is determined by the binary logarithm of a larger number and by the binary code of the phase of the mutual spectrum, i.e. according to the ratios obtained by substituting (1) and (2) into (3):

P,,, if 1 M, -. ,five; 1 i M, + M ,, -. 15; , 5 34M, + 27Mi-41

P,

..

32

34М, + 7МгЗЗЗ 32.

if l, 5iM, 2; 1.-G M ,, h-M I, 5; cf 0.5 if UM, 1.5; 1, 5 e M + M 2; tf with 0.5

(51 P ,, ---., If 1.5 fM, 2;, 5iM, + M,, 5,

P, if 1, -2; 1, 5 M, 4M 2: su 0.5,

where M,, M are the man-ss of the corresponding mantissa, not counting the older one, are of larger and smaller numbers; th bit and 6 bit),

P, the order of a larger number. Let the numbers of the fast Fourier transform get from

Let's consider an example of calculating the log -:., .. A (K) and B (K) in a code with a fixed

the rhymes, the module and the phases to the proposed parts (the numbers are indicated by the device as such (8 bits are used),

131211 109, 876.543210 О 1 1 О 0000000000 О О 11 011101011

0111010111

Oh oh

one

Respectively

B (C) 432; log.B (K) 10.7927;

A (K), logjA (K) n, 5850;

Cf (K) arctg HI arctg 30 °;

C (K) fA (K) + B (K) 3.46; logjC (K) l1,791.

After normalizadii in the form of a floating number, they have the form:

A (K) 1011, 1100000000 (last

P .

M

entry in the 13th cycle);

B (K) 1010, 1 lOmOlOl (last

P. M, entering in the 12th cycle);

A (K) -bB (K) (last

M, M entering in the 14th bar).

The last entry in register 6 is the code 10,000,000, in the register

Thus, the mutual spectrum modulus in the proposed device is determined by the binary logarithm of a larger number and by the binary code of the phase of the mutual spectrum, i.e. according to the ratios obtained by substituting (1) and (2) into (3):

line 8 - 10111010, in register 19 - 00101110 - mantissas without the most significant units, in register 24, - 00101, in register 25 - 001010, in triggers 5, 7 and 18 - 1,1.0, respectively.

After correction, the binary code of register 6 is equal to:

10,000,000 OOORP i 1 10001111 code, register 8:

10111010

V, 11000010

Under the control of the comparison unit 13, the output of the multiplexer is 0001111, since the number A (K) is greater than the number B (K).

After correction in the register 19 is the code:

00000 O 01110000

10100011 The resulting code is proportional

T-jo, i.e. at 28.65, i.e. error

is 1.35,

The resulting logarithms of numbers are:

Log A (K) 1011, 1000111

and the true value of the logarithm of the number A (K) in binary code is 1011; 10010101

log B (K) 1010, 11000010, is the true value of 1010, 11001010

The error in determining the logarithms in this case does not exceed 0.1 dB.

In the last tact of correction in. the trigger 29 is remembered by the unit (the highest bit of the received code is cf s, that is, qi j 70.5). In the process of extending the logarithms on the adder 32, the logarithm of the number A (K) is summed, the direct code shifted by two bits towards lower registers 19 under the control of trigger 29 and multiplexers 30 and 31, and shifted by one register bit nineteen:

A (K) + 00101i 100011 1

"000000 0101000

At the output of the adder 32 of the receive serial binary code starting with the lower bits of the module of the mutual spectrum:

M

istiknoe

i-og2C (K) ioi 1-, nooiooo,

the value in the binary code is 1011 ,, 11001010, i.e. the error of determination of the module does not exceed - 0.02 dB

per octave.

Claims (1)

Invention Formula A device for spectral analysis, containing three registers, a, a comparison unit, four multiplexers, three shift registers, three elements UNACTICAL, three flip-flops, four adders, the control input of the first multiplexer connected to the output of the comparison unit, the first and second inputs of which are respectively, the real and imaginary inputs ten 15 0 five P five 0 five five parts of the operand of the device, the first input of the comparison unit is combined with the first input of the first element UNEMATICAL AND information input of the first register, the output of the higher bit of which is connected to the second input of the first element UNEMPLARITY, the output of which is connected to the clock input of the first shift register and the clock input of the first trigger, output which is connected to the control input of the second multiplexer, the output of which is connected to the first input of the first adder, the output of which is connected to the first information the input of the first multiplexer, the second information input of which is connected to the output of the second adder, the first input of which is connected to the output of the third multiplexer, the control input of which is connected to the output of the second trigger, the clock input of which is connected to the clock input of the second shift register and connected to the output of the second of the UNCHARTERNESS element, the first input of which is connected to the output of the cTapniero bit of the second register, the pyromicopic input of which is combined with the second input of the second element of the UNEMINABLE and in By the first input of the comparison unit, the output of the first register is connected to the installation input of the first trigger and the information input of the first shift register, the outputs of the first and second bits of which are connected respectively to the information input of the second multiplexer and the second input of the first one from the mmmator, the output of the second register is connected to the installation input of the second trigger and the information input of the second shift register, the output of which (n-3) -th and n-th bits of which are connected respectively to the information input of the third multiplex Lexus and the second input of the second adder, the output of the first multiplexer is connected to the first input of the third adder, the second input of which is connected to the output of the fourth multiplexer, the control input of which is connected to the output of the third trigger, the clock input of which is combined with the clock input of the third shift register AND connected to the output third ele THE UNCHARTERNESS element, the first input of which is connected to the output of the senior bit of the third register, whose information input is combined with the second input of the third element UNEMATICAL AND connected to the output of the fourth adder, the first and second inputs of which are combined respectively with the first and second inputs of the comparison unit, the output of the third register connected to the setup input of the third trigger and the information input of the third shift register, the outputs of the (n-3) -th and n-th bits of which are connected respectively to The fourth multiplexer's third input and third input of the third adder, the output of which is connected to the serial input of the third shift register, the clock inputs of the first, second and third registers are combined and are the clock input of the device, and the control inputs of the first shift, the second and third shift registers are combined and are the input of specifying the number of shifts of the device, characterized in that, in order to extend the functionality by defining the module spectrum and obtaining spectral characteristics on a logarithmic scale, two counters, two order registers, the fourth trigger, the fifth, sixth, seventh, eighth and ninth multiplexers, the fifth adder, and the counting inputs of the counters are connected to the clock input of the device , the information output of the first counter is connected to the information input of the first order register, the recording resolution input of which is connected to the output of the first element INEQUALITY, and the low-order output of the first order register is connected pervsm with the data input of the fifth multiplexer a second data input which is connected to vghodom second adder and an output of the fifth multiplexer is connected to the input of sequential recording information of the first shift register, the second data output the counter is connected to the information input of the second register of orders, the permission input: whose records are connected to the tricks of the second element UNEQUALITY, and the low-order output of the second order register is connected to the first information input of the sixth multiplexer, the second information input of which is connected to the output of the third adder, and the output of the sixth multiplexer is connected to the input of the sequential recording of information of the second shift register; the output of the n-th bit of the first shift of the register is the output of the real hour These operands, devices and connected to the first information input of the seventh multiplexer, the second information input of which is connected to the output of the n-th bit. The second shift register is the imaginary input of the imaginary part of the device, the control input of the seventh multiplexer is connected to the output of the comparison unit, and the output of the seventh multiplexer is connected to the first input of the fifth adder, the second input of which is connected to the output (ni) -ro of the third, shift register, the output of the (n-2) -th bit, which is connected to the informational In the course of the eighth multiplexer J, the control input of which is connected to the inverse output of the quadruples of the trigger, the setup input of which is connected to the output of the fourth adder, and the clock input of the fourth trigger is connected to the recording enable input of the device, the output of the eighth multiplexer is connected to the information input of the ninth multiplexer the control input of which is the start-up input of the device, and the output of the ninth multiplexer is connected to the third input of the fifth adder, the output of which is the output of the logarithm Odulov spectrum mutual device control inputs of the first and second shift registers connected to the orders of the input device specifying number of shifts, and yn ravl yu1tsi: e n inputs and addition. the sixth multiplexers are combined and are the control input of the device Correction. D. (k) Phi5.1 1t sh tt 1ppt1 M} 11shi sh shshsh {psh.  1} pt8lt-pshchyu go .. FROM 130B code entered iQgM ugiA {i (} lsh1ll t shshp .ratplpll .. ™ ™ ™ ™ ™ pshtg1 llgsh1shg- ™ t IT s " ™ f IT s " ™ f TamnJtH JS i / a.2