SU1239874A1 - Method and apparatus for entering additional signaal in multichannel communication systems - Google Patents

Abstract

The invention relates to telecommunications and m. used to synchronize multichannel data transmission systems using Walsh functions. The noise immunity of synchronization by the group signal increases, in which there are no signals from the Rademacher functions. The unit contains a block. correlation reception 1, processing unit 2 mismatch signal (CP), analyzer 3 CP, r-r 4 clock pulses, driver (F) 5 control signals, F 6 reference signals, additional F 7 reference signals, F 5 contains a counter modulo M 8, a controllable key 9 and an inverter 10. The analyzer 3 CP contains an el OR 11, a reversible counter 12, an el 2I-NOT-13 and n signal processing circuits, each of which consists of keys 14 and 15 and prohibition ban 16. / z.p. f-ly, 2 ill. with S (L go SAE SO CX) - 4

Description

f1239874

The invention relates to telecommunications and can be used to synchronize multichannel data transmission systems using Walsh functions.

The purpose of the invention is to improve the synchronization noise immunity on a group signal in which there are no signals of the Rademacher function.

Fig. 1 shows a structural 10 electrical circuit of a synchronization device based on a group signal in multichannel communication systems; Fig. 2 shows timing diagrams, and the device operation is as follows. 15

: A group signal synchronization device in multichannel communication systems contains block 1 correlation reception., Processing block 2

mismatch signal (СР), analyzing; an instantaneous jamming 3 of the mismatch signal (СР) is being read, and values of FVK are read. Signals of the values of FVC generator 4 clock pulses, form (Fig. 2e, g,) are sent to the corresponding inputs of which reference signals come from the outputs of the driver 6, the reference signal in (Fig. 26) and the additional driver 7 of the reference signals (Fig. 2). These reference signals are Rademacher functions of N orders in accordance with the Walsh signal being processed. From this point on, the cross-correlation function (PVC) of the input group signal and reference signals is calculated in the correlators of the correlation reception unit.

At the end of the first integration cycle from the output of the counter 8 modulo M to the second control input of the correlation reception unit 1, a short pulse ends the cycle (Fig. 2n), under the action of which

globalizer 5 control signals, shaper 6 reference signals, additional shaper 7 support-Hbix signals, and the composition of the control signal generator 5 includes a counter 8 modulo, M, control key 9 and an inverter 10, and the analyzer 3 CP includes item OR

. 11, a reversible counter 12, an element 2I-NOT 13 and n signal processing circuits, each of which contains first and second keys 14 and 15 and an element 16 of the prohibition.

The group signal synchronization device in multichannel communication systems operates in the following way.

The input group signal (Fig. 2a) is fed to the information input b. Pok 1 of the correlation reception, the first control input of which and the control input of the control key 9 receive the enable signal 1 from the output of the inverter 10 (Fig. 25}, Sequence clock pulses from the generator output 4 clock pulses (fig. 2) are fed to the input, counter 8 modulo M through the open control key 9 and to the input of the driver 6 of the reference signals (fig. 2n).

In block 1 of the correlation reception, under the influence of the enable signal 1, the first keys are opened, the input group signal passes to the inputs of the correlators, to the reference keys

the current inputs of the processing unit 2, in which the split is carried out

25 of these signals and the formation of them discrete signals (Fig. 2nd, 1) mismatch, arriving at the information inputs of the first keys 14, -14, and elements 16 "-1bl

30 ban n signal processing circuits. Simultaneously, the pulse of the end of the cycle from the output of the counter 8 modulo M is fed to the control inputs of the first key 14, the prohibition element

,, 1, second keys, and a tuning input of a parallel recording of a reversible counter 12 (Fig. 2h).

40

45

If on the first run of the processing unit 2 there is a single potential (), then the pulse of the end of the cycle through the open first key 14., enters the information input of the second key 15 and closes it to pass the end of the pulse to the first input of the reversing counter 12. 15.

12. All other second keys

55

 open for passage of the pulse of the end of the cycle to the corresponding inputs of the reversible counter 12 (Fig. 2p, c, T).

If t 0, then the pulse of the end of the cycle does not pass to the information input of the second key 15, which remains open, and through the open element 16, the prohibition enters the information input of the first key 14- and the element 16 prohibition.

Instantaneous reading of PVC values occurs. The signals of the values of PVCs (Fig. 2e, g,) are received at the respective inputs of which the reference signals are received from the outputs of the driver 6 of the reference signal (Fig. 26) and additional. body shaper 7 reference signals (Fig. 2). These reference signals are N-Order Rademacher functions in accordance with the Walsh signal being processed. From this point on, the correlation function of correlation reception unit 1 calculates the cross-correlation function (PVC) of the input group signal and reference signals.

At the end of the first integration cycle from the output of the counter 8 modulo M to the second control input. block 1 of the correlation reception receives a short pulse at the end of the cycle (Fig. 2n), under the action of which

the current inputs of the processing unit 2, in which the split is carried out

These signals and the formation of them discrete signals (Fig. 2nd,, 1) mismatch arriving at the information inputs of the first keys 14, -14, and elements 16 "-1bl

ban n signal processing circuits. Simultaneously, the pulse of the end of the cycle from the output of the counter 8 modulo M is fed to the control inputs of the first key 14, the prohibition element

1b, the second keys and the building input of the parallel recording of the reversible counter 12 (Fig. 2h).

If on the first run of processing unit 2 there is a single potential (), then the pulse of the end of the cycle through the open first key 14., enters the information input of the second key 15 and closes it to pass the pulse of the end of the cycle to the first input of the reversible counter 12. 15.

12. All other second keys

 open for the passage of a pulse at the end of the cycle to the corresponding inputs of the reversible counter 12 (Fig. 2p, c, T).

If t 0, then the pulse of the end of the cycle does not pass to the information input of the second key 15, which remains open, and through the open prohibition element 16, it enters the information input of the first key 14 and the prohibition element 16.

The change in the state of the second key 15 provides compensation for the synchronization mismatch:, as follows. Under the action of a pulse at the end of the cycle, the binary number i, 2 1 / is written in the reversible counter 12 (Fig. 2v ,, x). At the output of the OR 11 element, a single potential appears (Fig. 2u.), Under the action of which the element 2И-НЕ 13 opens for the passage of clock pulses to the countdown input of the reversible counter 12 (Fig. 2i). At the output of inverter 10, a zero potential appears, under the action of which. The control key 9 and the first keys in the correlation reception unit 1 are closed and the input group signal is stopped. The up / down counter 12 starts to operate in a countdown mode. In this case, after the return count of one clock pulse at its input, the reversible counter 12 is zeroed. At the output of the OR 11 element, the initial state is set to zero and a new receive cycle of the input group signal begins.

In the next cycle, the pulse of the end of the cycle is formed again, under the action of which a new binary number (L J 0) is written into the reversible counter 12. At the time of the reverse counting of the reversible counter 12, the reception of the input multicast signal is stopped, thus compensating for the timing detuning of the order with I. This will continue until the mismatch between the Walsh function generators of the receiving and transmitting half sets is completely compensated. -

When this is achieved, all the BANKS 16, -16 elements are open to zero potentials from the inputs of the error signal processing unit 2 and the ICC pulse through the open BANES 16, -16 elements to the output of the synchronization device using a group signal in a multichannel system and is the output of the frame alignment signal.

When using bitwise compensation, no more than a cycle of receiving information is required to synchronize half sets.

5 f5 20 25

,

0

five

Claims (3)

1. A synchronization device based on a group signal. In multichannel communication systems comprising. Sequentially connected a clock generator, a driver of control signals, a driver of reference signals, a correlation reception unit, a error signal processing unit and an error signal analyzer, kt, active the input of which is connected to the output of the clock pulses, and to the combined control input of the error analyzer and the first control input of the correlation unit a - the second output of the control signal generator, the third output of which is connected to the second control input of the correlation reception unit, the information input of which is the device input, characterized in that, in order to improve the synchronization immunity over the group signal, in which there are no function signals Rademacher, an additional driver of the reference signals was introduced into it, while (n-1) and p-th outputs of the driver of the reference signals are connected to the additional inputs of the correlation unit h Through the additional reference driver, the first output of the error signal analyzer is the output of the device, and the second output is connected to the input of the control signal generator. 2. The device according to claim 1, characterized in that the error signal analyzer is made in the form of n signal processing circuits, each of which consists of a prohibition element combined by the information input and a first key, the inverse output of which is connected to the information input of the second key, and the inverse the output of the second key of each of the p signal processing circuits is connected to the corresponding information input of the record of the reversible counter, the outputs of which through the series-connected element OR and element 2I-NOT connect These are connected to the reverse count input of the reversible counter, the strobe input recording of which is combined with the control inputs of the second keys of the signal processing circuit and the control inputs of the first key and the inhibit element of the first signal processing circuit, the output of the inhibitor element of each transmitting signal processing circuit is connected to the combined information inputs of the first key and the prohibition element of each subsequent signal processing circuit, and the output of the prohibition element of the nth signal processing circuit is the output of the signal analyzer matching, and the control input of the first key of the first signal processing circuit is a control input, the information inputs of the first keys of the n signal processing circuits are informational inputs, and the second input element 2-NOT - clock input of the analyzer. mismatch signal. 3. The device according to A.1, about tl and - preferably with the fact that the driver of the control signals is made in the form of serially connected The Q of the inverter, the control key and the modulo M counter, wherein the inverter input and the control key control input are respectively the input and clock input of the control signal, the outputs of the inverter, the control key and the modulo M counter, respectively the first, second and third outputs of the driver control pulses,