SU1238217A1 - Method and apparatus for producing commands of revolution relay - Google Patents

Abstract

1. A method of generating the relay speed commands, including converting the shaft rotation speed into a sequence of pulses proportional to it in frequency, summing these pulses in a predetermined period of time of the measuring cycle, coitrol in the counting process to match the result of the summation to the threshold, remembering the fact of comparison with a threshold, the generation of a command signal and cancellation of the summation result at the beginning and end of the measuring cycle, characterized in that, in order to improve noise immunity, after reaching the correspondence of the result of the summation to the threshold value, the summation of pulses continues until the end of the measuring cycle control of the compliance of the result of the summation with the additional threshold value, in the absence of the fact that the current value is compared with the additional the threshold for the measuring cycle, at the end of the measuring cycle, the formation of the command signal and the aiulation of the memorization and summation results, and if it is present, block the formation of the command signal by canceling the memory result, and at the end of the measuring cycle the summation result is also satisfied relations: f 2d - 2 D /,. 2d - 2p; Гп 2 /, where is the threshold value; , t is the specified time interval of the measuring cycle; fc is the threshold frequency of the useful signal; Sfl - additional threshold value; fn is the frequency of interference; t is the duration of interference; 7n - the period of the following packets of interference; L / (- increment of the current value of the frequency of the useful signal. 2. Method according to claim I, characterized in that, in order to prevent generation of false commands in the event that the result of summing the maximum value is exceeded after reaching the result of the summation by an additional threshold value, the summation of pulses stops and resumed after the end of the measuring cycle. 3. A device for implementing the method for generating the rotational speed relay commands according to claim 1, comprising a rotary frequency converter rotary, under The key to the counting input of the summing register, the first bit outputs of which are connected to the inputs of the first NAND element, the reset input of the summing register is connected to the timer output, the RS flip-flop, the second and third NAND elements, the AND element and the outputi (L S Y Od og yu

Description

A new bus, characterized in that in the device, the second one-bit outputs of the summing register are connected via the second AND-NOT element to the first input of the AND element, the second input of which is connected to the output bus and the third input of the IS-NOT element, the first input of which is connected to a single the output of the RS flip-flop, the single input of which is connected to the output of the first NAND element, and the zero input to the output of the I element, and the output of the timer

Claims (1)

one The invention relates to energy and can be used to work in the system of automatic control of hydroelectric power plants. The aim of the invention is to increase the noise immunity and prevent the generation of false commands in the event of exceeding the result of the summation of the maximum value. The drawing shows a functional diagram of the device for implementing the method of generating the relay speed commands. The device for implementing the method of generating the rpm relay commands includes a shaft of the hydraulic unit 1, a pulse frequency converter of rotation consisting of a capacitive sensor 2, an automatic generator converter 3, a selector-generator 4, a summing register 5 (pulse counter), timer 6, and AND-7 elements 7 -Y, expander 11 pulses, triggers 12 and 13 of type RS, element I 14 and output bus 15. The device operates as follows. Converter 3 converts the frequency of rotation of shaft 1 into a sequence of pulses whose frequency is proportional to the frequency of rotation of the shaft. These pulses, passing through the selector driver 4, are fed to the counting input of the summing register 5. Under normal operating conditions (in the absence of interference), the maximum code combination at the outputs of register 5 corresponds to the current shaft rotation frequency. If the shaft rotation frequency does not exceed a certain predetermined value, then the sum register 5 does not count up to the state when the AND-NE element 8 is triggered, and is reset to zero state by the signal from the output of timer 6 via the AND-NOT element 10. The trigger 12 remains in the zero state, preventing the pulse from passing to the output of the NAND element. 9. If the rotational speed of the shaft exceeds a certain predetermined value, then the output through the pulse expander connected to the second input of t; retego element AND-NOT. 4. The device according to claim 3, characterized in that between the timer output and the reset input is summed, its register includes an additional AND-NOT element, the other input of which is connected to the single output of the additional RS flip-flop, the single and zero inputs of which are connected respectively to the output timer and the output of the second element is NOT the element And-: NOT 8 forms the logical level "O which sets trigger one to one. At the same time, at the input of the element AND-HE 9 connected to the trigger output | 2, there is a logical level" 1 and when the output pulse appears the extender 11 and its arrival at the input of the element AND-HE 9 at the output of the latter appears the level of the logical 0, which is a relay command signal. The indicated signal, through element 14, resets trigger 12 to the initial zero state. At the same time, the time parameters of the expander 11 and the trigger 12 at the input R are chosen such that the retention time of the logic level "1 at the inputs of the AND-HE element 9 is sufficient to turn on the actuators. When a summing register 5 arrives at the counting input, together with the useful information signals of interference pulses, the frequency of which is much higher than the frequency of the useful signal, the AND-NE element 8 is triggered, the trigger 12 is set to one. After some time, the element AND-NOT 7 is triggered, dropping the trigger 12 through the element 14 to the zero state. As a result, when a signal from the output of timer 6 appears at the output of the expander 11, a pulse is generated that does not pass to the output of the NAND element 9, since the specified element is blocked by a logic level "O from the output of the trigger 12." The method of generating the RPM relay commands and the device for its implementation effectively prevent the appearance of spurious output pulses when the following conditions are met: t Un - Sn, where 2p is the number of pulses corresponding to the threshold value (at which the element IS-NE 8 is triggered); 2d is the number of pulses corresponding to an additional threshold value (at which the NAND 7 element is triggered); fn is the frequency of interference; t is the duration of interference, while En. /with, where fc is the threshold frequency of the useful signal at the input of summing register 5; D / (i Ed - En, and for the period following the packets of interference Gp 2t, where Tn - the period of the following packets of interference; D / (- increment of the current frequency of the useful signal. In addition, the presence of the expander 11 pulses, triggered by the differential over t - a predetermined period of time, the change of logic level talents from the output of the triterion cycle, defined by measure 6, eliminates the appearance of a false output command signal when the timer 6 is exited, and RS trigger 13 and the element AND NOT 10 allows timer 6. In addition, the condition for the operation of the invention is the limitation on the rate of change of the frequency of the input signal, namely increase the reliability of the device by increasing the frequency of interference. D / (i Ed - En, and for the period following the packets of interference Gp 2t, where Tn - the period of the following packets of interference; D / (- increment of the current frequency of the useful signal. logic level from the output of timer 6, eliminates the appearance of a false output command signal when timer 6 fails, and the presence of the RS flip-flop 13 and the NAND 10 element allows improve the reliability of the device when increasing the frequency of interference.