SU1238100A1 - Multichannel model identification device - Google Patents

Abstract

The invention relates to computing and can be used to process information of the percentron type. The aim of the invention is to improve the accuracy and enhance the functionality by using information about the approximate object model. The device contains a control unit 1, a memory unit 2, a minimum signal selection unit 3, processing channels 4, adaptive functional transducers 5 (AFP), switches 6, elements 7, functional transducer 8. 2 cnf. .4 Il W C1J i2: J .j GLj (pue.i

Description

The invention relates to computing and can be used for processing information in self-storing xx systems for processing perceptron-type information.

The purpose of the invention is to improve the accuracy and enhance the functionality by using information about the approximate model of the object.

Figure 1 presents the scheme of the proposed device; Fig. 2 is a control block diagram; FIG. 3 is an adaptive functional converter circuit; figure 4 - diagram of the task assignment factors.

I

On the figures accept the following

designations: control unit 1, memory unit 2, minimum signal selection unit 3, processing channels-4, adaptive functional transducers 5 (AFP), switches 6, And 7 elements, functional; converter 8, elements OR 9 and 10,

ok L memory, ol j of selection of the mini signal, channels- 4 processing-;, adaptive functional converters 5 GAFP). switches 6,

LINE: converter o, elements OR 9 AND 10,

Trigger 1 1, generator; tor 1 2 rectangular pulses. counter I3, decoder 14, switch 1-5, element OR 16, comparison circuit 17, decoder 18, counter 19, delay element 20, element OR 21, And elements 22, decoder 23, counter 24, decoder 25, And 26, triggers 27, elements OR-28, elements AND 29, triggers 30, decoder 31, elements 32 and 33. Delays, element OR 34, trigger 35, element ШШ 36, start input 37, elements 38 and 39 of delay, element OR 40, switching element 41, generator of 42 square-wave pulses, counter 43, element OR 44, decoder 45, delay element 46, element OR 47, counter 48, delay element 49, decoder torus 50, coupling 51, delay element 52, square pulse generator 53, counter 54, element. OR 55, delay element 56, decoder 57, communication 58, delay element 59, communication 60-65, elements OR 6 67, communication 68.69, element OR 70, coefficient setting block 71, function value calculation block 72, discriminator 73, comparison circuit 74, switching element 75, register 76 element OR 77, comparison circuit 78, communications 79-83, AND elements 84, 85, adaptation channels 86, console registers 87

002

tantas, switching elements 88, shift registers 89, switching elements 90 - 92, registers 93, switching elements 94, elements OR 95, register 96, adders 97 modulo two, 98 square impulse generator, delay element 99, OR element 100 , element 101. Delay.

The device works as follows.

The source data for the identified object is recorded in block 2 of the memory in the form of two parts: the training and testing sequences. On the functional converter 8, an approximate mathematical model of the object is realized with the value of the selection criterion at the points of the check sequence. The functional transducer 8 differs from the AFP 5 class of reproducible functions. AFP 5 is intended for the implementation in the general case of private models of a very limited class.

.four;,; -aota, xii. + c3jX; 5, + a, x, x; i, (l)

0

five

0

five

five

where x-, y,,

X, - - input arguments; Y, - output variable

private model; а.а, а2, а, - coefficients of particular models.

The functional converter 8 reproduces a wide class of functions of one, two, and several variables in the form of which an approximate object model can be specified.

The control unit 1 performs the initial connection of switches 6 m of processing channels 4 so that the values of any two input variables are sent to each channel via the communication of switches from memory block 2. These variables in each of the m processing channels from the outputs of the switches 6 arrive at the inputs of the arguments of the AFP 5, the first inputs of which receive the learning sequence points from block 2. The control unit 1 transfers all the AFP of all channels to the adaptation mode, after which it ends in the 1st channel (, t-1) from the output of the end of the adaptation of the AFP 5 of this channel, a signal is output to the input element And 7 of the same channel. But a signal to you} 4de of the element AND 7 of the 5th channel can only appear if its

3 1238100 - 4 second input a signal comes from the elec- tal of two signals: a signal from

And 7 (i + l) -ro (, m-2) channel (or the signal from the output of the AFP-3 adaptation end of the m-th channel for the And (tn-l) -ro channel element) ends - adaptation mode in (i + 1), (i + 2) ,, .., m channels. After the end of the mode - adaptation in each of the m channels

the output of the AFP evaluation of the 5th channel and the signal from the output of the 3 (i-l) -ro channel unit, i.e. the minimum signal of 5 (i-1) signals from the AFP evaluation outputs of the 5 first (i-1) channels. Thus, at the output of block 3 of the 1st channel there is a minimum signal from 1 signal, and at the output of the block from the output of element 7 of the first channel 10 ka 3 (t + 1) -th channel - the minimum in block 1 of control to the input end - a signal from the entire set of signals with none of the settings is given a signal about the outputs — evaluation of the AFP 5 of all (t + 1) completion of the AFP setup of all channels. channels. Based on signals from you- Upon receipt of this signal, block 1 of moves, unit 3 of all channels, control unit 1 translates AFP of all channels 15, compares the output of units 3 of all channels with the output of unit 3 (t + 1) channels, determines the channel in which the signal at the output of the evaluation of the AFP 5 has minimals in the mode of evaluation of the resulting particular models. A signal about the start of the evaluation mode of the particular models by the block 1 control is issued in block 2

memory, which is at its output at 20 f ° value. Thus, the feeds of all AFPs are points of the check sequence. In the evaluation mode, in each channel, the AFP counts at the points of the check sequence the value of the next cycle of operation of the sequence of blocks 3 of all channels to exclude the best one from the analysis. model. This is accomplished by the control unit by issuing a corresponding 35 to the input.

40

Well selection criteria for the resulting private model. At the end of the evaluation mode, in each of the Un channels, the output of the evaluation of the AFP 5 model appears, the signal of the corresponding block 3 signal, pa so. proportional to the criterion of the corresponding permitting selection output at the points of the check sequence of the private model of this AFP 5. This signal arrives at the input of the minimum signal selection unit 3, the second input of which receives a signal from the output of the previous channel 3. In the first processing channel to the second input of the block 3 with

The output of the control block G in the model selection mode receives a signal that is known to be larger than the signal from the output of the evaluation of any AFP 5. Therefore, block 3 of the first channel is based on the signal emitted from the output of block 1 control 45 Selected (channel image: the models of the first row of selection are passed, the signal from the output of the first channel AFP 5 evaluation is sent to its output.In block 3 of the second channel two signals are compared: a signal from the output 50 an approximate object model that evaluates the AFP 5 first channel and torus based on already I have a signal from the output of the AFP 5 evaluation of the second channel.Minimum (of these two signals, the signal from the output of the

3 of the second channel is fed to the input 55 worse than the particular models received by block 3 of the third channel and so on. in the first selection row, in block B i-OM (, in), the information processing unit 3 selects the mini control unit 1 of the control. This signal blocks the signal from the AFP 5 evaluation output and, therefore, when the sequence of blocks 3 of all channels is repeated, the specified signal does not participate in the selection section and as a result, the second largest minimum signal is extracted. This process continues until a given number of the best particular models of the first row of selection is allocated. In the mode of selection of the best private models of the first row and selection is involved (t + 1)

which are used in the second selection row. In this case, on the second selection row, the information object can be used by b and is located in the functional converter of the 8 (m + l) channel. If this model

model selections (t + 1), the channel is not included in the number of channels using

A processing channel is made in which the best particular model of the first selection row is located. To highlight the second best model you need to

block 3 of all channels to exclude from the analysis found the best. model. This is accomplished by the control unit by issuing to the input a corresponding

corresponding block 3 signals, pa with the appropriate enable output

  Selected (channels form models of the first row of selection, an approximate model of the object, which was obtained on the basis of the already available

block 1 control This signal blocks the signal from the AFP 5 evaluation output and, therefore, when the sequence of blocks 3 of all channels is repeated, the specified signal does not participate in the selection section and as a result, the second largest minimum signal is extracted. This process continues until a given number of the best particular models of the first row of selection is allocated. In mode. selection of the best private models of the first row and selection is involved (t + 1)

  Selected (channels form models of the first row of selection, an approximate model of the object, to the torus is obtained on the basis of already having

which are used in the second selection row. In this case, on the second row of selection, the Selected can be used (the channels form models of the first row of selection, an approximate model of the object that has been obtained on the basis of

worse than private models obtained in the first row of breeding, then

The current bb is an information object and is located in the functional converter of the 8 (m + l) channel. If this model

worse than private models obtained in the first row of breeding, then

model selections (t + 1), the channel is not included in the number of channels using

51

which form models of the second row and selection. If the approximate model of the object exceeds the models of the first row of selection in accuracy, then the models of the second and subsequent series of selection will be more accurate.

The X channels selected by the control unit 1 and the (that + 1) -th channel (if it is not among the best) are considered to be occupied and then used for storing private models of the first row of selection. The remaining channels are released (hereinafter they are used to obtain models of the second row of selection). Upon completion of the NII of this mode, the control unit 1 outputs control signals to the switches 6 of all the free processing channels and connects the output pairs of the channels of the first row to the inputs of the free channels. After that, all free channels are again switched to the adaptation mode, after it to the evaluation mode, then to the selection of particular second-row models, and so on. This cycle is repeated until there are more free channels on the next row. The channel with the minimum value of the selection criteria contains the output of the object model.

The operation of the device begins with the issuance of a start signal at the start input 37. This signal is used to reset the triggers 11., 27,30,35, the counter 24,43,54, the decoder 31, and through the delay element 39 and the OR 4 element the generator 42 is started, the pulses of which arrive at the counter 43, the output which is connected to the decoder 45 defining the addresses of the points. training sequence in memory block 2. The AFP 5 is brought into operation by a signal from the output of trigger 35 through communication 64, which appears at the output of trigger 35 when the Start signal from input 37 arrives at its single input (via delay element 32 and OR 34). This signal comes to the input element

, And 84, whose second entrance is at. each channel 4 receives a signal with

the output of the corresponding trigger 27 which generates an enable signal to the AND 84 element only in the case when channel 4 is free, i.e. the corresponding trigger 27 is in

j

0 5 0 5 0

,

five

00 6

zero state. The signal from the trigger output 5 and 35 in each AFP 5 in registers 76 through the elements AND 84 and OR 77 is entered to the maximum possible number, and in blocks 71 the initial values of the coefficients a are set (;, 1,2,3) of expression (l). The assignment of the initial values of the coefficients is performed on the signal at the link 64 (through the element 84), arriving at the control inputs of the co-element 88 of all the adaption channels 86. On this signal, the contents of registers 87, in which a stored sub-set of initial values of the coefficients a ;, are transmitted to the shift registers 89. The delayed signal from AND 84 / is delayed 101 and element 100) through the control inputs of elements 91 switching, through which the content of the shift registers 89 is transmitted in each channel 86 to the inputs of adders 97 modulo two and through OR elements 95 to registers 96, the contents of which are then transmitted to block 72. The signal from the output of delay element 101 after; stupid and on the starting. The input of the generator 98, the oscillation period. Which is selected in such a way that for the time between two adjacent pulses in AFP 5 it was possible to evaluate the set of coefficients obtained in block 71.

According to the signals of the decoder 45, block 2, through switches 6, sends to AFP 5 of all the processing channels, the arguments of the training points of the sequence, which are received via communication 82 to the inputs of the arguments of block 72. In each channel, block 72 by the values of the coefficients a and arguments X; , X according to the relation (1) calculates the value of V ;; , 1. output variable of a particular model at the i -th point. The calculated value of Y, -; , i is fed to the input of the discriminator 73, which sequentially calculates the criterion Y

S |.,; Klr

g is the number of points of the training sequence;

V; is the value of the function at the i point of the training sequence;

H; .- the function value calculated in block 72 at the i-th point; 1 | module symbol After discriminator 73 calculates criterion J, the signal from its output is fed to the input of the comparison circuit 74, to the other input that receives the signal from the register 76 output, and to the enabling input - the signal from the connection 68 connecting this input and the output of the OR element 47. The signal at the output of the element OR 47 comes from the output of the decoder 45 after issuing the last address for the points I train10

the specified accuracy of the models is in all channels, the decoder 5 generates an enable signal at the elend 41, and the signal from the output of the decoder 45 delayed by element 46, the element 41 starts the generator 4 The next cycle of the AFP adapter 5 starts. The delay time of element 46 is determined by the time for comparison, in the AFP 5, all channels of particular models obtained on this adaptation cycle with the best modules stored in registers 93, and in the registers 93 new best models

this sequence of ciphers / coefficients, if such

20

25

thirty

torus The same signal from the expander of the decoder 45 stops the oscillation of the generator 42, through the element 49 for the holds and the element OR 44 sets the counter 43 to its initial state, is fed to the input of the counter 48, which counts the number of adaptation cycles of the AFP 5. On the signal on its own. the enable input comparison circuit 74 compares the signals arriving at its inputs. If the value of the criterion calculated by discriminator 73 is less than the number recorded in register 76, then the output of the comparison circuit 74 is a signal that arrives at the input of element 75. Using this signal, a new criterion value is written to register 76 from the output of discriminator 73. The signal of the circuit 74, which enters the input of the block 71 35 control inputs of the switching elements 92), records the contents of the shift registers 89 into the registers 93. The values of the coefficients are stored, which are stored until a new set is found. coefficients, giving a smaller value of the criterion S. The contents of register 76 are compared in circuit 79, with the given, valid

an error. If the contents of register 76 is less than or equal to the permissible error, then the comparison circuit 78 excludes the signal to the input element AND 7 of its processing channel. The same signal through the element OR 70 is fed to the closing input of the block 71.

Counter 48 counts the number of adaptation cycles; AFP 5; So far they are doing. In this case, the generator 98 of the block 71 outputs a signal to the control input of the switching elements 90, except that the modulators of the adders 97 modulo two are fed to the shift registers 89. The new content of the shift registers 89 via the switching elements 9 controlled by the signal 98 through delay element 99 and element OR 100, enters the inputs of the sum of ditch 97 modulo two and through the element OR 95 to registers 96 and so on. This random process of searching for a particular model in each channel continues until idle generator 98 stop with exit and e ment HJDi 70 no signal, stopping the oscillation generator 98. This occurs when the contents of counter 48 previews a predetermined number of cycles of the adaptation AFP 5 or is a signal for de O AND gate 7 of the first channel. According to the state of the counter 48 or the presence of a signal at the output of the element And 7, the decoder 50 sends signals through the elements AND 85 and OR, 70 to the input of the setup in state 1 of all bits to 45 registers 76 (i.e. for recording; c. AFP 5 of extremely large numbers), signaling on switching elements 94 of blocks 71 of all free channels for transferring the coefficients of the best particular descriptions from registers 93 to registers 96, and then to blocks 72. Signal from the decoder signal 50 Cher delay element 52 enters the triggering input of the generator 53, they

40

50

 counter 48 does not exceed the set -55 pulses of which are fed to the input

number or until the output of the element And 7 of the first channel does not appear signal, indicating that

The specified accuracy of the 1GNT models in all channels, the decoder 50 outputs the enable signal to the element 41, and the signal from the output of the decoder 45 delayed by the element 46, through the element 41 starts the generator 42. The next adaptation cycle of the AFP 5 starts. It takes time to compare 5 channels of all channels obtained on this cycle of adaptation of private models with the best modules stored in registers 93, and h. registers to 93 new best models.

25

thirty

five

there are. In this case, the generator 98 of the block 71 outputs a signal to the control input of the switching elements 90, through which the modulators of the adders 97 modulo two are fed to the shift registers 89. The new contents of the shift registers 89 through the switching elements 91 controlled by the signal received from the generator 98 through delay element 99 and element OR 100, is fed to the inputs of adders 97 modulo two and through. OR elements 95 to registers 96 and so on. This process of randomly searching for the best private model in each channel continues until the generator stops at the input of the generator 98 from the output of the HJDi 70 element and stops oscillating the generator 98. This happens when the contents of the counter 48 exceed a specified number cycles of adaptation of the AFP 5 or the signal appears at the output of the element And 7 of the first channel. According to the state of the counter 48 or the presence of a signal at the output of the element And 7, the decoder 50 transmits the signals through the elements AND 85 and OR, 70 to the input of the installation in state 1 of all bits .. 5 registers 76 (i.e. for recording; AFP 5 of extremely large number), signaling on switching elements 94 of blocks 71 of all free channels for transferring the coefficients of the best particular descriptions from registers 93 to registers 96, and then to blocks 72. The signal from the decoder code 50 through the element 52 delays arrive at the trigger input of the generator 53, im0

0

counter 54. As long as the number in the counter 54 does not exceed the specified number of check sequence points

c evaluation mode of the obtained particular models at check points; sequences. The signal from the output of the decoder 57 stops the generator 5, 53, through the delay element 56 and the OR element 55, after a specified time, returns to the initial state with the flow sensor 54. The signal from the output of the decoder 57 enters through the element

The decoder 57 issues in, block 2 the addresses of points, the check sequence, the arguments of which are via switches 6, and the values of the functions directly from the output of block 2 are entered in AFP 5 of all channels. Block 72 on the set of coefficients a; , issued, block 71, and the value of the arguments, X | ((received by communication 82

from switches 6, by the ratio (1) 10 OR 16 to the installation inputs of the counters, calculate the values of private descriptors 13 (via the element OR 66), 19 and scientific research institutes on the points of the test sequence of the switch 15. Delayed elementality in each free channel , volume 59 signal from the output of the decoder In each canape, the calculated for 57 through the SHSh 9 element and the trigger 11 of each point of the test sequence - 15 starts the generator 12, pulses

which is fed to the input of the counter 13. Signals from the output of the decoder 14 are fed to the enabling inputs of the switch 15, which, in accordance with the value of g g jf, is fed to the input of the discriminator 73, to another input which comes from block 2. the function values in the corresponding

the points of the check sequence are 20 times with the number in the counter

ti. In each channel, the discriminator sequentially calculates the criterion

8 ,. | ./У,-Ч,е., „/,,

where o is the number of check points

sequences; UK -, the value of the function in tt-oh

the check sequence point;

X i; i - calculated in block 72 is sbiKm.,

the function at the kth point;

E, FU are the numbers of the arguments used in the selected channel.

After the discriminators 73 calculate the criteria 8, the signals from their outputs go to the inputs of the comparison circuit 74, the other inputs of the chips receive the maximum possible signals from the registers 76 on the first selection row. The circuit 74 performs the comparison of two signals only if there is a cadio control signal from the output of the decoder 57 (through the OR element 47 and the connection 68), which appears only in the case when the number in the counter 54 becomes equal to the maximum specified (determined by the number of points of the check sequence ). If there is a control signal on the first selection row, the circuit 74 outputs the switching elements 92 and the control inputs of the elements 75. Through these elements, the values of the criterion S are written to the registers 76 from the outputs of the discriminators 73. This actually ends

c evaluation mode of the obtained particular models at check points; sequences. The signal from the output of the decoder 57 stops the generator 5, 53, through the delay element 56 and the OR element 55, after a specified time, returns to the initial state with the flow sensor 54. The signal from the output of the decoder 57 enters through the element

0

five

0

13. through a switch to the first input of the comparison circuit 17 a predetermined processing channel. In the first row of selection, the first pulse of the generator 12, the counter 13 5 through the decoder 14, outlines the signal to connect to the first input of the first channel comparison circuit 17. In this case, the circuit 17 compares the output of the first and (t + 1) -th channels 4. If the signal at the first input of the circuit 17. Since the comparison is greater than the signal at the second input, then no signal appears at the output of the circuit 17. After that, the generator 12 generates a second pulse to the counter 13 and the switch 15 according to the signals of the decoder 14 connects the second channel. This process is repeated until the switch 15 connects a channel to the circuit 17, the signal at the output of which is equal to the signal at the output (in + l) -ro of the channel. If there are two identical signals at the inputs, the circuit 17 generates a signal to stop the generator 12. (via the element OR 10 and the AND trigger) and the signal to the inputs of the elements 22. The signals from counter 13 through the elements 22 enter the decoder 23, which outputs a signal to the trigger 27 corresponding to the found channel whose number is stored in the counter

13. The specified trigger 27, with its signal as a logical unit in block 3, selection and blocking this channel with a signal as a logical zero on 5 inputs of the AND 84 and AND 85 elements of the selected channel j. The signal from the output of the decoder 23 through the element OR 21 is fed to the counter

0

25

19 / KOTOpbrti counts the number of blocked channels in the current selection row.), Through delay element 20 and element OR 56 at the installation input of counter 13, starting (through element OR 9 and trigger 1 |) generator 12. While the number of blocked channels is less than the specified, decoder

18 does not signal, and similarly to the indicated, other best processing channels are selected, but as soon as this number becomes equal to the specified one, the signal from the output of the I8 decoder through the OR 10 element goes to the zero input of trigger 1G and prevents the generator 12 from starting

the output of the delay element 20 through the element OR 9 and the trigger 11. In addition

Therefore, the signal from the decoder 18 code goes to the inputs of the elements OR 28 and through them to the inputs of the And 29 elements. If the inputs of the And 29 elements receive single signals from the flip-flops 27, then from the outputs of the And 29 elements the signals go to the decoders 31. Signals From the outputs of the decoder 31, they are fed to the inputs of the switches 6 of all the channels that perform the re-switching for the next row of selections. Delayed by the element 32, the signal from the output of the decoder 18 through

the OR 3 element translates the trigger 35 into a single state, the signal from the top of the trigger 35 enters the AFP 5 of all unlocked channels and starts the adaptation mode of the AFP 5 on the points of the training sequence in the next row of selection. The signal from the output of the element OR 21 is fed not only to the input of the counter 19, but to the input of the counter 24 through the element

20 delays) which will add up to the total number of channels occupied. As soon as the counter code 20 shows that all channels are busy, the signal from the output of the decoder 25 through the elements OR 67

arrives at the zero inputs of the triggers 27. The same signal from the output of the decoder 25 through the element OR 16 switches the control unit 1 to the selection mode of the best processing channel. In this case, the signal from the output of the element first. OR 16 sets the counter 13 and the switch 15 to the zero state, and hence the signal from the output of the delay element 59 through the SHSh 9 element and the trigger P starts the generator 12 and starts

40

45

50

55

Finding the channel in which the best model is found. As soon as such a channel is defined, a signal appears at one of the outputs of the decoder 23, which through the element OR 21 enters the input of the element AND 26, the signal from the output of the element AND 26 through the element OR 10 and the trigger II stops the generator 12, and in the counter 13 remains channel number with the best model received. . . .

20

25

35

F o

of b. r. e and

15

thirty

40

five

0

five

pm lla

.

1. A multichannel model identification device containing a control unit, the start input of which is the device start input, a memory block and m processing channels, each of which includes a minimum signal selection block, an adaptive function converter and a switch, the processing channels from first to (t-1) -and-include element I, which is the enable input of the minimum signal selection unit of each processing channel, is connected to the corresponding permit output of the control unit, and the output is connected to the corresponding to the commutating input of the control unit, the first informational input of the minimum signal selection unit of each processing channel is connected to the model evaluation output of the adaptive functional converter, the output of the minimum signal selection unit of each previous channel 1C), starting from the first (t -1) - is connected to the second information input of the selection block of the maximum signal of the subsequent processing channel; the second information input of the selection block of the minimum signal of the first processing channel is connected to the output house start channel control unit,

the first output of the switch of each processing channel is connected to the input

the arguments of the adaptive function converter, the output of the function of which is connected to the first information input of the switch, the second information input of the switch of the first processing channel is connected to the output of the arguments of the memory block, the output of the function values of which is connected to the fugation value of the adaptive functional converter; .

.131

permissive input of which is connected by the corresponding permissive output of the control unit, permissive switch input of each channel is connected to the control enable switching output of the control unit, coefficients recording resolution outputs, connection resolution and output of a specified number of cycles of which are connected to the first, second and third control inputs, respectively adaptive functional converter of each processing channel, the output of which is configured from the first to (t − 1) -th processing channels is connected to the first in one element of the And element, the second input of the element And the first through (t-2) -th processing channel is connected to the output of the element And the subsequent processing channel, the second input of the element And (t-1) th processing channel is connected to the output of the end of the adaptive functional converter t of the th processing channel, the output of the element I of the first processing channel is connected to the input of the end of the control unit settings, address and resolution. the memory block inputs are connected respectively to the address output and to the output of the output of the control unit, the second switch output of each previous processing channel is connected to the second information input of the subsequent processing channel, the third output of which is connected to the third information input of the previous processing channel, different that, in order to increase accuracy by using information about the approximate object model, it introduced (t + 1) -th processing channel, including; The th converter and the minimum signal selection block, which allows the input and output of which are connected respectively to the () permitting output and (t + 1) -th switching input of the control unit, the first information input of the minimum signal selection block

The processing channel (t + 1) of the processing channel is medium with the output of model evaluation of the functional P1zoobrazovatel, the second information input of the minimum signal selection unit (t + 1) of the processing channel is connected to the output of the minimum signal selection unit of the processing channel i, output value 0014.

The SRI of the function converter function is connected to the first information input of the switch (m + l) -th processing channel, the control inputs of the function converter are connected respectively to the coefficients resolution enable, connection resolution outputs and the output of a specified number of control unit cycles, allowing the switch input ( T-I) of the channel channel & oki connected; with the output of the switching resolution of the control unit, the first output is connected to the input of the arguments of the function converter, the second output and the second information input are connected respectively to the third information input and to the second output of the u switch of the processing channel.

2. The device according to claim 1, characterized in that the control unit contains a switch, counters, triggers, decoders, generators of rectangular pulses, groups of triggers, groups of elements AND, groups of elements OR, switching element delay elements, elements AND, the comparison circuit, the OR elements, the output of the first of which is connected to the single input of the first trigger, the zero input of which is connected to the output of the second OR element, the start input of the first generator of rectangular pulses is connected to the single output of the first trigger and connecting the control unit, the output of the first generator of rectangular pulses is connected to the counting input of the first counter, the outputs of which bits are connected respectively to the first inputs of elements AND of the first group and to the inputs of the first decoder, the outputs of which are connected respectively to the address inputs of the switch; connected to the output of the third SHS element, the input of the first delay element is connected to the output of the fourth OR element and to the counting input of the second counter, the second inputs of the AND elements of the first group, and the first input of the second element OR is connected to the output of the comparison circuit, the outputs of the elements AND of the first group are connected respectively to the inputs of the second decoder, the outputs of the bits of the third counter are connected

1.5.

respectively, with inputs of the third decoder, the output of which is connected to the first input of the third OR element and to the first input of the AND element, the second input of which is connected to the output of the fourth OR element, and the output is connected to the second input of the second OR element, the single inputs of the first group of triggers are connected with the outputs of the second decoder, the outputs of the elements OR of the first group are connected respectively to the first inputs of the elements AND of the second group, the second inputs of which and the enabling outputs of the control unit are connected respectively with the outputs of the triggers of the first group, the outputs of the elements of the second group are connected respectively to the single inputs of the triggers of the second group and to the infor. the fourth decryptor's output inputs, the output of which is the output of the switching resolution of the control unit, the input of the second delay element, the third input of the second OR element, and the first inputs of the OR elements of the first group are connected to the output of the fifth decoder; the outputs of the second and third delay elements are connected respectively to the first and the second inputs of the fifth OR element, the output of which is connected to the single input of the second trigger, the zero input of which is connected to the output of the sixth OR element, the start input of the com control block nen fourth deshift Rhatore and counter mounting inputs, with zero inputs of flip-flops of the second group to the fourth input of the second OR gate, a first input of a sixth OR gate, the inputs of the third and fourth delay elements of the second flip-flop output coupled to the output; permitting the recording of the coefficients of the control unit and through the fifth delay element is connected to the first input of the seventh OR element, the second input of which is connected to the output of the fourth delay element, the third input is connected to the output of the switching element, and the transducer is connected to the starting input of the second generator square pulse , the output of which is connected to the counting input of the fourth counter, the setup input of which is connected to the output of the eighth element SH, the first input of which

It

15

20

25

5 0 5

23810016

connected to the start input of the control unit; the outputs of the bits of the fourth counter are connected respectively to the inputs of the sixth decoder, the output of which is connected to the enable output of the control unit, to the stop input of the second square-wave pulse generator; the first input of the ninth OR element, with the counting input of the fifth counter and the input of the seventh delay element, the output of which is connected to the second input of the eighth OR element, the output of the sixth delay element is connected to the information an input switching element, enabling input coupled to an output of the seventh decoder, data inputs of which are connected respectively to the outputs of n bits of the counter, and a clock input connected. to the end of the setup of the control unit; the output of the seventh decoder is connected to the second input of the sixth OR element, to the input of the eighth delay element and to the output of a specified number of cycles of the control unit; the setup input of the fifth counter is connected to the second trigger trigger; start the third generator of rectangular impulses, the output of which is connected to the counting input of the sixth counter, the installation input of which is connected to the output of the tenth element OR, the first input of which is soy The output of the ninth delay element is dinin, the second input is connected to the start input 40 of the control unit, the bits of the sixth counter are connected to the inputs of the eighth decoder, the output of which is connected to the address output of the control unit, to the third element. that OR, with 1Input of the 9th delay element, with the third stop input; the generator of rectangular pulses and with the second input of the ninth element SH, the output of which is; the enable output of the control unit, the output of the third OR element through the tenth delay element is connected to the first input of the first CMM element, the second input of which is connected to the output 1 of the first delay element, the switching input from the first to (m-t-1) th control loop

thirty

35

five

Connected respectively with the enable inputs of the switch, the output of which is connected to the first input of the comparison circuit, the second input of which is connected to the (ha + 1) -th switching input of the control unit, the installation input of the first counter connected to the output of the eleventh element OR, the first input of which is connected to . the output of the third OR element and the installation input of the second counter, the second input is connected to the output of the first delay element and to the counting input of the third counter, zero inputs of the first group triggers are connected respectively to the outputs of the OR elements of the second group, the first inputs of which are connected to the start input of the block control, the second inputs are connected to the output of the third decoder, the inputs of the fourth element OR are connected respectively to the outputs of the second decoder, the outputs of the bits of the second counter are connected respectively about with the inputs of that descrambler, the codes of the second trigger

the groups are connected respectively with the second inputs of the elements. OR of the first group,.

3. Device according to claim 1, that the adaptive functional converter contains the elements AND OR, comparison circuits, register, discriminator, coefficient setting unit, and function value calculator, the inputs of which are connected respectively to the input of the converter arguments and the output of the block coefficients, and the input is connected to the first input of the discriminator and to the output of the converter function values, the output of the discriminator is connected to the first information input of the first comparison circuit and to the information input of the element to ommutation, permitting the 5th input of which is connected to the output of the first comparison circuit, and the code is connected to the information input of the register, the setup input of which is connected to the output of the first element

0 OR, whose first input is connected to the output of the second OR element, the register output is connected to the second information input of the first comparison circuit, to the first information input

5 with the input of the second comparison circuit and with the output of the transmitter: model of the converter, the output of the second comparison circuit is connected with the code of the end of the converter tuning and with the first

0 the input of the second element OR, the second input of the discriminator is the input of the values of the functions of the converter, the first, second and third equalizing inputs of the converter are connected

5, respectively, with the first input of the first element I, with the enabling input of the first comparison circuit and with the first input of the second element I, whose output is connected to the second input

0 of the second element OR, the second input of the first element OR. connected to the output of the first And element, the inputs of the coefficient setting unit are connected respectively to the outputs of the first and second elements of the second OR element and the first comparison circuit, the second inputs of the first and second And elements are connected to the resolver input of the converter, the second in0; The input is the value of the allowable error of the converter.

five

-It

69

fig 2

tfJ

7s

85

- S-f 7G

t Ж1ч / ч уi

72

R

74

79

78

eight

V

80 a08

M

(rigz

 R

L.-

Editor S. Lisin

Compiled by A. Zherenov

Tehred N. Bonkalo Proofreader E. Sirohman

Order 3294/51 Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

Claims (3)

Claim 1. A multichannel device for identifying models containing a control unit, the start-up input of which is the start-up input of the device, a memory unit and u processing channels ^ each of which includes a minimum signal selection unit, an adaptive functional converter and a switch, processing channels from first to (m -Ι) -th include the element AND, Moreover, the enable input of the selection block of the minimum signal of each processing channel is connected to the corresponding enable output of the control unit, and the output is connected to the corresponding com using the control unit input, the first information input of the minimum signal selection block of each processing channel is connected to the evaluation output of the adaptive functional converter model, the output of the minimum signal selection block of each previous processing channel, starting from the first through (u-1) -th, is connected to the second information the input of the selection block of the minimum signal of the subsequent processing channel, the second information input of the selection block of the minimum signal of the first processing channel is connected to the output launch and of the control unit channels, the first output of the switch of each processing channel is connected to the argument input of the adaptive functional converter, the function output of which is connected to the first information input of the switch, the second information input of the switch of the first processing channel is connected to the argument output of the memory block, the output of the function values of which is connected to the input values of the functions of the adaptive functional converter of each processing channel ^ 13 ^ 1238, the enable input of which is connected by the corresponding enable output of the control unit, the enable input of the switch of each channel is connected to the output of the enable resolution of the control unit 5, the output enable resolution of the coefficients, enable connection and the output of a given number of cycles which are connected respectively to the first, second and third To the control inputs of the adaptive functional converter of each processing channel, the output of the end of which is configured from the first to (u-1) -th processing channels is connected to 15 the first input of the And element, the second input of the And element from the first through (w-2) -th processing channel is connected to the output of the And element of the subsequent processing channel. the second input of the And (t-1) element of the 20th processing channel is connected to the output of the end of tuning adaptive functional converter of the 1st processing channel, the output of the And element of the first processing channel is connected to it with the input of the end of tuning of the control unit, address and resolution. melting inputs of the memory block. Connected respectively with the address output and with the output enable output of the control unit ₃ θ, the second output of the switch of each previous processing channel is connected to the second information input of the subsequent processing channel, the third output of which is connected to the third information input of the previous processing channel, in that, to improve accuracy by the use of information about the approximate MO, Delhi object ^- it entered (m + 1) -th processing channel comprising a switch funktsion the first converter and the minimum signal selection block, which permits input and output 45 of which are connected respectively to the (t + 1) -th enable output and (w + 1) -th switching input of the control unit, the first information input of the minimum signal-jq selection block ( t + 1) of the processing channel is connected to the evaluation output of the functional converter model, the second information input of the minimum signal selection block (t + 1) of the 55 processing channel is connected to the output of the minimum signal selection block of the GP processing channel, the output is 00 14th functions of the functional converter is connected to the first information input of the switch (πι + Ι) of the th processing channel, the control inputs of the functional converter are connected to respectively. with the steps of resolving the recording of coefficients, resolving the connection and the output of a given number of cycles of the control unit, the enable input of the switch of the (tn + Ι) processing channel is connected to the output of the enable resolution of the control unit, the first output is connected to the input of the arguments of the functional converter, the second output and the second information the input is connected respectively to the third information input and to the second output of the switch of the th processing channel. 2. The device according to claim 1, distinguishing with. I mean that, the control unit contains a switch, counters, triggers, decoders, rectangular pulse generators, trigger groups, AND element groups, OR element groups, switching element, delay elements, AND elements, comparison circuit, OR elements, the first which is connected to the single input of the first trigger, the zero input of which is connected to the output of the second OR element, the start input of the first rectangular pulse generator is connected to the single output of the first trigger and to the output of the control unit channels, in the output of the first rectangular pulse generator is connected to the counting ^; the input of the first counter, the outputs of the discharges of which are connected respectively to the first inputs of the AND elements of the first group and to the inputs of the first decoder, the outputs of which are connected respectively to the address inputs of the switch, the installation input of which is connected to the output of the third OR element, the input of the first delay element is connected to the output of the fourth element OR and with the counting input of the second counter, the second inputs of the elements' And the first group, the first input of the second element OR are connected to the output of the comparison circuit, the outputs of the elements AND the first the first group are connected respectively to inputs of the second decoder, outputs the third bits of the counter are connected 1238100 16 is connected to the start input of the control unit, the outputs of the fourth counter bits are connected respectively to the inputs of the sixth decoder, the output of which is connected to the output of the control unit output enable, to the stop input of the second rectangular pulse generator, with the input of the sixth delay element, with 10 the input of the ninth OR element, 'with the counting input of the fifth counter and the input of the seventh delay element, the output of which is connected to the second, input <the eighth OR element, output; of the sixth delay element is connected to the information input of the switching element, the enabling input of which is connected to the output of the seventh decoder, the information inputs of which are connected respectively to the outputs of the digits of the fifth counter, and the clock input is connected. to the input of the end of tuning the control unit, / the output of the seventh decoder is connected to the second 'input of the sixth OR element, with the input of the eighth delay element' and with the output of the specified number of cycles of the control unit, the installation input of the fifth counter is connected to the output of the second trigger, the output of the eighth delay element is connected with the start input of the third rectangular pulse generator, the output of which is connected to the counting input of the sixth counter, the installation input of which is connected to the output of the tenth OR element, the first input of which is Inonii yield ninth delay element, a second input connected to the input of 'start control unit, the outputs of the sixth counter bits are connected respectively to the inputs of the eighth decoder whose output is connected to the address output unit upravle45 Nia with vtorm input of the third elements. “That OR, with the input of the ninth delay element, with the stop input of the third rectangular pulse generator and with the second input of the ninth ele! OR, the output of which is the output of the permission to connect the control unit, the output of the third OR element through the tenth delay element is connected to the first input of the first 55 15, respectively, with the inputs of the third decoder, the output of which is connected to the first input of the third OR element and the first input of the AND element, the second input of which is connected to the output _{5 of} the fourth OR element, and the output is connected to the second input of the second OR element, unit inputs of the triggers of the first the groups are connected respectively to the outputs of the second decoder, the outputs of the OR elements of the first group are connected respectively to the first inputs of the elements AND of the second group, the second inputs of which and the enabling outputs of the control unit are connected respectively etstvenno flops to the outputs of the first group of elements and outputs connected respectively to the second group with single-input flip-flops' of the second group and with Infor-. by the input inputs of the fourth decoder, the output of which is the switching permission permission of the control unit, the input of the second delay element, the third input of the second OR element and the first inputs of the OR elements of the first group are connected to the output of the fifth decoder, the outputs of the second and third delay elements are connected respectively to the first and second inputs fifth element OR, the output of which is connected to a single ·. the input of the second trigger, the zero input of which is connected to the output of the sixth OR element, the start input of the control unit is connected to the installation inputs of the fourth decoder and the third counter, with zero inputs of the triggers of the second group, with the fourth input of the second OR element, with the first input of the sixth OR element, with the inputs of the third and fourth delay elements, the output of the second trigger is connected to the output of the recording resolution of the coefficients of the control unit and through the fifth delay element is connected to the first input of the seventh OR element, the second input of which is connected to the output of the fourth delay element, the third 50 input is connected to the output of the switching element, and the output is connected to the start input of the second rectangular pulse generator, the output of which is connected to the counting input of the fourth counter, the installation input of which is connected to the output of the eighth OR element, the first whose input is an OR element, the second input of which is connected to the output of the first delay element, switching inputs from the first to (w + 1) -th control unit 17 1238100 are connected respectively with the enabling inputs of the switch, the output of which is connected to the first input of the comparison circuit, the second input of which is connected to the (t + 1) -th switching input of the control unit, the installation input of the first counter is connected to the output of the eleventh OR element, the first input of which connected to. the output of the third OR element and with 10 installation input of the second counter, the second input is connected to the output of the first delay element and to the counting input of the third counter, the zero inputs of the triggers of the first group 15 are connected respectively to the outputs of the OR elements of the second group, the first inputs of which are connected to the start input control unit, the second inputs are connected to the output of the third 20 decoder, the inputs of the fourth element OR are connected respectively to the outputs of the second decoder, the outputs of the discharges of the second counter are connected respectively about with the inputs of the fifth 25 decoder, the outputs of the triggers of the second group are connected respectively to the second inputs of the elements OR of the first group. 3. Ustroystvo.po claim 1 of m and l - 30 sistent in that the converter comprises an adaptive functional elements of AND, OR, comparison circuit register discriminator coefficient block assignment, and block ₃₅ singing calculated values of the functions, the inputs of which are connected respectively with the input transducer and arguments coefficients _h output setting unit, and an output connected to the first input of the discriminator and the output values of the converter functions, you move the discriminator is connected to. the first information input of the first comparison circuit and with the information input of the switching element, the permitting input of which is connected to the output of the first comparison circuit, and the output is connected to the information input of the register, the installation input of which is connected to the output of the first OR element, - the first input of which is connected to the output of the second OR element, the output of the register is connected to the second information input of the first comparison circuit, with the first information input of the second comparison circuit and with the evaluation output of the converter model, the output is a swarm of the comparison circuit is connected to the output of the end of the converter settings and with the first input of the second OR element, the second input of the discriminator is the input of the values of the converter functions, the first, second and third control inputs of the converter are connected respectively to the first input of the first AND element, with the enable input of the first comparison circuit and with the first input of the second AND element, the output of which is connected to the second input of the second OR element, the second input of the first OR element is connected with the output of the first AND element, inputs of the block Denmark coefficients are respectively connected to the outputs of the first and second AND gates, a second OR gate and the first comparison circuit, the first and second inputs of AND gates connected vtdrogo permissive inverter input, the second information 'input of the second comparison circuit is input to the inverter allowable error value.