SU1238081A1 - Device for checking digital sequences - Google Patents

Abstract

The invention relates to the field of computing and can be used for con, trol discrete signals. The aim of the invention is to simplify the device. A distinctive feature of the proposed device is the combination of control and accumulation of information in one shift register. The device allows you to block the flow of information when the information depth is larger than the length of the register. In addition, the proposed device allows the monitored sequences to be displayed in step mode. The goal is achieved by introducing a trigger and a single pulse generator. 1 PC..

Description

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The invention relates to electrical measuring technology and can be used to control discrete signals in input-output channels of digital computing machines.

The aim of the invention is to simplify the device.

The drawing shows a block diagram of the device.

The device contains shift registers 1, trigger 2, element 3, single pulse generator 4, indication unit 5, switch 6, group of 7 inputs of monitored sequences, generator start and single pulse input 8, device mode switching input 9, device clock input 10, input 11 of the initial installation of the device.

The device works as follows

At the beginning of work, input 11 of the initial installation of the device, the reset input of the first bit of the I -th shift register, and the inputs of the installation of one digit of bits from the second to the m-th and the n-th digit of the shift register pass a short pulse to to which the P-register is set to the state About J 1,..., t.

The same impulse sets trigger 2 to one state. Therefore, trigger 2 permits the passage of clock pulses on

clock input 10 through the element FROM, the sync pulses are fed to the sync inputs of the shift registers 1. By clock sync to 1 shift registers. Logical values are recorded for signals coming from a group of 7 device inputs. Element And 3 skips the sync pulses until

the shift registers 1 are completely not filled with controlled sequences. At this point in time, the zero level previously recorded in the first bit of the h th shift register enters trigger 2, the zero signal from the output of trigger 2 enters the input of the IZ element, prohibiting thereby passing the clock pulses to the sync inputs of the shift registers 1. The recording of information in registers 1 is stopped and stored in them.

controllable sequence information.

The display of the information stored in register 1 is performed in block 5

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indication in step-by-step mode with the help of single-pulse generator 4 pulses, arriving in read-out mode, to the clock inputs of the pulse output generator 4 sic registers through switch 6, which is controlled by device mode switching input 9.

The device allows for the length of the input sequence coming to a group of 7 device inputs, more than the length of the shift registers 1, to eliminate information loss. This is achieved by the fact that after filling the AND-th shift register 1, the zero level appearing at the output of flip-flop 2 is fed to the input of the AND 3 element, thereby prohibiting the passage of clock pulses to the sync inputs of the shift registers 1. The recording of information in registers 1 is stopped, and information from controlled sequences is stored in them.

Thus, the P-i shift register 1 performs the function of storing (storing) information received at the input of the controlled sequence, and also controls the depth of analysis, i.e. sets the number of clock cycles 30 of the tested sequence.

When displaying information of shift registers 1 after recording information in them, switch 6 on the device mode switching input 9 connects the output of the generator 4 to a single

pulse to register 1 I clock

shear. This allows you to analyze

the controlled sequences are coherent when the signal is received at the input 8 of the start of a single pulse generator or manually with a frequency determined by the operator. This allows sequentially viewing the bits of the monitored sequences in the display unit 5 ,.

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Claims (1)

Invention Formula 9. A device for monitoring c phraous sequences, containing n shift registers (where h is the number of monitored sequences), an indicating unit, an And element, a switch, the groups of inputs of monitored device sequences being connected respectively to the information inputs of the shift registers, a clock input of the device connected to the first input of the element I and I, so that, in order to simplify the device, a trigger and a generator of a single pulse are entered into it, with the outputs of the last bits from the first to (ft – 1) -th shift registers being connected respectively from the first to (n - 1) -th inputs of the display unit, the output of the last bit of the AND -th shift register is connected to the hM input of the display unit and to the information input of the trigger, the sync input of which is connected to the synchronous inputs of the shift registers and to the switch output whose control input is a switch input eni device mode, start-up input380814 A single impedance ra- tor of the device is connected to the control input of a single pulse generator, the input of which is connected to the first information input of the switch, the second information input of which is connected to the output of the element I, the reset input of the first bit of the AND -th shift register. ha is connected to the installation inputs of 10 unit bits from the second to in (and where m is the number of bits in the controlled sequence) of the YI th shift register, with a single trigger input and is the initial input f5 device installation, and the trigger output is connected to the second input element: that, And P Oje-j 1LJLl  s with Jf Editor M. Tsitkina Compiled by N.Toropova Tehred L. Serdyukova Proofreader V. But ha 3293/50 Circulation 671. Subscription VNIIPI State 1 USSR Committee for inventions and discoveries .113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4