SU1238077A1 - Device for generating variable modulo remainder of number - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices. The aim of the invention is to increase the reliability of the formation. The device contains five elements, OR elements, seven pulse shapers, six counters, an EXCLUSIVE OR element, a multiplication unit, an AND element, a group of modulo-two adders, and a multiplication unit. The code of the number Cd and the selected module M are set. The code of the number C is continuously fed to the information inputs of the counter during the time of the for- ming time. The module code is assigned to a group of adders. The device implements the known phasing aj (- j + Cd (py4M), where 9, Co - O, K - 1; j 1, M - T, Multiplication unit is used to calculate the characters of the code sequence. 2 Il w.ro 00 about

Description

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The invention relates to computing technology and can be used in digital computing devices.

The purpose of the invention is to increase the reliability of the form.

FIG. 1 shows a block diagram of the device; in FIG. 2, the same multiplier.

The device contains (Fig. 1) a bus to 1 setting the module code, the element OR 2, the pulse shapers 3 and A, the counters 5 and 6, the elements OR 7 and 8, the element 9 .. EXCLUSIVE OR, the elements OR 10 and 11 , meter 12, generator is 12 pulses, element OR 14, counter 15, multiplication unit T6, counters 17 and 18, element 19, generator 20 clock pulses, element OR 21, pulse formers 22-24, element OR 20 - EI 25, group 26 summa--. ditch two counters 27, a number code bus 28, start input 29, device forming end output 30, device outputs 31, element

OR 32,

The multiplication unit (Fig. 2) contains a pulse shaper 33, an element OR-NOT 34, an element OR 35, a group, 36 modulo-two adders, a shaper 37 a pulse, an element AND 38, counters i 39 and 40,

 In the initial state, the counters are 5,6, 12,15,17,18,27 Hfig. 1) and the counters 40 and 39 (Fig. 2) are cleared, the counters 5,6,1B, 40 being subtractive, and the counters 12,15., 17,27. and 39 - summarizing. The generator 20 clock pulses produces at its output a sequence of clock pulses.

Before starting work on the bus 28, specifying the code of the number is given a code C, which during the generation time affects the pre-recording inputs of the counter 17. The module code M is also set. On bus 1, it acts on the inputs cy Iatopo

group 26 and to the pre-recording inputs of counters 5 and 6,

The device implements the expression

3 (9) j + Cg (mod М),,

thirty

35

40

45

50

where Cd O, M-1, j 1; M-1, (1)

The pulse from the input 29 of the start of the device starts the device into operation. This pulse, the passage through the element OR 2, affects the resolution input of the counter 5, resulting in

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counter 5 will record the Modul M code acting on the information inputs; I’ll influence the resolution inputs of the counter 6 and through the OR element 32 on the resolution input to the counter 27, write the module code M and the code into these counters

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the numbers Cp are correspondingly; I will affect the first input of the element OR 11 and the passage to its output, will go to the counting input of the counter 15.

On a slice of the start-up pulse, feeding. 4 impulses, input to the imaging unit, 4 a pulse is formed at the output of the latter, which a passage to the inputs of the 13th ШШ 7 and 8 elements goes to their outputs, and then to the subtractive inputs of counters 5 and 6, respectively, subtract a unit from these counters; pass to the first input of the element OR 10, enter the counter resolution input .18, pre-record in it the code of the GO number recorded in the counter 17. The multiplication unit 16 does not participate in the calculation of the first character of the code sequence, since the value of the element is cm , (1), determined by the state of counter 12, is numerically equal. zero

After the code sequence of the CQ number is zacisana in the counter 18, the output element is. And OR 21 a unit potential is maintained, which will be maintained until the counter 18 clears. On the front of this potential, the shaper 22 pulses will form W 1pulse, which will reset the counter 27.-This. a unit potential from the output of the element OR 21 will open the element AND 19. and the clock pulses affecting its other output. The input goes to the subtracting input of the counter 18 and to the synchronizing input of the counter 27. The last performs the summation of the incoming input the number of clock pulses. Summation is carried out until a binary number is formed at the outputs of the counter 27, a number equal to the selected module M and acting on the first inputs of the group 26 modulo-two adders performing the equivalence operation. The second inputs of these adders are affected by the binary code of the selected module M. As a result, two groups 26 will have zero potentials at the output of each adder, which will affect the inputs of the OR-NOT element 25. At the output of the latter, a single potential is formed that through the driver 24 the pulses will reset the counter 27, and the counting of clock pulses will start anew, i.e. On the first inputs of modulo adders two groups 26 will be affected in parallel code by binary codes of numbers from 1 to M. During this time at least one of the outputs the sum of the tori of group 26 will be a single potential. Therefore, at the output of the element OR NOT 25 there will be zero potential. As soon as the counter 27 counts the number of clock pulses equal to the selected module M, it will be reset again. Such an operation will occur until the counter 18 is reset. And the latter will be reset by V.TOM. If the number of clock pulses received at its second input is numerically equal to the number recorded in the counter .18. As a result, a zero potential occurs at the output of the OR 21 element, the AND 19 element closes and the clock pulses no longer arrive at the inputs of the counters 18 and 27, Therefore, at the outputs of counter 27, the remainder of the number recorded in counter 1-8 modulo M. will remain. From the cut of the pulse produced at the output of the OR 21 element, the driver of the pulses will form a pulse that will go to the input of the OR element 32 and beyond proh d, enter the counter 17 into the input, write to the last code C, to the counting input of counter 12 and through the element OR 7 to the subtractive input of counter 5, add and subtract from the content, these counters one, respectively, the passage through the element OR EXCLUSIVE 9 will go to the input of the imager 13 pulses to

The cutoff of this pulse will form a pulse arriving through the element OR 14 at the input of the discharge of the multiplication unit 16, thereby including the latter into operation.

The multiplier 16 operates as follows (FIG. 2).

The controlling input-pulse, which has arrived at its input, passes to the controlling input of the meter 40, thus recording in it the code of the number of multiplicand. As a result, the code of the same number is formed at the output of this counter, and since the outputs of counter 40 are connected to

s to f5 20 25

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the inputs of the element OR 35, then at the output of the latter a single potential appears, which will be maintained until the counter 40 is in the zero state. A single potential from the output of the element OR 35 opens the element And 38, the second input of which receives the clock pulses. As a result, clock pulses arrive at the counting input of counter 39 and are counted by it. As soon as the number of clock pulses, counted by counter 39, is equal to the number code affecting the first inputs of modulo 36 cell 36 moduliB (multiplier), a single potential is formed at the output of the OR-NO 34 element, the front of which pulse generator 33 will generate a pulse that will to the subtracting input of the counter 40, and also to zero the counter 39. As soon as the subtracting input of the counter 40 receives the number of pulses, numerically equal to the code of the number written in it, it is reset, on: the output of the OR element 35 is formed The evo potential and clock pulses will not pass to the output of the AND 38 element. The number of clock pulses received from the output of the AND 38 element to the counting input of counter 39, as well as to the output of the block, will be numerically equal to the product of the numbers affecting the first and second inputs of the block 16 multiply. A slice of a single impulse on the extr-code of the element OR 35, the pulse shaper 37 impulses the impulse. End of multiplication.

The number of pulses received at the output of the multiplication unit 16 is counted by a counter 17, in which the code of the number Co is pre-recorded. Impulse The end of the multiplication from the output of the pulse generator of the 37 pulses of the multiplication unit 16, the passage through the element OR 10, will go to the input of the resolution of the counter 18, write into it the code of the number of the counter 17, and then begin-. The process of calculating the remainder modulo M from that number, which was described above. After the next character of the code sequence has been generated, the shaper 23 carries the next pulse. At the outputs of the counter 12, under the influence of pulses from the outputs of the former 23, codes from O to M-1 will be generated sequentially. After the M-1 code has been formed, under the influence of the next pulse from the output of the imaging unit 23, the counter 5 will be reset, resulting in a transfer at its output through which the impulse 12 will reset the input pulse of the EXCLUSIVE OR 9 to its output the output, the passage through the element OR 11, is counted by the counter 15, and the passage through the element OR 8, is subtracted from the counter 6, is fed to the input of the imaging unit 3 pulses Sov.

Shaper 3 will form a pulse, which is transmitted through its input pulse, which, passing through the element OR 14, enters the resolution input of the multiplication unit 16, thus turning it on into operation, as well as passing to the input of the element OR 2, arrives at the resolution enable input, setting it in a preliminary state, numerically equal to the code of the number M acting on the inputs from bus 1. This same pulse, passing through the element OR 7 will subtract 5 1 from the counter, as a result of which counter 5 will be recorded numbers M-1,

At the same time, the counter 15, with the arrival of the next pulse on its counting input, will issue a code 1 to its outputs. M-1. After the counter 15 is set to the M-1 state, and the counter 6 is in the zero state, then Under the influence of the next impulse arriving at the corresponding inputs of these counters from the transfer output of counter 5 through the elements OR 8 and 11, a transfer is formed at the transfer output of counter 6, which flushes counters 13 and 1.7, and also forms the end of formation signal, witnessing that the process of forming signals has ended on the selected module M and the code of the number Cd.

Invention Formula

A device for forming a remainder in an arbitrary module of a number containing the first and second counters, the AND element, the first OR element, the OR OR NOT element, a group of modulo-two adders, the first and second pulse generator, and the clock generator, clock generator connected to the first

o

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The input of the AND element, the output of which is connected to the subtractive input of the first counter and the counting input of the second counter, the second input of the AND element connected to the first {OR element and the input of the first pulse generator, the output of which is connected to the reset input of the second counter, the output of the second imager pulses connected to the reset input of the second counter, the input of the second pulse generator is connected to the output of the element OR NOT, the inputs of which are connected to the output of modulators two groups, the first inputs of which are connected to The respective outputs of the second counter, which are the outputs of the device, the inputs of the first element OR are connected to the outputs of the first counter, characterized in that, in order to increase the reliability of the formation, it contains the second, third, quarter, fifth, sixth, seventh and eighth elements OR, the third, fourth, fifth, and sixth pulse formers, the third, fourth, fifth, sixth, and seventh counters, the EXCLUSIVE OR element, and the multiplication unit, the information inputs of the third counter being connected to the module code setting bus, dinene with information inputs of the fourth counter and with the second inputs of the corresponding modulo adders two groups. the device start input is connected to the first inputs of the second, third and fourth elements OR, through the third pulse generator to the first inputs of the fifth, sixth and seventh elements OR, to the resolution input of the fourth counter, the information inputs of the fifth counter are connected to the code setting bus number, the output of the first element OR is connected to the inputs of the first and third pulse shapers, the output of the third pulse shaper is connected to the second inputs of the fourth and fifth elements OR, to the first input of the element EXCLUDE ALTERNE and the sixth-counter synchronization input, the transfer output of the third counter is connected to the second inputs of the third, sixth and seventh elements OR, with the second input of the element DELAYED OR, and through the fourth pulse shaper - with the second input of the second element OR, the first input of the eighth element OR

and the reset input of the sixth counter, the output group of which is connected to the first group of information inputs of the multiplication unit, the second group, whose information inputs are connected to the output group of the seventh counter, the counting input of which is connected to the output of the third RTO element, the output of the fourth ISH element is connected to an enable input of the fifth counter, the outputs of which are connected to the information inputs of the first counter, the output of which is connected to the output of the seventh OR element, the output of the i-ID element. connected to the subtracting input of the third counter, the resolution input of which is connected to the output of the second OR element and the third input of the fifth OR element, the output of the

The fourth counter is connected to the reset inputs of the fifth and seventh counters and is the output of the device forming end, the output of the sixth OR element is connected to the subtractive input of the fourth counter, the clock and my clock generator output is connected to the sync input of the multiplication unit, the resolution input of which is connected to the output of the eighth element OR, the second input of which is connected to the output of the fifth pulse former, the input of which is connected to the output of the element EXCLUSIVE OR, the information output of the multiplying block n summing inputs with the fifth counter, the output end of the multiplier multiplying block is connected to the seventh input tr1vtim IL element.

1

Editor M, Tovtin

Compiled by A, Sirotsk

Tehred L. Serdyukov a, Corrector E, Roshko

Order 3293/50 Circulation 671 Subscription

, VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

F14.2.

Claims (1)

Claim An apparatus for forming Remainder ka for proizvolnrmu modulo the number, comprising first and second schetchyki, AND gate, a first OR element, an OR-HE, a group of adders modulo two, first and second pulses Teli formation ³³ and the clock generator, the output the clock generator is connected to the first input of the AND element, the output of which is connected to the subtracting input of the first counter and to the counting input of the second counter, the second input of the And element is connected to the output of the first OR element and to the input of the first pulse shaper s, the output of which is connected to the reset input of the second counter, the output of the second pulse shaper is connected to the reset input of the second counter, the input of the second pulse shaper is connected to the output of the OR-HE element, the inputs of which are connected to the output of the adders modulo two groups, the first inputs of which are connected to the corresponding outputs of the second counter, which are the outputs of the device, the inputs of the first OR element are connected to the outputs of the first counter, characterized in that, in order to increase the reliability of the formation, it contains second, third, fourth, fifth, sixth, seventh and eighth OR elements, third, fourth, fifth and sixth pulse shapers, third, fourth, fifth, sixth and seventh counters, an EXCLUSIVE OR element and a multiplication unit, the information inputs of the third counter being connected two groups are connected to the information input bus of the module code, two groups are connected to the information inputs of the fourth counter and to the second inputs of the respective adders modulo., the device start input is connected to the first inputs of the second, third and fourth OR elements, through thirds a pulse shaper with the first inputs of the fifth, sixth and seventh OR elements, with a fourth counter resolution input, information inputs of the fifth counter are connected to the number code job bus, the output of the first OR element is connected to the inputs of the first and third pulse shapers, the output of the third pulse shaper is connected to the second the inputs of the fourth and fifth elements OR, with the first input of the element EXCLUSIVE OR and the synchronization input of the sixth counter, the transfer output of the third counter is connected to the second inputs of the the sixth, sixth and seventh OR elements, with the second input of the EXCLUSIVE OR element and through the fourth pulse shaper - with the second input of the second OR element, the first input of the eighth OR element Ί and the reset input of the sixth counter, the group of outputs of which is connected to the first group of information inputs of the multiplication unit, the second group of information inputs of which is connected to the group of outputs of the seventh counter, the counting input of which is connected to the output of the third OR element, the output of the fourth OR element is connected with the seventh resolution input of the fifth counter, the outputs of which are connected to the information inputs of the first counter, whose resolution input is connected to the output of the seventh OR element, the output of the fifth OR element. connected to the subtracting input of the third counter, the enable input of which is connected to the output of the second OR element and the third input of the fifth OR element, the transfer output of the fourth counter is connected to the reset inputs of the fifth and seventh counters and is the output of the end of the device formation, the output of the sixth OR element is connected with the subtracting input of the fourth counter, the output of the clock generator is connected to the synchronizing input of the multiplication unit, the resolution input of which is connected to the output of the eighth OR element, the second input to is connected to the output of the fifth pulse shaper, the input of which is connected to the output of the EXCLUSIVE OR element, the information output of the multiplication block is connected to the summing input of the fifth counter, the output of the multiplication end of the multiplication block is connected to the third input of the seventh OR element.