SU1737442A1 - Arbitrary modulo computing device - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices, as well as in devices for generating elements of finite fields. The purpose of the invention is to expand the scope of application by performing an accumulative summation. The computing device contains, by an arbitrary modulus, an adder 5, a memory register 6, a multiplexer 7, a subtractor 8, a comparison circuit 9, elements OR 10-12, a pulse shaper 13, and a result register 14. 1 il.

Description

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The invention relates to computing and can be used in digital devices, as well as in devices for generating elements of finite fields.

A device is known for generating a residual modulus of arbitrary modulus of a number containing two registers, five OR elements, two comparison circuits, a multiplexer, a delay element, an adder, a group of blocks of AND elements and a block of permanent memory with corresponding links, selected as a prototype.

The disadvantage of this device is the narrow scope, which implies the impossibility of performing accumulative summation.

The purpose of the invention is to expand the scope of application by performing an accumulative summation.

The drawing shows a diagram of the computing device for an arbitrary module.

The computing device for an arbitrary module contains the input of the device number 1, the device zero input 2, the device start input 3, the device module assignment input 4, the adder 5, the memory register 6, the multiplexer 7, the subtractor 8, the comparison circuit 9, the first 10, the second 11 and the third 12 OR elements, the pulse shaper 13, the result register 14, the output 15 of the device result and the output 16 of the device termination signal.

The computing device of an arbitrary module works as follows.

The computing device, using an arbitrary modulus, performs the summation of the numbers arriving in series at its input 1 in the parallel binary code. At the same time, the arrival of each number is accompanied by a pulse applied to the input 3 of the device startup. Before the commencement of the summation, a pulse is applied to the input 2 of the zeroing of the device, which, having passed through the element 12 OR, is fed to the input of the zeroing of the memory register 6, setting the latter to the zero state. After resetting the register 6, the computing device is ready for operation. At the same time, the inputs of the first adder of the adder 5 are affected by the codes of the first number intended for s / mm. The input 4 of the device module assignment during the operation of the computing device is constantly affected by the binary codes of the selected module, which is summed up. In the absence of a single potential at the control input

multiplexer 7 of this output connected its first inputs, otherwise - the second information inputs. When a single impulse device starts up at input 3, the number of the code acting on the first inputs of adder 5 is recorded in register 6. The recording takes place at the front of the pulse coming from the output of element 10 OR at the input of register 6 recording. The 13 pulses form a pulse that triggers the comparison circuit 9. The comparison circuit 9 compares the codes of the numbers from the register output 6 and the inputs 4 of the computing device. If the value of the number acting on the first inputs of the comparison circuit 9 is greater than the value of the module arriving at the second inputs of the comparison circuit 9, then at the end of the comparisons the pulse appears at the output greater than the comparison circuit 9, if the values of the indicated numbers are equal, then the pulse appears at the output It is equal to the comparison circuit 9, in other cases - at the output Less than the comparison circuit 9.

Assume that the value of the number stored in register 6 turned out to be less than the value of the module arriving at input 4 of the computing device. In this case, the impulse to terminate the operation of the comparison circuit 9 appears at the output. Less than the comparison circuit 9. Further, this impulse, passage through the element 11 OR, is fed to the input of the register entry 14 and to the output 16 of the computing device. Under the action of this pulse, register 14 records the contents of register 6. The pulse at output 16 of the device termination signal permits reading the result of the summation recorded in register 14, as well as the arrival of the next number at the input 1 of the number of the computing device. As a result of the arrival of the second number codes, the first inputs of the adder 5 at its outputs form the sum code of this number with the number recorded in register 6. This code goes through the multiplexer 7 to the information inputs of register 6. On the front of the device start pulse, this code is written to register 6 The contents of register b are compared with the value of the selected module P. Suppose that the value of the contents of register 6 is greater than the value of module P. In this case, the comparison circuit 9 gives a pulse to its output More. This pulse triggers subtractor 8, which subtracts the value of module P from the value of the contents of register 6. Upon completion of subtraction, subtractor 8 outputs a pulse to its output, which

to the control input of the multiplexer 7, commutes with its outputs its second inputs, and also, the passage through the element OR 10 writes the contents of the subtractor 8 into the register 6. This same pulse, the passage through the element 11 OR, rewrites the contents of the register 6 into the register 14 and enters to the output 16 of the device termination signal. When the comparison circuit 9 is in operation, a situation may arise when the contents of register 6 are equal to the value of module P acting on input 4 of the computing device. In this case, the comparison circuit 9 gives a pulse to its output, Equals. Consequently, the contents of register 6 are identically equal to zero in a given module P. This pulse, passing through the element OR 11, writes the contents of register b (in this case, zero) to register 14 and arrives at the output 16 of the device termination signal, indicating that the next cycle of summation is complete. When the next number of codes arrives at the input of 1 number and the start pulse at input 3, the operation of the computing device occurs as described. In this case, at the end of each cycle of summation, the sum code received 1 numbers at its input appears at the outputs 15 of the result of the computing device, and the output 16 generates a pulse indicating that the next summation cycle is completed and the device is ready to accept the next number for summation. The full cycle of accumulating summing begins from the moment the pulse is applied to the input 2 of the computing device, and each time after the completion of the summing up, the output of the device termination signal 16 appears the sum of all numbers whose codes are sequentially fed to the device 1 input (accompanied by a trigger pulse to input 3 of the device) according to the selected module P for the given full cycle, the code of which is fed to the inputs 4 of the device. The arrival of the next pulse at the input 2 of the device means the beginning of the next full cycle of accumulating summation, in this case any other module P can be chosen by changing its codes at input 4 or the previous one is left.

The technical and economic efficiency of the proposed computing device consists in expanding its field of application due to the possibility of performing accumulative summation over a given module P.

Invention Formula

Computing device of arbitrary modulus containing memory register, multiplexer, subtractor, comparison circuit, first to third elements

OR and the result register, the input of the device module's job is connected to the input of the subtracable subtractor and the first information input of the comparison circuit, the Output Less than which is connected to the first input of the second OR element, the output of which is connected to the resolution enable input of the result register, whose output is the output of the result devices whose startup input is connected to the first input

the first OR element, the output of which is connected to the write register recording resolution input, the zeroing input of which is connected to the output of the third OR element, the first input of which is connected to the output Equal to the comparison circuit, the difference output of the subtractor is connected to the first information input of the multiplexer, the output of which is connected to the information the memory register input, which is different from the fact that, in order to expand the scope of application by performing accumulative summation, it contains an adder and a pulse shaper, and in number od devices connected to

the input of the first adder term, the output of which is connected to the second information input of the multiplexer, the control input of which is connected to the second inputs of the first and second element

OR and the output of the subtractor, the start input of which is connected to the output of the More comparison circuit, the resolution input of which is connected to the output of the pulse former, the input of which is connected

with the start-up input of the device, the zeroing input of which is connected to the second input of the third element OR, the output of the memory register is connected to the information input of the result register, the input decremented

the subtractor, the input of the second term of the adder and the second information input of the circuit, the comparison, the Output Equal of which is connected to the third input of the second OR element, the output of which is the output

signal termination device.

Claims (1)

5 claims An arbitrary module computing device containing a memory register, a multiplexer, a subtractor, a comparison circuit, from the first to third elements 10 OR and a result register, the input of the device module job being connected to the input of the subtracted subtractor and to the first information input of the comparison circuit, the Less of which is connected with the first input of the second OR element, the output of which is connected to the write enable input of the result register, the output of which is the output of the device result, the start input of which is connected to the first input 20 of the first OR element, the output of which is connected to the write enable input of the memory register, the zeroing input of which is connected to the output of the third OR element, the first input of which is connected to the output 25 As well as the comparison circuit, the subtractor difference output is connected to the first information input of the multiplexer, the output of which It is connected to the information input of the memory register, with the 30th fact that, in order to expand the scope of application due to the accumulative summation, it contains an adder and an impulse generator pulses, and the input of the number of the device is connected to the 35 input of the first term of the adder, the output of which is connected to the second information input of the multiplexer, the control input of which is connected to the second inputs of the first and second element 40 OR and the output end of the subtractor, the start input of which is connected to the output More comparison circuit , the resolution input of which is connected to the output of the pulse shaper, the input of which is connected 45 to the input of the start of the device, the zeroing input of which is connected to the second input of the third OR element, the output the memory register is connected to the information input of the result register, the input of the reduced 50 subtractor, the input of the second term of the Adder and the second information input of the circuit, comparison, the output of which is also connected to the third input of the second OR element, the output of which is the output 55 of the device end signal.