SU1226615A1 - Versions of t-flip-flop - Google Patents

Abstract

The invention relates to a pulse technique and can be used in various scaling schemes. The purpose of the invention is to increase the speed T of the trigger, which is achieved by functional connections between the circuit elements. T-flip-flop according to the first variant contains transistors 1-6, potential clamps 7 and 8, input 9, auxiliary input 10, current source 11, power bus 12 and 13, voltage reference bus 14. Functional diagram of the T-flip-flop according to the second variant is given in the description of the invention. The feedback between the first and second bistable cells is carried out in the first variant of the T-flip-flop by the collector connection of the transistor.4 with the base of the transistor 2. The triggers have, in comparison with the prototype, a 2-fold higher operating frequency and 2 times less tavl kytsy elements. 2 sec. f-ly. 2 Il. / 3 i SL to yu 05 O ate

Description

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The invention relates to a pulse technique and can be used in various scaling schemes. The purpose of the invention is to increase the speed of the T-flip-flop.

Fig. 1 shows the electrical circuit of the T-flip-flop, the first option; figure 2 - Tr is the second option.

T-flip-flop (Fig.)) Contains transistors 1-6 and the first and second clampers 7 and 8 of the potential, the emitters of the first and second transistors are connected to the collector of the third transistor 3, the base of which is connected to Vhbdu 9, the base of the second transistor 2 is connected to the first output the first latch 7 potential, the fourth collector and the base of p of transistors 4 and 5 are connected to the first output of the second latch 8 of potential, the emitters of the fourth and fifth transistors 4 and 5 are connected to the collector of the sixth transistor 6, the base of which is connected to input 10, and the emitter through the current source 11 is connected to the first power supply I2, the collector of the fifth transistor 5 is connected to the second power supply line 13, the base of the fourth transistor 4 is connected to the reference voltage bus 14 and to the base of the first transistor I, connected to the first terminal of the first potential clamp 7, the second terminals of the first and second potential clamp 7 and 8 are connected to the second power bus, the emitter of the third transistor 3 is connected to E1 by a sensor of the sixth transistor 6, and the additional collector of the fourth transistor ra 4 - with the base of the second transistor 2, the collector of which is connected to the first terminal of the second latch 8 of the potential, and output 15.

In the second embodiment, the goal is achieved by the fact that the T-flip-flop (Fig. 2) contains transistors 1-6 (transistors 1 and 6 two-emitter), the first and second latching devices 7 and 8 of the potential, the first emitter of the first and the emitter of the second transistor 1 and 2 are connected with the collector of the third transistor 3, the base of which is connected to the input 9, the callback of the first and the base of the second transistors 1 and 2 are connected to the first output of the first potential fixer 7, the collector of the fourth and the base of the fifth transistors 4 and 5 are connected and connected to the first 261515

The second terminal of potential 8, the fourth emitter of the first transistor 4 and 5 is connected to the collector of the sixth transistor 5, the base of which is connected to an additional output 10, and the emitter is connected to the first power supply bus 12 This transistor 5 is connected to the second power supply bus 13, the base of the fourth transistor is connected to the reference voltage bus 14 and to the base of the first transistor 1, and the second transistors of the first and second clamps 7 and 8

15 potential is connected to the second power supply bus 13, the second emitter of the first transistor 1 is connected to the collector of the sixth transistor 6, the emitter of which is connected to the emitter of the third

20 of transistor 3, and the collector of the second transistor is connected to the first output of the second latch 8 of the potential and the output 15, the second emitter of the fifth transistor 5 can be connected

25 to additional outlet 16.

T-flip-flop potential catchers can be implemented in the form of resistors (Figs. I and 2), or they can be resistive-diode.

30 T-trigger variants contain two bistable cells, each of which is implemented on the basis of a two-step emitter-functional logic element.

j, j A potential is applied to the bus 14 with a level located in the middle between the logic zero levels and the unit of the upper stage of the two-stage logic elements.

4 (1) The direct connection between the first and second bistable cells is provided by the collector connection of transistor 2 to the base of transistor 5.

The feedback between the second and the first bistable cells is implemented in the first T-flip-flop by the collector connection of the transistor 4 with the base of the transistor 2, in the second version - by the emitter connection of the transistor 4 and the transistor.

T-trigger (Fig, 1) works as follows.

In the initial state at the input 9 and the additional input 10 there are logical levels of the lower stage

two-stage logical elements, respectively, the level of logical zero and the level of logical units.

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while the transistor 3 is closed, and the transistor 6 is open. Suppose that in the initial state the transistor 4 is also open. Then the current of the current source 11 will flow through the open transistor 6 and then through the open emitter-collector transitions of the transistor 4, branching into two equal in value, flows through both latch 7 and 8 of the potential.

At the same time on the bases of transistors 2 and 5 and at the output 15 there is a logical level of the upper stage of the two-stage logic element - the level of logical zero, the transistor 5 is closed. The T-trigger is in the zero state.

When the input clock signal is applied at the input 9, a potential is established corresponding to the level of the logical unit, and at the additional input 10 - the corresponding level of the logical zero. Transistor 3 opens and transistor 6 closes.

Since at this point in time the potential of the base of transistor 2 (level of logical zero) is lower than the potential of the base of transistor 1 {threshold voltage level), transistor 2 is in the closed state and transistor 1 is in the open state.

The current set by the current source 14 flows through the open emitter-collector junctions of transistors 3 and 4 and then through the clamp 7 of the potential, maintaining the logic zero level at the base of transistor 2. Since the passage of current through the clamp 8 potential stops, then on the basis of the transistor 5 and the level of the logical unit is set at the output 15. The T-flip-flop switches to a single state.

After the end of the input clock signal at the input 9, the logic zero level is reestablished, and at the additional input 10 - the logic unit level. Transistor 3 closes and transistor 6 opens.

Since at this point in time the potential of the base of the transistor 5 (the level of the logical unit) is higher than the potential of the base of the transistor 4 (the threshold voltage level), the transistor 5 is in the open state and the transistor 4 is in the closed state.

The current source 11 current flows through the open emitter-collector

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transitions of transistors 6 and 5. At the same time, the potential at the base of transistor 5 and at output 15 does not change. The T-trigger remains in a single state.

Since the passage of current through the potential clamp 7 is stopped, a logic unit level is established at the base of transistor 2.

When the next input clock is applied, transistor 3 reopens and transistor 6 closes.

At this point in time, the potential of the base of transistor 2 (the level of the logical unit) is higher than the potential of the base of transistor 1 (the level of the threshold voltage), as a result, transistor 2 is open, and transistor 1 is closed.

The current source I1 current flows through the open emitter-collector transitions of transistors 3 and 2 and then the latch 8 potential. On the base of the transistor 2, the logical unit level is maintained, and on the base of the transistor 5 and the output 15, a logic zero level is set. The trigger returns to the zero state.

After the input clock signal has ended, the transistor 3 closes and the transistor 6 opens.

Since at this point in time the potential of the base of transistor 5 (logic zero level) is lower than the potential of the base of transistor 4 (threshold voltage level), then transistor 5 is in the closed state and transistor 4 is in the open state.

The potential current of the current source 11 is supplied through an open transistor

6and further through the open emitter-collector transitions of the transistor 4, branching into two equal in size, flows through both clamps

7 and 8 potential.

In this case, on the base of the transistor 2 is established, and on the base of the transistor 5 and the output 15, the potential corresponding to the logic zero level is confirmed. The T-trigger remains in the zero state.

According to the second variant, the T-trigger (FIG. 2) works as follows.

In the initial state at the input 9 and at the additional input 10 there are logical levels of the lower stage of two-stage logic elements, respectively, the level of logical zero and the level of logical

units, while the transistor 3 is closed, and the transistor 6 is open.

Let transistor 4 and the first emitter-collector junction of transistor 1 also be open in the initial state. Then the current of current source 11 flows through the open transistor 6 and further, it branches into two equal in value, flows through transistor 4 and potential clamp 8, also through the first emitter-collector junction, transistor 1 and fixator 7 potential.

In this case, at the bases of transistor 2 and 5 and at output 15 there is a logical level of the upper stage of a two-stage logic element - the level of logical zero, the transistor 5 is closed. The T-trigger is in the zero state.

When the input clock signal is applied at the input 9, the potential is set to correspond to the level of the logical unit, and at the additional input 10 - the potential corresponding to the level of the logical zero.

Transistor 3 opens and transistor 6 closes.

Since at this point in time the potential of the base of transistor 2 (level of logic zero) is lower than the potential of the base of transistor 1 (threshold voltage level), then transistor 2 is in the closed state and transistor I is in the open state.

The current of the current source 11 flows through the open transistor 3 and the open second emitter-collector junction of transistor 1 and then through the clamp 7 of the potential, maintaining the logic zero level at the base of transistor 2. Since the passage of current through the clamp 8 potential stops, then on the basis of the transistor 5 and the output 15 is set the level of logical units. The T-flip-flop switches to a single state.

After the end of the input clock, the logic zero level is re-established at input 9, and the logical unit level at the additional input 10. Transistor 3 is closed and transistor 6 opens

Since at this point in time the potential of the base of the transistor 5 (the level of the logical unit) is higher than the potential of the base of the transistors 1 and 4 (the level of the DoroBoro voltage), the transistor

5 is in the open and the transistor

1 and 4 in the closed state.

The current of the current source flows through the open emitter-collector junctions of transistors 6 and 5. At this potential, the base of the transistor 5 and the output 15 does not change. The T-trigger remains in a single state.

Since the passage of current through the potential clamp 7 is stopped, a logic unit level is established at the base of transistor 2.

When the next input clock is applied, transistor 3 reopens and transistor 6 closes.

At this point in time, the potential of the base of transistor 2 (the level of the logical unit) is higher than the potential of the base of transistor 1 (the level of the threshold voltage), as a result of which the transistor

2 is open, and transistor 1 is closed.

The current source I1 current flows through the emitter-collector transitions of transistors 3 and 2 and then through the latch 8 potential. On the base of the transistor 2, the logical unit level is maintained, and on the base of the transistor 5 and the output 15, a logic zero level is set. The T-trigger returns to the zero state.

After the end of the input clock signal, the transistor 3 is closed and the transistor 6 is opened.

Since at this point in time the potential of the base of transistor 5 (logic zero level) is lower than the potential of the base of transistor 4 (threshold voltage level), then transistor 5 is in the closed state and transistor 4 is in the open state.

The current source 11 current flows through the open transistor 6 and further, branching into two equal in value, flows through the transistor 4 and the latch 8 potential, as well as through the first emitter-collector junction of the transistor 1 and latch 7 potential.

In this case, at the base of the transistor 2 is established, and at the base of the transistor 5 and at the output 15, a potential corresponding to a logic zero level is confirmed. The T-trigger remains in the zero state. The functional speed of the T flip-flop determines with the switching time of two bistable cells.

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Thus, the maximum trigger frequency kc / 2 T (, p, where Ter is the average switching time of one bistable cell. In this case, each variant of the T-trigger is implemented on ten elements.

Based on the feature of the T-flip-flop, which is that at the time between the two input clock pulses and when the trigger state is zero, the current of the current source flows simultaneously through both latch 7 and 8 of the potential to achieve maximum workers; The frequencies must be equal to a certain ratio between the switching time of the bistable cells, the duty cycle of the input clock, and the load on the output terminal of the device.

For example, to implement the speed limit in the second T-flip-flop version, with an appropriate design and when the output signal is removed from the additional output 16 of the device, when the first bistable cell switches the time from one to zero state one and a half times the second, and the switching time from zero to one for both bistable cells is the same, the duty cycle of the input clock must be -2.5.

Such a duty cycle of the input clock pulses can be implemented, for example, at the input differential-Hotf amplifier-driver with a shifted relative to the constant component of the input sinusoidal signal, the trigger threshold.

When the T-flip-flop is operating in a wide range of input clock frequencies from a pulse signal of the square wave type, when using resistor potentiators, a modulation of the output signal amplitude of bistable cells occurs.

In cases where this effect is undesirable, it is possible to exclude the output T-flip-flop modulation by connecting the collector of transistor 2 to the additional terminal of the second potential clamp, to the midpoint of the potential clamp 8. For this purpose, you can use the exception of the passage of a portion of the collector current of transistor 2 through a fixed

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8 by connecting an additional second collector of the transistor 2 to the second power line 13.

In the first T-flip-flop version, it is possible to exclude modulation of the amplitude of the output signal also at the output of the first bistable cell. For this, the collector of transistor 1 must be connected to the auxiliary side of the first latch 7 of the potential (to the midpoint of the latch 7 of the potential).

The advantage of the proposed trigger in comparison with the known one is its more than twice the maximum operating frequency. This is due to one and a half times higher functional speed of the proposed trigger, two times fewer components and, accordingly, a simpler design, which significantly reduces the switching time of each bistable cell and increases the speed of the T-trigger.

F o rmula of the invention

I. T-flip-flop, containing an input, an output, six transistors and two potential clamps, emitters of the first and second transistors connected to the collector of the third transistor, the base of the second transistor connected to the first output of the first potential clamp, the collector of the fourth transistor and connected to the first output of the second clamp of the potential, the emitters of the fourth and fifth transistors are connected to the following: with a stopper of the sixth transistor, the emitter of which is connected to the first bus Moreover, the collector of the fifth transistor is connected to the second power bus, the base of the fourth transistor is connected to the reference voltage bus and to the base of the first transistor, the collector of which is connected to the first terminal of the first potential clamp, characterized in that the second terminals of the first transistor and the second clamping potential is connected to the second power bus, the emitter of the third transistor is connected to the emitter of the sixth transistor, the additional collector of the fourth transistor is connected to the BA912266

, Zoy second transistor, collector

which is connected to the first output of the second potential clamp and the output of the T-flip-flop, and the bases of the third and sixth transistors are connected respectively to the inputs and an additional input of the T-flip-flop.

 2. A T-flip-flop containing an input, an output, six transistors and two potential clamps, the first emitter of the first and the emitter of the second transistor are connected to the collector of the third transistor, the collector of the first and the base of the second transistor are connected to the first output of the first potential clamp, the fourth collector and base n In addition, the transistors are connected to the first terminal of the second potential clamp, the fourth emitter and the fifth transistor emitter are connected to the sixth transistor collector 15

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a resistor whose emitter is connected to the first power supply through a current source, the collector of the fifth transistor is connected to the second power supply bus, the base of the fourth transistor is connected to the reference voltage bus and to the base of the first transistor, in order to improve speed, the second terminals the first and second latching potentials are connected to the second power bus, the second emitter of the first transistor is connected to the collector of the sixth transistor, the emitter of which is connected to the emitter of the third transistor, the second collector the first transistor is connected to the first output of the second latch potential and the output of the T-flip-flop, and the base of the third and sixth transistors are connected respectively to the input and the auxiliary input of the T-flip-flop.

Editor N. Dumbass

Compiled by L. Yanov

Tehred L.Oleynik Proofreader E. Roshko

Order 2145/56 Circulation 816 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

Claims (2)

Claim 1. A T-trigger containing an input, an output, six transistors and two potential clamps, emitters of the first and second, transistors are connected to the collector of the third transistor, the base of the second transistor is connected to the first output of the first potential clamp, the collector of the fourth transistor is connected to the base of the fifth transistor and connected to the first output of the second potential clamp, the emitters of the fourth and fifth transistors are connected to the collector of the sixth transistor, the emitter of which is connected through the current source to the first power bus, the collector of the fifth transistor is connected to the second power bus, the base of the fourth transistor is connected to the reference voltage bus and to the base of the first transistor, the collector of which is connected to the first output of the first potential clamp, characterized in that, in order to improve performance, the second conclusions of the first and second potential clamps connected to the second power bus, the emitter of the third transistor is connected to the emitter of the sixth transistor, the additional collector of the fourth transistor is connected with ba1226615 S 'of the second transistor, the collector of which is connected to the first output of the second potential clamp and the output of the T-trigger, and the bases of the third and sixth transistors are connected respectively to the inputs and the additional input of the T-trigger. ‘2. A T-trigger containing an input, an output, six transistors and two potential clamps, the first emitter of the first and the emitter of the second transistor are connected to the collector of the third transistor, the collector of the first and the base of the second transistor are connected to the first output of the first potential clamp, the collector of the fourth and the base of the fifth transistor are connected to the first output of the second potential clamp, the emitter of the fourth and emitter of the fifth transistor are connected to the collector of the sixth transistor, the emitter of which is connected to with a power supply bus, the collector of the fifth transistor is connected to the second power supply bus, 5 the base of the fourth transistor is connected to the reference voltage bus and to the base of the first transistor, characterized in that, in order to improve performance, the second terminals of the first and second potential clamps are connected to the second power bus, the second emitter of the first transistor is connected to the collector of the sixth transistor, the emitter of which is connected to the emitter of the third transistor, the collector of the second transistor is connected to the first output of the second fix ora Ttriggera capacity and output, and the base of the third and sixth 20 transistors are connected respectively to the input and auxiliary input Ttriggera. Fig 2