SU1647873A1 - Hysteretic section - Google Patents

Abstract

The invention relates to a pulse technique and can be used in integrated current-frequency converters, non-linear current-frequency converters, non-linear automation devices. The purpose of the invention is to increase speed and expand the scope. The goal is achieved by the joint action of positive feedback on the differential current through transistors 1, 2.5, 6 and negative feedback on the common-mode current through transistors 5, 6, 7 and resistors 10, 11. The output is carried out using a differential stage transistors 8, 9 and by eliminating the saturation state of the transistors. 1 il.

Description

The invention relates to a pulse technique and can be applied in integrated current-frequency converters, non-linear automation devices, and pulse-width modulators.

The aim of the invention is to increase the speed by eliminating the saturation state of the transistors, the accuracy and the expansion of the application area due to the controllability of the switching threshold.

The invention is illustrated in the drawing.

The device contains transistors 1-9, resistors 10, 11, current sources 12-14, first power bus 15, input buses 16, 17, second power bus 18 and output buses 19, 20. At the same time, the emitters of transistors 1 and 2 are connected to each other. the other, with the bases of the transistors 3, 4 and with the first output of the current source 12, the emitters of the transistors 3, 4 are connected to the first power supply bus 15 and with the second terminals of the current sources 12, 14. The base of the transistor 1 is connected to the base of the transistor 9, the collector of transistor 3 and the transistor of the transistor 6. The base of the transistor 2 is connected to the base of the transistor 8. the collector of transistor 4 and the emitter of the transistor 5. The collector of transistor 1 is connected to the base of transistor 5, the first output of transistor CTOpj 10 and the input bus 16. The collector of the transistor 2 is connected to the base of the transistor 6, the first terminal of the resistor 11 and the bus 17. The second terminals of the resistors 10, 11 are connected to the emitter of the transistor 7. The collectors of the transistors 5, 6 are connected to the base of the transistor 7 and the first terminal 13 m current source. The collector of the transistor 7 is connected to the second terminal of the current source 13 and the power line 18. The emitters of transistors 8, 9 are connected to the first output of current source 14. The collectors of transistors rf, 9 are connected to the output buses 19, 20 of the device. The values of resistors 10, 11 are equal.

The device works as follows.

Transistors 1, 2, 5, and 6 form a positive feedback circuit that can be in one of two stable states: transistor 1 is open, current of source 12 flows through it, resistor 10 and transistor 7, or transistor

ABOUT

4 -vj

00 vj

WITH

2, the current of the source 12 H2 flows through it and the resistor 11. In this case, the collector currents of the transistors 5, 6, 3, A are the same and equal From / 2 (if we ignore the value of the base currents). Accordingly, if transistor 1 is open, current of source 14 flows through transistor 9 and output bus 20, if transistor 2 is open through transistor 8 and bus 19. In any of the stable positions, none of the transistors is saturated (assuming that the difference in incidence drops resistors do not exceed the voltage of the emitter - base transistors).

The common-mode negative feedback loop through the collectors of transistors 5, 6, transistor 7 and resistors 10, 11 compensates for changes in the common-mode input current and current H2.

Switching the link from one position to another occurs when the differential input current is supplied through the input buses 16, 17 at the time when M1, x112.

This happens as follows. Let the transistor 1 be opened at the initial moment. They begin to increase the current through the bus 17. At the same time, the current through the resistor 11 increases, the potential of the base of the transistor b decreases and, respectively, since the currents of transistors 6, 5 are equal to currents of transistors 3,4 and those. in turn, each other, the potential of the base of transistor 2 increases due to the in-phase feedback through transistor 7. At the moment when the base potential of transistor 2 exceeds the base potential of transistor 1, i.e. at 112, an avalanche-like switching of the differential stage in transistors 1, 2 will occur due to the action of positive feedback. At the same time, the cascade in the transistors 8, 9 is switched and the source current begins to flow through the output bus 19. In the same way, switching occurs in the opposite direction.

Thus, during the operation of the link, no transistor enters the saturation state (under the condition of 2 H2Rio 0.6 V), the currents of the open transistors are calculated and are set by sources 12-14 of current. This ensures that there are no delays in switching and allows

transistors in the modes in which they have the highest speed. The switching threshold of the link with an accuracy of the gain of the transistors 1, 2,

5, 6 current is set by current source 12. The output current is also set by the current source 14. The current From allows to optimize the speed of the link.

Claims (1)

Invention Formula The hysteresis element containing the first and second transistors, the collectors of which are connected to the first terminals of the first and second resistors, respectively, are input and output buses that differ from the fact that. in order to increase speed, increase accuracy and expand the application area by providing controllability of the switching threshold, the third, fourth, fifth, sixth, seventh, eighth and ninth transistors, the first, the third third current sources, and the emitters of the first and second transistors are introduced connected to each other, to the bases of the third and fourth transistors and to the first output of the first current source, the emitters of the third and fourth transistors are connected to each other, the second output of the first and third current sources and with the first power bus, the base of the first transistor is connected to the collector of the third, the base of the ninth and emitter of the sixth transistor, the base of the second transistor is connected to the base of the eighth, collector of the fourth and emitter of the fifth transistors, emitters of the eighth and ninth transistors are connected to the first output of the third current source, collectors, respectively, with the first and second output buses of the device, collectors of the first and the second transistors are connected to the bases of the fifth and sixth transistors respectively, to the first and second input buses of the device, the second terminals of the resistors are connected to the emitter of the seventh transistor, the collectors of the fifth and sixth transistors are connected to each other, to the base of the seventh transistor and to the first output of the second current source, the collector of the seventh transistor is connected to the second output a second current source and a second power bus. J3 W-o + CFu. -a