SU1203505A1 - Information input device - Google Patents

Description

dinene with the second input of the second trigger, the second input of the third element AND and the input of the second delay element, the output of which is connected to the first input of the second OR element, the output of which is connected to the second input of the memory unit, the third input of which is connected to the third input of the third OR element,

The invention relates to computing and can be used in information-measuring systems, in automated systems for scientific research, in auto-control systems.

The purpose of the invention is to increase speed by reducing the redundancy of the input information.

The drawing shows a block diagram of the device.

The device contains analog inputs the first trigger 2, information outputs 3, control output 4, control input 5, comparison elements 6, first element OR 7, control block 8, priority block 9, first counter 10, digital-to-analog converter (D / A) 11, a group of 12 elements AND, a group of triggers 13, a second counter 14, a first delay element 15, a memory block 16, a pulse generator 17, a second trigger 18, an element 19, a third element OR a second delay element 21, a second element OR 22.

The device works as follows.

The analog signals are fed to the inputs 1; j - 1n To the input of the counter 10 to the input of the counter 14 through the element OR 20, the control unit 8 delivers a sequence of pulses. In this case, the trigger 18 is cocked into one state, at the output forming a single signal arriving at one of the inputs of the memory block 16.

the output of the pulse generator is the output of the device, the input of the pulse generator is connected to the output of the first trigger, the second input of the second OR element is connected to the third output of the control unit, the first input of which is the control input of the device.

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At the same time, the pulses from the second output of the control unit 8 arrive through the OR element 20 at the input of the counter 14 and sequentially form the increasing address of the memory cell of the block 16. In addition, the pulses also arrive at the delay element 21, and from it through the OR element 22 to the control input Record

The memory unit 16 is recorded and the information generated at its inputs into the memory cell at the address, determined by the contents of the counter 14.

5 Digital-to-analog converter I1 converts the digital code at the output of counter 10 into an analog value, supplied to the inputs of the comparison elements 6, which compare this analog value with the analog values at the inputs. If the indicated values at the inputs of some comparison element 6 coincide, then a single state is established at its output. If at least one of the elements of the comparison is in the single state, then the element OR 7 produces a signal

0 coming into the control unit 8. At the same time, the priority block 9 generates at its outputs the positional and binary codes of the number of the senior according to the set priority. elemental teton: comparing them to all those that are currently in a single state.

From the moment of the occurrence of a single signal at the output of the element OR 7, the control unit 8 stops the detection of:

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the inputs of counters 10 and 14 and generates a signal at the third output, which is fed to the input Record of memory block 16. This signal records the address code corresponding to the input number of the analog value, for which the input analog value is equal to the analog value at the output of the digital-analog converter 11, and formed on the first group of outputs of the priority block 9, into the memory cell of the block. In parallel with the address code, one or zero is also recorded in one of the bits in the memory location, depending on the state of the trigger 18.

At the end of this operation, the control unit 8 generates at the fourth output a signal that goes to the inputs of all the elements AND, as well as to the input of the trigger 18, sets it to the zero state, and to the input of the first element 15 of the deceleration. The second inputs of the And elements are individually connected to the outputs of the priority block 9, at which the position code of the input address of the analog values is formed, for which the input analog value is equal to the analog value at the output of the digital-to-analog converter 11. Therefore, if there is a signal on any of these outputs 9 priority occurs the installation of the corresponding trigger 13 e single state. Due to the fact that the signal from the output of each of these triggers 13 is fed to the inhibit input of the corresponding comparison element 6, it is forcibly set to the zero state and held there until the end of the entire conversion cycle.

At the same time, a delayed pulse from the output of the delay element 15 through the element 19 passes to the input of the counter 20 only when there is no next pulse at the second output of the control unit B. This occurs when a single signal at the output of the element OR 7 is stored.

If a single signal at the output of the element OR 7 is saved, which indicates the presence of a single state of one or more elements 6 of the comparison, then block 8

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The control generates the next signal Recording at the third output and the process of recording information in the memory block 16 described above is repeated with the only difference that from the output of the trigger 18 to the memory block 16 the zero is recorded.

Thus, the zero in this bit of the information word of the memory block 16 encodes a sign that the addresses of the input analog values recorded in the memory correspond to the case of several comparison circuits simultaneously triggered, and the unit encodes the increment sign of the analog value at the output of the digital-analog converter 11 by one quantization step.

In the case when, after the next pulse, one or several comparison elements 6 are triggered at the second output of the control unit 8, the OR element 7 supplies the unit to the third input and the third output unit 8 outputs the control signal Recording to the input of the OR element 22, then with it, thanks to the delay element 21, a delayed signal arrives at the other input of the element OR 22, i.e. Duplication of the signal occurs. Recording does not change the conditions for inputting the input system.

When the signal at the output of the IL 7 element becomes zero, i.e. forcibly using the corresponding trigger 13 is set to the zero state, the last of the comparison elements 6, which were triggered in this conversion step, is allowed to further receive pulses at the input of the counter 10.

The unit state of any flip-flop 13 is maintained until the end of the conversion cycle, which ensures that at the end of each conversion cycle, only the inputs of 1 analog values are memorized, the comparison elements 6 of which are set to one state in this conversion cycle.

At the end of the write cycle, the cells of the memory block 16 are filled with information containing the code of the address of the input analog values 1, -IH and the code of the feature. Moreover, the location of the codes according to the cells of the memory block 16 is strictly ordered from the increasing amplitude of the input analog values 1, - tho since the addressing of the memory cells is performed according to the contents of the counter 14; which is successively increased similarly to the content of counter 10 (successively proportional to the signal at the output of the digital-to-analog converter 11), which is encoded by writing units to one of the information inputs of the memory block 16, or (if several elements of 6 Comparison with one analog signal value at the output of the diffraction analog converter 11) is sequentially increased. As the elements of the comparison elements 6 that have been triggered at a given cycle, are compared with the priority block 9, which is encoded as writing zeros according to the corresponding input arc of memory block 16

The number of cells of the memory block 16 is chosen to be greater than the number of quantization levels by the value ,, equal to the number of input analogue values (input channels), c. so that when all the elements 6 are compared, the memory at the last step of the analog signal of the digital-to-analog converter 11 is sufficient to record the corresponding information ..

At the end of the recording cycle, the control unit 8 generates a reset signal for the flip-flops 13, a 10-G counter (overruns Simultaneously at the edge (edge) of the signal from the start of its counter digit. 10 the counter 14 is set to the zero state, cocked into one state trigger 2 and generator 17 begins to generate a sequence of 1-pulses e arriving at the input of counter 14 and the input of memory block 16. Memory is simultaneously generated with a request for control code 4 of the device.

Ippulsyz coming on. t4g counter input in series uo.lk. the contents of the meter 14 per unit and thereby ensure the sequential reading of the addresses of the memory cells with information stored in the memory block 16 into the external

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The device 5 is connected to the information outputs 3 of the input system.

At the end of the read cycle to the external device, the counter 14 overflows. The signal at the output of its higher bit, applied to the zero input of trigger 2, passes from one state to zero, on which (on the signal front.) Trigger 2 switches to zero. state and the generator 17 stops the issuance of pulses.

The next conversion cycle, analogous to the one described above, begins after the arrival of the signal at input 5 of the input device from an external device.

Thus, in the proposed input system, 5, the conversion results are ENTERED into an external device in the form of codes of addresses of input analog values and the code of the sign indicated above and occupying one bit in the output information code. In this case, in the input sequence, the codes are ordered in such a way that the first input result corresponds to the number (address) of the channel having an amplitude of one quantized level, the second result is the channel number. having an amplitude of two quantized levels, etc., if the bit of the feature contains one. If the sign category is zero; then the address codes correspond to the input channels with the same amplitude. This circumstance makes it possible as the unambiguous decoding by an external device introduces the amplitude of the input analog values 1 ,, - 1; -, without entering information about the am: p litus into it. This is essentially V1– {declining the volume of information entered into an external device. In addition, according to the size of the Amplitude code, the number of output communication lines is reduced, and the memory size of the external device is also reduced by the amount J necessary for storing h Codes equivalent to the input analog values 1 -1.,

The proposed device is advantageous especially in the case when the address code width is less than the amplitude code size, since the number of output communication lines is minimal, and

also in the case of use in systems of tolerance control that implement the operations more or less than the norm. In such control systems, it is important to obtain semi-explicit information about the addresses of input analog quantities, which exceed or do not exceed the specified norms, and the amplitude itself is of secondary importance,

Editor V. Petrash

Compiled by V. Verkhovsky

Tehred I.Astalosh Corrector S. Shekmar

8417/51 Circulation: 709

VNIIPI State Committee of the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PShPatent, Uzhgorod, st. Proektna, 4

Claims (1)

INFORMATION INPUT DEVICE containing comparison elements, first OR element, control unit, priority block, first counter, digital-to-analog converter, group of AND elements, trigger group, the outputs of which are connected to the first inputs of the comparison elements, the second inputs of which are the analog inputs of the device, the second the output of the control unit is connected to the input of the counter, the outputs of which are connected to the inputs of the digital-to-analog converter, the output of which is connected to the third inputs of the comparison elements, the outputs of which are connected respectively to the inputs of the first OR element and the inputs of the priority block, the outputs of the second group of which are connected respectively to the second inputs of the AND elements • of the group whose outputs are connected to the first inputs of the triggers of the group, the second inputs of which are connected to the first output of the control unit, the fourth output of which is connected with the first inputs of the AND elements of the group, the output of the first OR element is connected to the third input of the control unit, the second input of which is connected to the output of the high order of the first counter, which differs that, in order to improve performance by reducing the redundancy of the input information, a second counter, first and second delay elements, a memory unit, a pulse generator, first and second triggers, AND element, second and third OR elements, outputs of the first group of priority block are introduced into it connected to the inputs of the first group of the memory block, the outputs of which are the information outputs of the device, the second output of the second trigger is connected to the first input of the memory block, the inputs of the second group of which are connected to the outputs of the second counter, the first input of which is connected to the high-order output of the first counter and the first input of the first trigger, the second input of which is connected to the high-order output of the second counter, the second input of which is connected to the output of the third OR element, the first input of which is connected to the output of the And element, the first input of which is connected with the first output of the second trigger, the first input of which is connected to the fourth output of the control unit and the input of the first delay element, the output of which is connected to the second input of the And element, the second output of the control unit The line is connected with the second input of the second trigger, the second input of the third AND element and the input of the second delay element, the output of which is connected to the first input of the second OR element, the output of which is connected to the second input of the memory unit, the third input of which is connected to the third input of the third element OR , the output of the pulse generator and is the output of the device, the input of the pulse generator is connected to the output of the first trigger, the second input of the second OR element is connected to the third output. of the control unit, the first input of which is control the input of the device.