SU1198746A1 - Device for demodulating bipulse phase-shift-keyed signals - Google Patents

Description

The invention relates to a pulse, Technique and can be used in communication equipment using pulse-code modulation.

The purpose of the invention is the expansion of the frequency range of a device for demodulating a bi-pulse phase-shifted signal by excluding time-consuming elements from the device. ''

In FIG. Figure 1 shows the functional; H ^ nal diagram of a device for demodulating a bi-pulse} phase-shifted signal; in FIG. 2 - an example of the device on the C-triggers. ’

The device contains comparators 1 and 2, triggers 3 and 4, an OR element 5, input bus 6, common bus 7, output buses 8, 9 and 10, while the output of comparator · 1 is connected to the installation input at 0 of trigger 4, and to the first the input of the installation in 1 trigger 3, the second input of the installation 1, which is connected to the inverse output of the trigger 4, the direct output to the first input of the OR element 5 and the output bus 9, and the inverse output to the first input of the installation to ”1 trigger 4 , the second input of the installation in 1 which is connected to the output of the comparator 2 and the input of the installation to O of trigger 3, and the direct output to 'and with the second input of the OR element 5, the output of which is connected to the output bus 8, and the input bus 6 is connected to the direct and inverse inputs respectively of comparators 1 and 2, the inverse and direct inputs of which are connected to the common bus 7.

Comparators can be performed, for example, on operational differential amplifiers. Triggers can be performed in different ways, for example on short-circuit triggers, to the 5-input of which two-input coincidence elements are connected. Also, triggers can be performed on 0-triggers with synchronization and set inputs at 0, and the 0 inputs of each trigger are connected to the inverse outputs of the opposite trigger, and the synchronization inputs are connected to the outputs of the same comparators (an example of the device implementation on L-triggers is shown in Fig. 2) )

The device works as follows.

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A bi-pulse phase-manipulated signal is supplied to the input bus 6, and the signal in which the positive voltage polarity precedes the negative voltage corresponds to single information. The information of the opposite phase corresponds to zero information, i.e. one in which the negative polarity of the stresses is preceded by a positive.

At the output of the first comparator1, a pulse is generated that coincides in time with a voltage of positive polarity on the input bus 6, and at the output of the second comparator 2, a pulse that coincides in time with a voltage of negative polarity at the input bus 6.

When a single signal arrives at the input bus 6 (i.e., a signal whose phase corresponds to single information), the pulse at the output of comparator 1 precedes the pulse at the output of comparator 2; upon receipt of a zero signal (i.e., a signal whose phase corresponds to zero information), the pulse at the output of comparator 2 precedes the pulse at the output of comparator 1.

When a single signal arrives at the input bus. 6 the pulse from the output of the comparator 1 is fed to

The 5-input of trigger 3 sets this trigger to 1. At the same time, at the in35 output version of trigger 3, a zero level is set, which prevents the passage of a subsequent pulse from the output of comparator 2 to

5-input of the trigger 4. The pulse from the output of the comparator 2 goes directly to the K-input of the trigger 3 and sets it to zero by its trailing edge. At the output of trigger 3, i.e. on the output bus of 9 units, a pulse is generated45, equal in duration to the input signal.

Upon receipt of a zero signal on the input bus 6, the pulse at the output of comparator 2, ahead of the pulse at 5 ° at the output of comparator 1, sets trigger 1 to 1, which is set to 0 by the trailing edge of the output pulse of comparator 1. Thus, when a zero signal arrives, an impulse equal in duration to the input signal is formed on the bus 10 zeros.

At the output of the OR element 5, i.e. on

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output bus 8 cycles, pulses are formed when a signal arrives, regardless of its phase.

If the device uses ϋ-triggers, then when a single (zero) signal arrives at the input bus 6, the pulse from the output of the comparator 1 (2), fed to the synchronization input of the ϋ-trigger 3 (4), sets this 0-trigger to a single state, since at its ϋ input there is a unit potential from the inverse output of the ϋ trigger 4 (3). Then the pulse from the output of the comparator 2 (1), arriving at the K-input of the ϋ-trigger 3 (4), sets it to zero? ·; howl condition; in this case, trigger 4 (3) remains in the zero state, since at the moment of the arrival of the leading edge of the pulse at its Q input, there is a zero potential of the inverse output of the ϋ trigger 3 (4) in its single state at its входе input. Thus, on the output bus 9 (10) when a single (zero) signal arrives at the input bus 6, an output pulse is generated that is equal in duration to the input signal. At the output of the OR element 5 (i.e., on the output bus of 8 clock cycles), a pulse is generated when the input signal arrives, regardless of its phase.

Thus, on the output bus 8, a clock signal is generated, on the output buses 9 and 10, the signals corresponding to 1 and 0.

The device does not have time, and the nodes are running, so it practically does not require configuration. The frequency of its operation is determined by the speed of logical elements: comparators and triggers, therefore, when executed on a modern high-speed element base, a device for demodulating a bi-pulse phase-shifted signal can be used in a wide, frequency range ..

Claims (2)

'1. A device for demodulating a bi-pulse phase-manipulated signal, containing the first and second comparators, the direct input of the first of which 0 and the inverse input of the second are combined, and the outputs are connected respectively to the installation inputs of 1 ”and 0 of the first trigger, the direct output of which is connected to the first output bus 15, characterized in that; that, in order to expand the frequency bottom; device area, it additionally introduces a second trigger and an OR element, and the output of the first comparator 20 is connected to the installation input at 0 of the second trigger, the first installation input at “1” of which is connected to the output of the second comparator, the second installation input to 1 ” - with an inverse 25 output of the first trigger, an inverse output with a second installation input of 1 of the first trigger, and a direct output with a second output bus and the first input of an OR element, the second 30 input of which is connected to the first output bus, and the output is from the third output ? bus, while the combined inputs of both comparators are connected to the input bus, and the second inputs of both comparators are connected to a common device bus · ³⁵ . 2. The device according to claim 1, characterized in that the triggers in it are based on. P-flip-flops, ⁴⁰ to the P-inputs of which are connected the inverse outputs of the opposite <rtriggers, the outputs of the same name comparators to the inputs of the synchronization, and the outputs of the opposite comparators to the inputs of the installation in O ”.